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d3561b7f RR |
1 | #ifndef __ASM_PARAVIRT_H |
2 | #define __ASM_PARAVIRT_H | |
3 | /* Various instructions on x86 need to be replaced for | |
4 | * para-virtualization: those hooks are defined here. */ | |
b239fb25 JF |
5 | |
6 | #ifdef CONFIG_PARAVIRT | |
da181a8b | 7 | #include <asm/page.h> |
658be9d3 | 8 | #include <asm/asm.h> |
d3561b7f | 9 | |
139ec7c4 | 10 | /* Bitmask of what can be clobbered: usually at least eax. */ |
21438f7c GOC |
11 | #define CLBR_NONE 0 |
12 | #define CLBR_EAX (1 << 0) | |
13 | #define CLBR_ECX (1 << 1) | |
14 | #define CLBR_EDX (1 << 2) | |
15 | ||
16 | #ifdef CONFIG_X86_64 | |
17 | #define CLBR_RSI (1 << 3) | |
18 | #define CLBR_RDI (1 << 4) | |
19 | #define CLBR_R8 (1 << 5) | |
20 | #define CLBR_R9 (1 << 6) | |
21 | #define CLBR_R10 (1 << 7) | |
22 | #define CLBR_R11 (1 << 8) | |
23 | #define CLBR_ANY ((1 << 9) - 1) | |
24 | #include <asm/desc_defs.h> | |
25 | #else | |
26 | /* CLBR_ANY should match all regs platform has. For i386, that's just it */ | |
27 | #define CLBR_ANY ((1 << 3) - 1) | |
28 | #endif /* X86_64 */ | |
139ec7c4 | 29 | |
d3561b7f | 30 | #ifndef __ASSEMBLY__ |
3dc494e8 | 31 | #include <linux/types.h> |
d4c10477 | 32 | #include <linux/cpumask.h> |
ce6234b5 | 33 | #include <asm/kmap_types.h> |
8d947344 | 34 | #include <asm/desc_defs.h> |
3dc494e8 | 35 | |
ce6234b5 | 36 | struct page; |
d3561b7f | 37 | struct thread_struct; |
6b68f01b | 38 | struct desc_ptr; |
d3561b7f | 39 | struct tss_struct; |
da181a8b | 40 | struct mm_struct; |
90a0a06a | 41 | struct desc_struct; |
294688c0 | 42 | |
93b1eab3 JF |
43 | /* general info */ |
44 | struct pv_info { | |
d3561b7f | 45 | unsigned int kernel_rpl; |
5311ab62 | 46 | int shared_kernel_pmd; |
93b1eab3 | 47 | int paravirt_enabled; |
d3561b7f | 48 | const char *name; |
93b1eab3 | 49 | }; |
d3561b7f | 50 | |
93b1eab3 | 51 | struct pv_init_ops { |
139ec7c4 | 52 | /* |
93b1eab3 JF |
53 | * Patch may replace one of the defined code sequences with |
54 | * arbitrary code, subject to the same register constraints. | |
55 | * This generally means the code is not free to clobber any | |
56 | * registers other than EAX. The patch function should return | |
57 | * the number of bytes of code generated, as we nop pad the | |
58 | * rest in generic code. | |
139ec7c4 | 59 | */ |
ab144f5e AK |
60 | unsigned (*patch)(u8 type, u16 clobber, void *insnbuf, |
61 | unsigned long addr, unsigned len); | |
139ec7c4 | 62 | |
294688c0 | 63 | /* Basic arch-specific setup */ |
d3561b7f RR |
64 | void (*arch_setup)(void); |
65 | char *(*memory_setup)(void); | |
6996d3b6 JF |
66 | void (*post_allocator_init)(void); |
67 | ||
294688c0 | 68 | /* Print a banner to identify the environment */ |
d3561b7f | 69 | void (*banner)(void); |
93b1eab3 JF |
70 | }; |
71 | ||
72 | ||
8965c1c0 | 73 | struct pv_lazy_ops { |
93b1eab3 | 74 | /* Set deferred update mode, used for batching operations. */ |
8965c1c0 JF |
75 | void (*enter)(void); |
76 | void (*leave)(void); | |
93b1eab3 JF |
77 | }; |
78 | ||
79 | struct pv_time_ops { | |
80 | void (*time_init)(void); | |
d3561b7f | 81 | |
294688c0 | 82 | /* Set and set time of day */ |
d3561b7f RR |
83 | unsigned long (*get_wallclock)(void); |
84 | int (*set_wallclock)(unsigned long); | |
d3561b7f | 85 | |
93b1eab3 JF |
86 | unsigned long long (*sched_clock)(void); |
87 | unsigned long (*get_cpu_khz)(void); | |
88 | }; | |
d3561b7f | 89 | |
93b1eab3 | 90 | struct pv_cpu_ops { |
294688c0 | 91 | /* hooks for various privileged instructions */ |
1a1eecd1 AK |
92 | unsigned long (*get_debugreg)(int regno); |
93 | void (*set_debugreg)(int regno, unsigned long value); | |
d3561b7f | 94 | |
1a1eecd1 | 95 | void (*clts)(void); |
d3561b7f | 96 | |
1a1eecd1 AK |
97 | unsigned long (*read_cr0)(void); |
98 | void (*write_cr0)(unsigned long); | |
d3561b7f | 99 | |
1a1eecd1 AK |
100 | unsigned long (*read_cr4_safe)(void); |
101 | unsigned long (*read_cr4)(void); | |
102 | void (*write_cr4)(unsigned long); | |
d3561b7f | 103 | |
4c9890c2 GOC |
104 | #ifdef CONFIG_X86_64 |
105 | unsigned long (*read_cr8)(void); | |
106 | void (*write_cr8)(unsigned long); | |
107 | #endif | |
108 | ||
294688c0 | 109 | /* Segment descriptor handling */ |
1a1eecd1 | 110 | void (*load_tr_desc)(void); |
6b68f01b GOC |
111 | void (*load_gdt)(const struct desc_ptr *); |
112 | void (*load_idt)(const struct desc_ptr *); | |
113 | void (*store_gdt)(struct desc_ptr *); | |
114 | void (*store_idt)(struct desc_ptr *); | |
1a1eecd1 AK |
115 | void (*set_ldt)(const void *desc, unsigned entries); |
116 | unsigned long (*store_tr)(void); | |
117 | void (*load_tls)(struct thread_struct *t, unsigned int cpu); | |
75b8bb3e GOC |
118 | void (*write_ldt_entry)(struct desc_struct *ldt, int entrynum, |
119 | const void *desc); | |
90a0a06a | 120 | void (*write_gdt_entry)(struct desc_struct *, |
014b15be | 121 | int entrynum, const void *desc, int size); |
8d947344 GOC |
122 | void (*write_idt_entry)(gate_desc *, |
123 | int entrynum, const gate_desc *gate); | |
faca6227 | 124 | void (*load_sp0)(struct tss_struct *tss, struct thread_struct *t); |
d3561b7f | 125 | |
1a1eecd1 | 126 | void (*set_iopl_mask)(unsigned mask); |
93b1eab3 JF |
127 | |
128 | void (*wbinvd)(void); | |
1a1eecd1 | 129 | void (*io_delay)(void); |
d3561b7f | 130 | |
93b1eab3 JF |
131 | /* cpuid emulation, mostly so that caps bits can be disabled */ |
132 | void (*cpuid)(unsigned int *eax, unsigned int *ebx, | |
133 | unsigned int *ecx, unsigned int *edx); | |
134 | ||
135 | /* MSR, PMC and TSR operations. | |
136 | err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */ | |
137 | u64 (*read_msr)(unsigned int msr, int *err); | |
c9dcda5c | 138 | int (*write_msr)(unsigned int msr, unsigned low, unsigned high); |
93b1eab3 JF |
139 | |
140 | u64 (*read_tsc)(void); | |
b8d1fae7 | 141 | u64 (*read_pmc)(int counter); |
e5aaac44 | 142 | unsigned long long (*read_tscp)(unsigned int *aux); |
93b1eab3 | 143 | |
2be29982 JF |
144 | /* |
145 | * Atomically enable interrupts and return to userspace. This | |
146 | * is only ever used to return to 32-bit processes; in a | |
147 | * 64-bit kernel, it's used for 32-on-64 compat processes, but | |
148 | * never native 64-bit processes. (Jump, not call.) | |
149 | */ | |
d75cd22f | 150 | void (*irq_enable_sysexit)(void); |
2be29982 JF |
151 | |
152 | /* | |
153 | * Switch to usermode gs and return to 64-bit usermode using | |
154 | * sysret. Only used in 64-bit kernels to return to 64-bit | |
155 | * processes. Usermode register state, including %rsp, must | |
156 | * already be restored. | |
157 | */ | |
158 | void (*usergs_sysret64)(void); | |
159 | ||
160 | /* | |
161 | * Switch to usermode gs and return to 32-bit usermode using | |
162 | * sysret. Used to return to 32-on-64 compat processes. | |
163 | * Other usermode register state, including %esp, must already | |
164 | * be restored. | |
165 | */ | |
166 | void (*usergs_sysret32)(void); | |
167 | ||
168 | /* Normal iret. Jump to this with the standard iret stack | |
169 | frame set up. */ | |
93b1eab3 | 170 | void (*iret)(void); |
8965c1c0 | 171 | |
e801f864 GOC |
172 | void (*swapgs)(void); |
173 | ||
8965c1c0 | 174 | struct pv_lazy_ops lazy_mode; |
93b1eab3 JF |
175 | }; |
176 | ||
177 | struct pv_irq_ops { | |
178 | void (*init_IRQ)(void); | |
179 | ||
294688c0 | 180 | /* |
93b1eab3 JF |
181 | * Get/set interrupt state. save_fl and restore_fl are only |
182 | * expected to use X86_EFLAGS_IF; all other bits | |
183 | * returned from save_fl are undefined, and may be ignored by | |
184 | * restore_fl. | |
294688c0 | 185 | */ |
93b1eab3 JF |
186 | unsigned long (*save_fl)(void); |
187 | void (*restore_fl)(unsigned long); | |
188 | void (*irq_disable)(void); | |
189 | void (*irq_enable)(void); | |
190 | void (*safe_halt)(void); | |
191 | void (*halt)(void); | |
192 | }; | |
d6dd61c8 | 193 | |
93b1eab3 | 194 | struct pv_apic_ops { |
13623d79 | 195 | #ifdef CONFIG_X86_LOCAL_APIC |
294688c0 JF |
196 | /* |
197 | * Direct APIC operations, principally for VMI. Ideally | |
198 | * these shouldn't be in this interface. | |
199 | */ | |
42e0a9aa TG |
200 | void (*apic_write)(unsigned long reg, u32 v); |
201 | void (*apic_write_atomic)(unsigned long reg, u32 v); | |
202 | u32 (*apic_read)(unsigned long reg); | |
bbab4f3b ZA |
203 | void (*setup_boot_clock)(void); |
204 | void (*setup_secondary_clock)(void); | |
294688c0 JF |
205 | |
206 | void (*startup_ipi_hook)(int phys_apicid, | |
207 | unsigned long start_eip, | |
208 | unsigned long start_esp); | |
13623d79 | 209 | #endif |
93b1eab3 JF |
210 | }; |
211 | ||
212 | struct pv_mmu_ops { | |
213 | /* | |
214 | * Called before/after init_mm pagetable setup. setup_start | |
215 | * may reset %cr3, and may pre-install parts of the pagetable; | |
216 | * pagetable setup is expected to preserve any existing | |
217 | * mapping. | |
218 | */ | |
219 | void (*pagetable_setup_start)(pgd_t *pgd_base); | |
220 | void (*pagetable_setup_done)(pgd_t *pgd_base); | |
221 | ||
222 | unsigned long (*read_cr2)(void); | |
223 | void (*write_cr2)(unsigned long); | |
224 | ||
225 | unsigned long (*read_cr3)(void); | |
226 | void (*write_cr3)(unsigned long); | |
227 | ||
228 | /* | |
229 | * Hooks for intercepting the creation/use/destruction of an | |
230 | * mm_struct. | |
231 | */ | |
232 | void (*activate_mm)(struct mm_struct *prev, | |
233 | struct mm_struct *next); | |
234 | void (*dup_mmap)(struct mm_struct *oldmm, | |
235 | struct mm_struct *mm); | |
236 | void (*exit_mmap)(struct mm_struct *mm); | |
237 | ||
13623d79 | 238 | |
294688c0 | 239 | /* TLB operations */ |
1a1eecd1 AK |
240 | void (*flush_tlb_user)(void); |
241 | void (*flush_tlb_kernel)(void); | |
f8822f42 | 242 | void (*flush_tlb_single)(unsigned long addr); |
d4c10477 JF |
243 | void (*flush_tlb_others)(const cpumask_t *cpus, struct mm_struct *mm, |
244 | unsigned long va); | |
1a1eecd1 | 245 | |
eba0045f JF |
246 | /* Hooks for allocating and freeing a pagetable top-level */ |
247 | int (*pgd_alloc)(struct mm_struct *mm); | |
248 | void (*pgd_free)(struct mm_struct *mm, pgd_t *pgd); | |
249 | ||
250 | /* | |
251 | * Hooks for allocating/releasing pagetable pages when they're | |
252 | * attached to a pagetable | |
253 | */ | |
6944a9c8 JF |
254 | void (*alloc_pte)(struct mm_struct *mm, u32 pfn); |
255 | void (*alloc_pmd)(struct mm_struct *mm, u32 pfn); | |
256 | void (*alloc_pmd_clone)(u32 pfn, u32 clonepfn, u32 start, u32 count); | |
2761fa09 | 257 | void (*alloc_pud)(struct mm_struct *mm, u32 pfn); |
6944a9c8 JF |
258 | void (*release_pte)(u32 pfn); |
259 | void (*release_pmd)(u32 pfn); | |
2761fa09 | 260 | void (*release_pud)(u32 pfn); |
1a1eecd1 | 261 | |
294688c0 | 262 | /* Pagetable manipulation functions */ |
1a1eecd1 | 263 | void (*set_pte)(pte_t *ptep, pte_t pteval); |
294688c0 JF |
264 | void (*set_pte_at)(struct mm_struct *mm, unsigned long addr, |
265 | pte_t *ptep, pte_t pteval); | |
1a1eecd1 | 266 | void (*set_pmd)(pmd_t *pmdp, pmd_t pmdval); |
49cd740b JP |
267 | void (*pte_update)(struct mm_struct *mm, unsigned long addr, |
268 | pte_t *ptep); | |
294688c0 JF |
269 | void (*pte_update_defer)(struct mm_struct *mm, |
270 | unsigned long addr, pte_t *ptep); | |
3dc494e8 | 271 | |
08b882c6 JF |
272 | pte_t (*ptep_modify_prot_start)(struct mm_struct *mm, unsigned long addr, |
273 | pte_t *ptep); | |
274 | void (*ptep_modify_prot_commit)(struct mm_struct *mm, unsigned long addr, | |
275 | pte_t *ptep, pte_t pte); | |
276 | ||
5b8dd1e9 | 277 | pteval_t (*pte_val)(pte_t); |
a15af1c9 | 278 | pteval_t (*pte_flags)(pte_t); |
5b8dd1e9 JF |
279 | pte_t (*make_pte)(pteval_t pte); |
280 | ||
281 | pgdval_t (*pgd_val)(pgd_t); | |
282 | pgd_t (*make_pgd)(pgdval_t pgd); | |
283 | ||
284 | #if PAGETABLE_LEVELS >= 3 | |
da181a8b | 285 | #ifdef CONFIG_X86_PAE |
1a1eecd1 | 286 | void (*set_pte_atomic)(pte_t *ptep, pte_t pteval); |
93b1eab3 JF |
287 | void (*set_pte_present)(struct mm_struct *mm, unsigned long addr, |
288 | pte_t *ptep, pte_t pte); | |
49cd740b JP |
289 | void (*pte_clear)(struct mm_struct *mm, unsigned long addr, |
290 | pte_t *ptep); | |
1a1eecd1 | 291 | void (*pmd_clear)(pmd_t *pmdp); |
3dc494e8 | 292 | |
5b8dd1e9 | 293 | #endif /* CONFIG_X86_PAE */ |
3dc494e8 | 294 | |
5b8dd1e9 | 295 | void (*set_pud)(pud_t *pudp, pud_t pudval); |
3dc494e8 | 296 | |
5b8dd1e9 JF |
297 | pmdval_t (*pmd_val)(pmd_t); |
298 | pmd_t (*make_pmd)(pmdval_t pmd); | |
299 | ||
300 | #if PAGETABLE_LEVELS == 4 | |
301 | pudval_t (*pud_val)(pud_t); | |
302 | pud_t (*make_pud)(pudval_t pud); | |
9042219c EH |
303 | |
304 | void (*set_pgd)(pgd_t *pudp, pgd_t pgdval); | |
5b8dd1e9 JF |
305 | #endif /* PAGETABLE_LEVELS == 4 */ |
306 | #endif /* PAGETABLE_LEVELS >= 3 */ | |
da181a8b | 307 | |
93b1eab3 JF |
308 | #ifdef CONFIG_HIGHPTE |
309 | void *(*kmap_atomic_pte)(struct page *page, enum km_type type); | |
310 | #endif | |
8965c1c0 JF |
311 | |
312 | struct pv_lazy_ops lazy_mode; | |
aeaaa59c JF |
313 | |
314 | /* dom0 ops */ | |
315 | ||
316 | /* Sometimes the physical address is a pfn, and sometimes its | |
317 | an mfn. We can tell which is which from the index. */ | |
318 | void (*set_fixmap)(unsigned /* enum fixed_addresses */ idx, | |
319 | unsigned long phys, pgprot_t flags); | |
93b1eab3 | 320 | }; |
9226d125 | 321 | |
93b1eab3 JF |
322 | /* This contains all the paravirt structures: we get a convenient |
323 | * number for each function using the offset which we use to indicate | |
324 | * what to patch. */ | |
49cd740b | 325 | struct paravirt_patch_template { |
93b1eab3 | 326 | struct pv_init_ops pv_init_ops; |
93b1eab3 JF |
327 | struct pv_time_ops pv_time_ops; |
328 | struct pv_cpu_ops pv_cpu_ops; | |
329 | struct pv_irq_ops pv_irq_ops; | |
330 | struct pv_apic_ops pv_apic_ops; | |
331 | struct pv_mmu_ops pv_mmu_ops; | |
d3561b7f RR |
332 | }; |
333 | ||
93b1eab3 JF |
334 | extern struct pv_info pv_info; |
335 | extern struct pv_init_ops pv_init_ops; | |
93b1eab3 JF |
336 | extern struct pv_time_ops pv_time_ops; |
337 | extern struct pv_cpu_ops pv_cpu_ops; | |
338 | extern struct pv_irq_ops pv_irq_ops; | |
339 | extern struct pv_apic_ops pv_apic_ops; | |
340 | extern struct pv_mmu_ops pv_mmu_ops; | |
d3561b7f | 341 | |
d5822035 | 342 | #define PARAVIRT_PATCH(x) \ |
93b1eab3 | 343 | (offsetof(struct paravirt_patch_template, x) / sizeof(void *)) |
d5822035 | 344 | |
93b1eab3 JF |
345 | #define paravirt_type(op) \ |
346 | [paravirt_typenum] "i" (PARAVIRT_PATCH(op)), \ | |
347 | [paravirt_opptr] "m" (op) | |
d5822035 JF |
348 | #define paravirt_clobber(clobber) \ |
349 | [paravirt_clobber] "i" (clobber) | |
350 | ||
294688c0 JF |
351 | /* |
352 | * Generate some code, and mark it as patchable by the | |
353 | * apply_paravirt() alternate instruction patcher. | |
354 | */ | |
d5822035 JF |
355 | #define _paravirt_alt(insn_string, type, clobber) \ |
356 | "771:\n\t" insn_string "\n" "772:\n" \ | |
357 | ".pushsection .parainstructions,\"a\"\n" \ | |
658be9d3 GOC |
358 | _ASM_ALIGN "\n" \ |
359 | _ASM_PTR " 771b\n" \ | |
d5822035 JF |
360 | " .byte " type "\n" \ |
361 | " .byte 772b-771b\n" \ | |
362 | " .short " clobber "\n" \ | |
363 | ".popsection\n" | |
364 | ||
294688c0 | 365 | /* Generate patchable code, with the default asm parameters. */ |
f8822f42 | 366 | #define paravirt_alt(insn_string) \ |
d5822035 JF |
367 | _paravirt_alt(insn_string, "%c[paravirt_typenum]", "%c[paravirt_clobber]") |
368 | ||
2f485ef5 GOC |
369 | /* Simple instruction patching code. */ |
370 | #define DEF_NATIVE(ops, name, code) \ | |
371 | extern const char start_##ops##_##name[], end_##ops##_##name[]; \ | |
372 | asm("start_" #ops "_" #name ": " code "; end_" #ops "_" #name ":") | |
373 | ||
63f70270 JF |
374 | unsigned paravirt_patch_nop(void); |
375 | unsigned paravirt_patch_ignore(unsigned len); | |
ab144f5e AK |
376 | unsigned paravirt_patch_call(void *insnbuf, |
377 | const void *target, u16 tgt_clobbers, | |
378 | unsigned long addr, u16 site_clobbers, | |
63f70270 | 379 | unsigned len); |
93b1eab3 | 380 | unsigned paravirt_patch_jmp(void *insnbuf, const void *target, |
ab144f5e AK |
381 | unsigned long addr, unsigned len); |
382 | unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf, | |
383 | unsigned long addr, unsigned len); | |
63f70270 | 384 | |
ab144f5e | 385 | unsigned paravirt_patch_insns(void *insnbuf, unsigned len, |
63f70270 JF |
386 | const char *start, const char *end); |
387 | ||
2f485ef5 GOC |
388 | unsigned native_patch(u8 type, u16 clobbers, void *ibuf, |
389 | unsigned long addr, unsigned len); | |
390 | ||
d572929c | 391 | int paravirt_disable_iospace(void); |
63f70270 | 392 | |
294688c0 JF |
393 | /* |
394 | * This generates an indirect call based on the operation type number. | |
395 | * The type number, computed in PARAVIRT_PATCH, is derived from the | |
93b1eab3 JF |
396 | * offset into the paravirt_patch_template structure, and can therefore be |
397 | * freely converted back into a structure offset. | |
294688c0 | 398 | */ |
93b1eab3 | 399 | #define PARAVIRT_CALL "call *%[paravirt_opptr];" |
294688c0 JF |
400 | |
401 | /* | |
93b1eab3 JF |
402 | * These macros are intended to wrap calls through one of the paravirt |
403 | * ops structs, so that they can be later identified and patched at | |
294688c0 JF |
404 | * runtime. |
405 | * | |
406 | * Normally, a call to a pv_op function is a simple indirect call: | |
a4746364 | 407 | * (pv_op_struct.operations)(args...). |
294688c0 JF |
408 | * |
409 | * Unfortunately, this is a relatively slow operation for modern CPUs, | |
410 | * because it cannot necessarily determine what the destination | |
411 | * address is. In this case, the address is a runtime constant, so at | |
412 | * the very least we can patch the call to e a simple direct call, or | |
413 | * ideally, patch an inline implementation into the callsite. (Direct | |
414 | * calls are essentially free, because the call and return addresses | |
415 | * are completely predictable.) | |
416 | * | |
a4746364 | 417 | * For i386, these macros rely on the standard gcc "regparm(3)" calling |
294688c0 JF |
418 | * convention, in which the first three arguments are placed in %eax, |
419 | * %edx, %ecx (in that order), and the remaining arguments are placed | |
420 | * on the stack. All caller-save registers (eax,edx,ecx) are expected | |
421 | * to be modified (either clobbered or used for return values). | |
a4746364 GOC |
422 | * X86_64, on the other hand, already specifies a register-based calling |
423 | * conventions, returning at %rax, with parameteres going on %rdi, %rsi, | |
424 | * %rdx, and %rcx. Note that for this reason, x86_64 does not need any | |
425 | * special handling for dealing with 4 arguments, unlike i386. | |
426 | * However, x86_64 also have to clobber all caller saved registers, which | |
427 | * unfortunately, are quite a bit (r8 - r11) | |
294688c0 JF |
428 | * |
429 | * The call instruction itself is marked by placing its start address | |
430 | * and size into the .parainstructions section, so that | |
431 | * apply_paravirt() in arch/i386/kernel/alternative.c can do the | |
93b1eab3 | 432 | * appropriate patching under the control of the backend pv_init_ops |
294688c0 JF |
433 | * implementation. |
434 | * | |
435 | * Unfortunately there's no way to get gcc to generate the args setup | |
436 | * for the call, and then allow the call itself to be generated by an | |
437 | * inline asm. Because of this, we must do the complete arg setup and | |
438 | * return value handling from within these macros. This is fairly | |
439 | * cumbersome. | |
440 | * | |
441 | * There are 5 sets of PVOP_* macros for dealing with 0-4 arguments. | |
442 | * It could be extended to more arguments, but there would be little | |
443 | * to be gained from that. For each number of arguments, there are | |
444 | * the two VCALL and CALL variants for void and non-void functions. | |
445 | * | |
446 | * When there is a return value, the invoker of the macro must specify | |
447 | * the return type. The macro then uses sizeof() on that type to | |
448 | * determine whether its a 32 or 64 bit value, and places the return | |
449 | * in the right register(s) (just %eax for 32-bit, and %edx:%eax for | |
a4746364 GOC |
450 | * 64-bit). For x86_64 machines, it just returns at %rax regardless of |
451 | * the return value size. | |
294688c0 JF |
452 | * |
453 | * 64-bit arguments are passed as a pair of adjacent 32-bit arguments | |
a4746364 GOC |
454 | * i386 also passes 64-bit arguments as a pair of adjacent 32-bit arguments |
455 | * in low,high order | |
294688c0 JF |
456 | * |
457 | * Small structures are passed and returned in registers. The macro | |
458 | * calling convention can't directly deal with this, so the wrapper | |
459 | * functions must do this. | |
460 | * | |
461 | * These PVOP_* macros are only defined within this header. This | |
462 | * means that all uses must be wrapped in inline functions. This also | |
463 | * makes sure the incoming and outgoing types are always correct. | |
464 | */ | |
a4746364 GOC |
465 | #ifdef CONFIG_X86_32 |
466 | #define PVOP_VCALL_ARGS unsigned long __eax, __edx, __ecx | |
467 | #define PVOP_CALL_ARGS PVOP_VCALL_ARGS | |
468 | #define PVOP_VCALL_CLOBBERS "=a" (__eax), "=d" (__edx), \ | |
469 | "=c" (__ecx) | |
470 | #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS | |
471 | #define EXTRA_CLOBBERS | |
472 | #define VEXTRA_CLOBBERS | |
473 | #else | |
474 | #define PVOP_VCALL_ARGS unsigned long __edi, __esi, __edx, __ecx | |
475 | #define PVOP_CALL_ARGS PVOP_VCALL_ARGS, __eax | |
476 | #define PVOP_VCALL_CLOBBERS "=D" (__edi), \ | |
477 | "=S" (__esi), "=d" (__edx), \ | |
478 | "=c" (__ecx) | |
479 | ||
480 | #define PVOP_CALL_CLOBBERS PVOP_VCALL_CLOBBERS, "=a" (__eax) | |
481 | ||
482 | #define EXTRA_CLOBBERS , "r8", "r9", "r10", "r11" | |
483 | #define VEXTRA_CLOBBERS , "rax", "r8", "r9", "r10", "r11" | |
484 | #endif | |
485 | ||
97349135 JF |
486 | #ifdef CONFIG_PARAVIRT_DEBUG |
487 | #define PVOP_TEST_NULL(op) BUG_ON(op == NULL) | |
488 | #else | |
489 | #define PVOP_TEST_NULL(op) ((void)op) | |
490 | #endif | |
491 | ||
1a45b7aa | 492 | #define __PVOP_CALL(rettype, op, pre, post, ...) \ |
f8822f42 | 493 | ({ \ |
1a45b7aa | 494 | rettype __ret; \ |
a4746364 | 495 | PVOP_CALL_ARGS; \ |
97349135 | 496 | PVOP_TEST_NULL(op); \ |
a4746364 GOC |
497 | /* This is 32-bit specific, but is okay in 64-bit */ \ |
498 | /* since this condition will never hold */ \ | |
1a45b7aa JF |
499 | if (sizeof(rettype) > sizeof(unsigned long)) { \ |
500 | asm volatile(pre \ | |
501 | paravirt_alt(PARAVIRT_CALL) \ | |
502 | post \ | |
a4746364 | 503 | : PVOP_CALL_CLOBBERS \ |
1a45b7aa JF |
504 | : paravirt_type(op), \ |
505 | paravirt_clobber(CLBR_ANY), \ | |
506 | ##__VA_ARGS__ \ | |
a4746364 | 507 | : "memory", "cc" EXTRA_CLOBBERS); \ |
1a45b7aa | 508 | __ret = (rettype)((((u64)__edx) << 32) | __eax); \ |
f8822f42 | 509 | } else { \ |
1a45b7aa | 510 | asm volatile(pre \ |
f8822f42 | 511 | paravirt_alt(PARAVIRT_CALL) \ |
1a45b7aa | 512 | post \ |
a4746364 | 513 | : PVOP_CALL_CLOBBERS \ |
1a45b7aa JF |
514 | : paravirt_type(op), \ |
515 | paravirt_clobber(CLBR_ANY), \ | |
516 | ##__VA_ARGS__ \ | |
a4746364 | 517 | : "memory", "cc" EXTRA_CLOBBERS); \ |
1a45b7aa | 518 | __ret = (rettype)__eax; \ |
f8822f42 JF |
519 | } \ |
520 | __ret; \ | |
521 | }) | |
1a45b7aa | 522 | #define __PVOP_VCALL(op, pre, post, ...) \ |
f8822f42 | 523 | ({ \ |
a4746364 | 524 | PVOP_VCALL_ARGS; \ |
97349135 | 525 | PVOP_TEST_NULL(op); \ |
1a45b7aa | 526 | asm volatile(pre \ |
f8822f42 | 527 | paravirt_alt(PARAVIRT_CALL) \ |
1a45b7aa | 528 | post \ |
a4746364 | 529 | : PVOP_VCALL_CLOBBERS \ |
1a45b7aa JF |
530 | : paravirt_type(op), \ |
531 | paravirt_clobber(CLBR_ANY), \ | |
532 | ##__VA_ARGS__ \ | |
a4746364 | 533 | : "memory", "cc" VEXTRA_CLOBBERS); \ |
f8822f42 JF |
534 | }) |
535 | ||
1a45b7aa JF |
536 | #define PVOP_CALL0(rettype, op) \ |
537 | __PVOP_CALL(rettype, op, "", "") | |
538 | #define PVOP_VCALL0(op) \ | |
539 | __PVOP_VCALL(op, "", "") | |
540 | ||
541 | #define PVOP_CALL1(rettype, op, arg1) \ | |
a4746364 | 542 | __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1))) |
1a45b7aa | 543 | #define PVOP_VCALL1(op, arg1) \ |
a4746364 | 544 | __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1))) |
1a45b7aa JF |
545 | |
546 | #define PVOP_CALL2(rettype, op, arg1, arg2) \ | |
a4746364 GOC |
547 | __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \ |
548 | "1" ((unsigned long)(arg2))) | |
1a45b7aa | 549 | #define PVOP_VCALL2(op, arg1, arg2) \ |
a4746364 GOC |
550 | __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \ |
551 | "1" ((unsigned long)(arg2))) | |
1a45b7aa JF |
552 | |
553 | #define PVOP_CALL3(rettype, op, arg1, arg2, arg3) \ | |
a4746364 GOC |
554 | __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \ |
555 | "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3))) | |
1a45b7aa | 556 | #define PVOP_VCALL3(op, arg1, arg2, arg3) \ |
a4746364 GOC |
557 | __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \ |
558 | "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3))) | |
1a45b7aa | 559 | |
a4746364 GOC |
560 | /* This is the only difference in x86_64. We can make it much simpler */ |
561 | #ifdef CONFIG_X86_32 | |
1a45b7aa JF |
562 | #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \ |
563 | __PVOP_CALL(rettype, op, \ | |
564 | "push %[_arg4];", "lea 4(%%esp),%%esp;", \ | |
565 | "0" ((u32)(arg1)), "1" ((u32)(arg2)), \ | |
566 | "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4))) | |
567 | #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \ | |
568 | __PVOP_VCALL(op, \ | |
569 | "push %[_arg4];", "lea 4(%%esp),%%esp;", \ | |
570 | "0" ((u32)(arg1)), "1" ((u32)(arg2)), \ | |
571 | "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4))) | |
a4746364 GOC |
572 | #else |
573 | #define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4) \ | |
574 | __PVOP_CALL(rettype, op, "", "", "0" ((unsigned long)(arg1)), \ | |
575 | "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \ | |
576 | "3"((unsigned long)(arg4))) | |
577 | #define PVOP_VCALL4(op, arg1, arg2, arg3, arg4) \ | |
578 | __PVOP_VCALL(op, "", "", "0" ((unsigned long)(arg1)), \ | |
579 | "1"((unsigned long)(arg2)), "2"((unsigned long)(arg3)), \ | |
580 | "3"((unsigned long)(arg4))) | |
581 | #endif | |
1a45b7aa | 582 | |
f8822f42 JF |
583 | static inline int paravirt_enabled(void) |
584 | { | |
93b1eab3 | 585 | return pv_info.paravirt_enabled; |
f8822f42 | 586 | } |
d3561b7f | 587 | |
faca6227 | 588 | static inline void load_sp0(struct tss_struct *tss, |
d3561b7f RR |
589 | struct thread_struct *thread) |
590 | { | |
faca6227 | 591 | PVOP_VCALL2(pv_cpu_ops.load_sp0, tss, thread); |
d3561b7f RR |
592 | } |
593 | ||
93b1eab3 | 594 | #define ARCH_SETUP pv_init_ops.arch_setup(); |
d3561b7f RR |
595 | static inline unsigned long get_wallclock(void) |
596 | { | |
93b1eab3 | 597 | return PVOP_CALL0(unsigned long, pv_time_ops.get_wallclock); |
d3561b7f RR |
598 | } |
599 | ||
600 | static inline int set_wallclock(unsigned long nowtime) | |
601 | { | |
93b1eab3 | 602 | return PVOP_CALL1(int, pv_time_ops.set_wallclock, nowtime); |
d3561b7f RR |
603 | } |
604 | ||
e30fab3a | 605 | static inline void (*choose_time_init(void))(void) |
d3561b7f | 606 | { |
93b1eab3 | 607 | return pv_time_ops.time_init; |
d3561b7f RR |
608 | } |
609 | ||
610 | /* The paravirtualized CPUID instruction. */ | |
611 | static inline void __cpuid(unsigned int *eax, unsigned int *ebx, | |
612 | unsigned int *ecx, unsigned int *edx) | |
613 | { | |
93b1eab3 | 614 | PVOP_VCALL4(pv_cpu_ops.cpuid, eax, ebx, ecx, edx); |
d3561b7f RR |
615 | } |
616 | ||
617 | /* | |
618 | * These special macros can be used to get or set a debugging register | |
619 | */ | |
f8822f42 JF |
620 | static inline unsigned long paravirt_get_debugreg(int reg) |
621 | { | |
93b1eab3 | 622 | return PVOP_CALL1(unsigned long, pv_cpu_ops.get_debugreg, reg); |
f8822f42 JF |
623 | } |
624 | #define get_debugreg(var, reg) var = paravirt_get_debugreg(reg) | |
625 | static inline void set_debugreg(unsigned long val, int reg) | |
626 | { | |
93b1eab3 | 627 | PVOP_VCALL2(pv_cpu_ops.set_debugreg, reg, val); |
f8822f42 | 628 | } |
d3561b7f | 629 | |
f8822f42 JF |
630 | static inline void clts(void) |
631 | { | |
93b1eab3 | 632 | PVOP_VCALL0(pv_cpu_ops.clts); |
f8822f42 | 633 | } |
d3561b7f | 634 | |
f8822f42 JF |
635 | static inline unsigned long read_cr0(void) |
636 | { | |
93b1eab3 | 637 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr0); |
f8822f42 | 638 | } |
d3561b7f | 639 | |
f8822f42 JF |
640 | static inline void write_cr0(unsigned long x) |
641 | { | |
93b1eab3 | 642 | PVOP_VCALL1(pv_cpu_ops.write_cr0, x); |
f8822f42 JF |
643 | } |
644 | ||
645 | static inline unsigned long read_cr2(void) | |
646 | { | |
93b1eab3 | 647 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr2); |
f8822f42 JF |
648 | } |
649 | ||
650 | static inline void write_cr2(unsigned long x) | |
651 | { | |
93b1eab3 | 652 | PVOP_VCALL1(pv_mmu_ops.write_cr2, x); |
f8822f42 JF |
653 | } |
654 | ||
655 | static inline unsigned long read_cr3(void) | |
656 | { | |
93b1eab3 | 657 | return PVOP_CALL0(unsigned long, pv_mmu_ops.read_cr3); |
f8822f42 | 658 | } |
d3561b7f | 659 | |
f8822f42 JF |
660 | static inline void write_cr3(unsigned long x) |
661 | { | |
93b1eab3 | 662 | PVOP_VCALL1(pv_mmu_ops.write_cr3, x); |
f8822f42 | 663 | } |
d3561b7f | 664 | |
f8822f42 JF |
665 | static inline unsigned long read_cr4(void) |
666 | { | |
93b1eab3 | 667 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4); |
f8822f42 JF |
668 | } |
669 | static inline unsigned long read_cr4_safe(void) | |
670 | { | |
93b1eab3 | 671 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr4_safe); |
f8822f42 | 672 | } |
d3561b7f | 673 | |
f8822f42 JF |
674 | static inline void write_cr4(unsigned long x) |
675 | { | |
93b1eab3 | 676 | PVOP_VCALL1(pv_cpu_ops.write_cr4, x); |
f8822f42 | 677 | } |
3dc494e8 | 678 | |
94ea03cd | 679 | #ifdef CONFIG_X86_64 |
4c9890c2 GOC |
680 | static inline unsigned long read_cr8(void) |
681 | { | |
682 | return PVOP_CALL0(unsigned long, pv_cpu_ops.read_cr8); | |
683 | } | |
684 | ||
685 | static inline void write_cr8(unsigned long x) | |
686 | { | |
687 | PVOP_VCALL1(pv_cpu_ops.write_cr8, x); | |
688 | } | |
94ea03cd | 689 | #endif |
4c9890c2 | 690 | |
d3561b7f RR |
691 | static inline void raw_safe_halt(void) |
692 | { | |
93b1eab3 | 693 | PVOP_VCALL0(pv_irq_ops.safe_halt); |
d3561b7f RR |
694 | } |
695 | ||
696 | static inline void halt(void) | |
697 | { | |
93b1eab3 | 698 | PVOP_VCALL0(pv_irq_ops.safe_halt); |
f8822f42 JF |
699 | } |
700 | ||
701 | static inline void wbinvd(void) | |
702 | { | |
93b1eab3 | 703 | PVOP_VCALL0(pv_cpu_ops.wbinvd); |
d3561b7f | 704 | } |
d3561b7f | 705 | |
93b1eab3 | 706 | #define get_kernel_rpl() (pv_info.kernel_rpl) |
d3561b7f | 707 | |
f8822f42 JF |
708 | static inline u64 paravirt_read_msr(unsigned msr, int *err) |
709 | { | |
93b1eab3 | 710 | return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err); |
f8822f42 JF |
711 | } |
712 | static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high) | |
713 | { | |
93b1eab3 | 714 | return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high); |
f8822f42 JF |
715 | } |
716 | ||
90a0a06a | 717 | /* These should all do BUG_ON(_err), but our headers are too tangled. */ |
49cd740b JP |
718 | #define rdmsr(msr, val1, val2) \ |
719 | do { \ | |
f8822f42 JF |
720 | int _err; \ |
721 | u64 _l = paravirt_read_msr(msr, &_err); \ | |
722 | val1 = (u32)_l; \ | |
723 | val2 = _l >> 32; \ | |
49cd740b | 724 | } while (0) |
d3561b7f | 725 | |
49cd740b JP |
726 | #define wrmsr(msr, val1, val2) \ |
727 | do { \ | |
f8822f42 | 728 | paravirt_write_msr(msr, val1, val2); \ |
49cd740b | 729 | } while (0) |
d3561b7f | 730 | |
49cd740b JP |
731 | #define rdmsrl(msr, val) \ |
732 | do { \ | |
f8822f42 JF |
733 | int _err; \ |
734 | val = paravirt_read_msr(msr, &_err); \ | |
49cd740b | 735 | } while (0) |
d3561b7f | 736 | |
49cd740b JP |
737 | #define wrmsrl(msr, val) wrmsr(msr, (u32)((u64)(val)), ((u64)(val))>>32) |
738 | #define wrmsr_safe(msr, a, b) paravirt_write_msr(msr, a, b) | |
d3561b7f RR |
739 | |
740 | /* rdmsr with exception handling */ | |
49cd740b JP |
741 | #define rdmsr_safe(msr, a, b) \ |
742 | ({ \ | |
f8822f42 JF |
743 | int _err; \ |
744 | u64 _l = paravirt_read_msr(msr, &_err); \ | |
745 | (*a) = (u32)_l; \ | |
746 | (*b) = _l >> 32; \ | |
49cd740b JP |
747 | _err; \ |
748 | }) | |
d3561b7f | 749 | |
1de87bd4 AK |
750 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
751 | { | |
752 | int err; | |
753 | ||
754 | *p = paravirt_read_msr(msr, &err); | |
755 | return err; | |
756 | } | |
f8822f42 JF |
757 | |
758 | static inline u64 paravirt_read_tsc(void) | |
759 | { | |
93b1eab3 | 760 | return PVOP_CALL0(u64, pv_cpu_ops.read_tsc); |
f8822f42 | 761 | } |
d3561b7f | 762 | |
49cd740b JP |
763 | #define rdtscl(low) \ |
764 | do { \ | |
f8822f42 JF |
765 | u64 _l = paravirt_read_tsc(); \ |
766 | low = (int)_l; \ | |
49cd740b | 767 | } while (0) |
d3561b7f | 768 | |
f8822f42 | 769 | #define rdtscll(val) (val = paravirt_read_tsc()) |
d3561b7f | 770 | |
688340ea JF |
771 | static inline unsigned long long paravirt_sched_clock(void) |
772 | { | |
93b1eab3 | 773 | return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock); |
688340ea | 774 | } |
93b1eab3 | 775 | #define calculate_cpu_khz() (pv_time_ops.get_cpu_khz()) |
6cb9a835 | 776 | |
f8822f42 JF |
777 | static inline unsigned long long paravirt_read_pmc(int counter) |
778 | { | |
93b1eab3 | 779 | return PVOP_CALL1(u64, pv_cpu_ops.read_pmc, counter); |
f8822f42 | 780 | } |
d3561b7f | 781 | |
49cd740b JP |
782 | #define rdpmc(counter, low, high) \ |
783 | do { \ | |
f8822f42 JF |
784 | u64 _l = paravirt_read_pmc(counter); \ |
785 | low = (u32)_l; \ | |
786 | high = _l >> 32; \ | |
49cd740b | 787 | } while (0) |
3dc494e8 | 788 | |
e5aaac44 GOC |
789 | static inline unsigned long long paravirt_rdtscp(unsigned int *aux) |
790 | { | |
791 | return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux); | |
792 | } | |
793 | ||
794 | #define rdtscp(low, high, aux) \ | |
795 | do { \ | |
796 | int __aux; \ | |
797 | unsigned long __val = paravirt_rdtscp(&__aux); \ | |
798 | (low) = (u32)__val; \ | |
799 | (high) = (u32)(__val >> 32); \ | |
800 | (aux) = __aux; \ | |
801 | } while (0) | |
802 | ||
803 | #define rdtscpll(val, aux) \ | |
804 | do { \ | |
805 | unsigned long __aux; \ | |
806 | val = paravirt_rdtscp(&__aux); \ | |
807 | (aux) = __aux; \ | |
808 | } while (0) | |
809 | ||
f8822f42 JF |
810 | static inline void load_TR_desc(void) |
811 | { | |
93b1eab3 | 812 | PVOP_VCALL0(pv_cpu_ops.load_tr_desc); |
f8822f42 | 813 | } |
6b68f01b | 814 | static inline void load_gdt(const struct desc_ptr *dtr) |
f8822f42 | 815 | { |
93b1eab3 | 816 | PVOP_VCALL1(pv_cpu_ops.load_gdt, dtr); |
f8822f42 | 817 | } |
6b68f01b | 818 | static inline void load_idt(const struct desc_ptr *dtr) |
f8822f42 | 819 | { |
93b1eab3 | 820 | PVOP_VCALL1(pv_cpu_ops.load_idt, dtr); |
f8822f42 JF |
821 | } |
822 | static inline void set_ldt(const void *addr, unsigned entries) | |
823 | { | |
93b1eab3 | 824 | PVOP_VCALL2(pv_cpu_ops.set_ldt, addr, entries); |
f8822f42 | 825 | } |
6b68f01b | 826 | static inline void store_gdt(struct desc_ptr *dtr) |
f8822f42 | 827 | { |
93b1eab3 | 828 | PVOP_VCALL1(pv_cpu_ops.store_gdt, dtr); |
f8822f42 | 829 | } |
6b68f01b | 830 | static inline void store_idt(struct desc_ptr *dtr) |
f8822f42 | 831 | { |
93b1eab3 | 832 | PVOP_VCALL1(pv_cpu_ops.store_idt, dtr); |
f8822f42 JF |
833 | } |
834 | static inline unsigned long paravirt_store_tr(void) | |
835 | { | |
93b1eab3 | 836 | return PVOP_CALL0(unsigned long, pv_cpu_ops.store_tr); |
f8822f42 JF |
837 | } |
838 | #define store_tr(tr) ((tr) = paravirt_store_tr()) | |
839 | static inline void load_TLS(struct thread_struct *t, unsigned cpu) | |
840 | { | |
93b1eab3 | 841 | PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu); |
f8822f42 | 842 | } |
75b8bb3e GOC |
843 | |
844 | static inline void write_ldt_entry(struct desc_struct *dt, int entry, | |
845 | const void *desc) | |
f8822f42 | 846 | { |
75b8bb3e | 847 | PVOP_VCALL3(pv_cpu_ops.write_ldt_entry, dt, entry, desc); |
f8822f42 | 848 | } |
014b15be GOC |
849 | |
850 | static inline void write_gdt_entry(struct desc_struct *dt, int entry, | |
851 | void *desc, int type) | |
f8822f42 | 852 | { |
014b15be | 853 | PVOP_VCALL4(pv_cpu_ops.write_gdt_entry, dt, entry, desc, type); |
f8822f42 | 854 | } |
014b15be | 855 | |
8d947344 | 856 | static inline void write_idt_entry(gate_desc *dt, int entry, const gate_desc *g) |
f8822f42 | 857 | { |
8d947344 | 858 | PVOP_VCALL3(pv_cpu_ops.write_idt_entry, dt, entry, g); |
f8822f42 JF |
859 | } |
860 | static inline void set_iopl_mask(unsigned mask) | |
861 | { | |
93b1eab3 | 862 | PVOP_VCALL1(pv_cpu_ops.set_iopl_mask, mask); |
f8822f42 | 863 | } |
3dc494e8 | 864 | |
d3561b7f | 865 | /* The paravirtualized I/O functions */ |
49cd740b JP |
866 | static inline void slow_down_io(void) |
867 | { | |
93b1eab3 | 868 | pv_cpu_ops.io_delay(); |
d3561b7f | 869 | #ifdef REALLY_SLOW_IO |
93b1eab3 JF |
870 | pv_cpu_ops.io_delay(); |
871 | pv_cpu_ops.io_delay(); | |
872 | pv_cpu_ops.io_delay(); | |
d3561b7f RR |
873 | #endif |
874 | } | |
875 | ||
13623d79 RR |
876 | #ifdef CONFIG_X86_LOCAL_APIC |
877 | /* | |
878 | * Basic functions accessing APICs. | |
879 | */ | |
42e0a9aa | 880 | static inline void apic_write(unsigned long reg, u32 v) |
13623d79 | 881 | { |
93b1eab3 | 882 | PVOP_VCALL2(pv_apic_ops.apic_write, reg, v); |
13623d79 RR |
883 | } |
884 | ||
42e0a9aa | 885 | static inline void apic_write_atomic(unsigned long reg, u32 v) |
13623d79 | 886 | { |
93b1eab3 | 887 | PVOP_VCALL2(pv_apic_ops.apic_write_atomic, reg, v); |
13623d79 RR |
888 | } |
889 | ||
42e0a9aa | 890 | static inline u32 apic_read(unsigned long reg) |
13623d79 | 891 | { |
93b1eab3 | 892 | return PVOP_CALL1(unsigned long, pv_apic_ops.apic_read, reg); |
13623d79 | 893 | } |
bbab4f3b ZA |
894 | |
895 | static inline void setup_boot_clock(void) | |
896 | { | |
93b1eab3 | 897 | PVOP_VCALL0(pv_apic_ops.setup_boot_clock); |
bbab4f3b ZA |
898 | } |
899 | ||
900 | static inline void setup_secondary_clock(void) | |
901 | { | |
93b1eab3 | 902 | PVOP_VCALL0(pv_apic_ops.setup_secondary_clock); |
bbab4f3b | 903 | } |
13623d79 RR |
904 | #endif |
905 | ||
6996d3b6 JF |
906 | static inline void paravirt_post_allocator_init(void) |
907 | { | |
93b1eab3 JF |
908 | if (pv_init_ops.post_allocator_init) |
909 | (*pv_init_ops.post_allocator_init)(); | |
6996d3b6 JF |
910 | } |
911 | ||
b239fb25 JF |
912 | static inline void paravirt_pagetable_setup_start(pgd_t *base) |
913 | { | |
93b1eab3 | 914 | (*pv_mmu_ops.pagetable_setup_start)(base); |
b239fb25 JF |
915 | } |
916 | ||
917 | static inline void paravirt_pagetable_setup_done(pgd_t *base) | |
918 | { | |
93b1eab3 | 919 | (*pv_mmu_ops.pagetable_setup_done)(base); |
b239fb25 | 920 | } |
3dc494e8 | 921 | |
ae5da273 ZA |
922 | #ifdef CONFIG_SMP |
923 | static inline void startup_ipi_hook(int phys_apicid, unsigned long start_eip, | |
924 | unsigned long start_esp) | |
925 | { | |
93b1eab3 JF |
926 | PVOP_VCALL3(pv_apic_ops.startup_ipi_hook, |
927 | phys_apicid, start_eip, start_esp); | |
ae5da273 ZA |
928 | } |
929 | #endif | |
13623d79 | 930 | |
d6dd61c8 JF |
931 | static inline void paravirt_activate_mm(struct mm_struct *prev, |
932 | struct mm_struct *next) | |
933 | { | |
93b1eab3 | 934 | PVOP_VCALL2(pv_mmu_ops.activate_mm, prev, next); |
d6dd61c8 JF |
935 | } |
936 | ||
937 | static inline void arch_dup_mmap(struct mm_struct *oldmm, | |
938 | struct mm_struct *mm) | |
939 | { | |
93b1eab3 | 940 | PVOP_VCALL2(pv_mmu_ops.dup_mmap, oldmm, mm); |
d6dd61c8 JF |
941 | } |
942 | ||
943 | static inline void arch_exit_mmap(struct mm_struct *mm) | |
944 | { | |
93b1eab3 | 945 | PVOP_VCALL1(pv_mmu_ops.exit_mmap, mm); |
d6dd61c8 JF |
946 | } |
947 | ||
f8822f42 JF |
948 | static inline void __flush_tlb(void) |
949 | { | |
93b1eab3 | 950 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_user); |
f8822f42 JF |
951 | } |
952 | static inline void __flush_tlb_global(void) | |
953 | { | |
93b1eab3 | 954 | PVOP_VCALL0(pv_mmu_ops.flush_tlb_kernel); |
f8822f42 JF |
955 | } |
956 | static inline void __flush_tlb_single(unsigned long addr) | |
957 | { | |
93b1eab3 | 958 | PVOP_VCALL1(pv_mmu_ops.flush_tlb_single, addr); |
f8822f42 | 959 | } |
da181a8b | 960 | |
d4c10477 JF |
961 | static inline void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm, |
962 | unsigned long va) | |
963 | { | |
93b1eab3 | 964 | PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, &cpumask, mm, va); |
d4c10477 JF |
965 | } |
966 | ||
eba0045f JF |
967 | static inline int paravirt_pgd_alloc(struct mm_struct *mm) |
968 | { | |
969 | return PVOP_CALL1(int, pv_mmu_ops.pgd_alloc, mm); | |
970 | } | |
971 | ||
972 | static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd) | |
973 | { | |
974 | PVOP_VCALL2(pv_mmu_ops.pgd_free, mm, pgd); | |
975 | } | |
976 | ||
6944a9c8 | 977 | static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned pfn) |
f8822f42 | 978 | { |
6944a9c8 | 979 | PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn); |
f8822f42 | 980 | } |
6944a9c8 | 981 | static inline void paravirt_release_pte(unsigned pfn) |
f8822f42 | 982 | { |
6944a9c8 | 983 | PVOP_VCALL1(pv_mmu_ops.release_pte, pfn); |
f8822f42 | 984 | } |
c119ecce | 985 | |
6944a9c8 | 986 | static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned pfn) |
f8822f42 | 987 | { |
6944a9c8 | 988 | PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn); |
f8822f42 | 989 | } |
c119ecce | 990 | |
6944a9c8 JF |
991 | static inline void paravirt_alloc_pmd_clone(unsigned pfn, unsigned clonepfn, |
992 | unsigned start, unsigned count) | |
f8822f42 | 993 | { |
6944a9c8 | 994 | PVOP_VCALL4(pv_mmu_ops.alloc_pmd_clone, pfn, clonepfn, start, count); |
f8822f42 | 995 | } |
6944a9c8 | 996 | static inline void paravirt_release_pmd(unsigned pfn) |
da181a8b | 997 | { |
6944a9c8 | 998 | PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn); |
da181a8b RR |
999 | } |
1000 | ||
2761fa09 JF |
1001 | static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned pfn) |
1002 | { | |
1003 | PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn); | |
1004 | } | |
1005 | static inline void paravirt_release_pud(unsigned pfn) | |
1006 | { | |
1007 | PVOP_VCALL1(pv_mmu_ops.release_pud, pfn); | |
1008 | } | |
1009 | ||
ce6234b5 JF |
1010 | #ifdef CONFIG_HIGHPTE |
1011 | static inline void *kmap_atomic_pte(struct page *page, enum km_type type) | |
1012 | { | |
1013 | unsigned long ret; | |
93b1eab3 | 1014 | ret = PVOP_CALL2(unsigned long, pv_mmu_ops.kmap_atomic_pte, page, type); |
ce6234b5 JF |
1015 | return (void *)ret; |
1016 | } | |
1017 | #endif | |
1018 | ||
f8822f42 JF |
1019 | static inline void pte_update(struct mm_struct *mm, unsigned long addr, |
1020 | pte_t *ptep) | |
da181a8b | 1021 | { |
93b1eab3 | 1022 | PVOP_VCALL3(pv_mmu_ops.pte_update, mm, addr, ptep); |
da181a8b RR |
1023 | } |
1024 | ||
f8822f42 JF |
1025 | static inline void pte_update_defer(struct mm_struct *mm, unsigned long addr, |
1026 | pte_t *ptep) | |
da181a8b | 1027 | { |
93b1eab3 | 1028 | PVOP_VCALL3(pv_mmu_ops.pte_update_defer, mm, addr, ptep); |
da181a8b RR |
1029 | } |
1030 | ||
773221f4 | 1031 | static inline pte_t __pte(pteval_t val) |
da181a8b | 1032 | { |
773221f4 JF |
1033 | pteval_t ret; |
1034 | ||
1035 | if (sizeof(pteval_t) > sizeof(long)) | |
1036 | ret = PVOP_CALL2(pteval_t, | |
1037 | pv_mmu_ops.make_pte, | |
1038 | val, (u64)val >> 32); | |
1039 | else | |
1040 | ret = PVOP_CALL1(pteval_t, | |
1041 | pv_mmu_ops.make_pte, | |
1042 | val); | |
1043 | ||
c8e5393a | 1044 | return (pte_t) { .pte = ret }; |
da181a8b RR |
1045 | } |
1046 | ||
773221f4 JF |
1047 | static inline pteval_t pte_val(pte_t pte) |
1048 | { | |
1049 | pteval_t ret; | |
1050 | ||
1051 | if (sizeof(pteval_t) > sizeof(long)) | |
1052 | ret = PVOP_CALL2(pteval_t, pv_mmu_ops.pte_val, | |
1053 | pte.pte, (u64)pte.pte >> 32); | |
1054 | else | |
1055 | ret = PVOP_CALL1(pteval_t, pv_mmu_ops.pte_val, | |
1056 | pte.pte); | |
1057 | ||
1058 | return ret; | |
1059 | } | |
1060 | ||
a15af1c9 JF |
1061 | static inline pteval_t pte_flags(pte_t pte) |
1062 | { | |
1063 | pteval_t ret; | |
1064 | ||
1065 | if (sizeof(pteval_t) > sizeof(long)) | |
1066 | ret = PVOP_CALL2(pteval_t, pv_mmu_ops.pte_flags, | |
1067 | pte.pte, (u64)pte.pte >> 32); | |
1068 | else | |
1069 | ret = PVOP_CALL1(pteval_t, pv_mmu_ops.pte_flags, | |
1070 | pte.pte); | |
1071 | ||
1072 | return ret; | |
1073 | } | |
1074 | ||
ef38503e | 1075 | static inline pgd_t __pgd(pgdval_t val) |
da181a8b | 1076 | { |
ef38503e JF |
1077 | pgdval_t ret; |
1078 | ||
1079 | if (sizeof(pgdval_t) > sizeof(long)) | |
1080 | ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.make_pgd, | |
1081 | val, (u64)val >> 32); | |
1082 | else | |
1083 | ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.make_pgd, | |
1084 | val); | |
1085 | ||
1086 | return (pgd_t) { ret }; | |
1087 | } | |
1088 | ||
1089 | static inline pgdval_t pgd_val(pgd_t pgd) | |
1090 | { | |
1091 | pgdval_t ret; | |
1092 | ||
1093 | if (sizeof(pgdval_t) > sizeof(long)) | |
1094 | ret = PVOP_CALL2(pgdval_t, pv_mmu_ops.pgd_val, | |
1095 | pgd.pgd, (u64)pgd.pgd >> 32); | |
1096 | else | |
1097 | ret = PVOP_CALL1(pgdval_t, pv_mmu_ops.pgd_val, | |
1098 | pgd.pgd); | |
1099 | ||
1100 | return ret; | |
f8822f42 JF |
1101 | } |
1102 | ||
08b882c6 JF |
1103 | #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION |
1104 | static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr, | |
1105 | pte_t *ptep) | |
1106 | { | |
1107 | pteval_t ret; | |
1108 | ||
1109 | ret = PVOP_CALL3(pteval_t, pv_mmu_ops.ptep_modify_prot_start, | |
1110 | mm, addr, ptep); | |
1111 | ||
1112 | return (pte_t) { .pte = ret }; | |
1113 | } | |
1114 | ||
1115 | static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr, | |
1116 | pte_t *ptep, pte_t pte) | |
1117 | { | |
1118 | if (sizeof(pteval_t) > sizeof(long)) | |
1119 | /* 5 arg words */ | |
1120 | pv_mmu_ops.ptep_modify_prot_commit(mm, addr, ptep, pte); | |
1121 | else | |
1122 | PVOP_VCALL4(pv_mmu_ops.ptep_modify_prot_commit, | |
1123 | mm, addr, ptep, pte.pte); | |
1124 | } | |
1125 | ||
4eed80cd JF |
1126 | static inline void set_pte(pte_t *ptep, pte_t pte) |
1127 | { | |
1128 | if (sizeof(pteval_t) > sizeof(long)) | |
1129 | PVOP_VCALL3(pv_mmu_ops.set_pte, ptep, | |
1130 | pte.pte, (u64)pte.pte >> 32); | |
1131 | else | |
1132 | PVOP_VCALL2(pv_mmu_ops.set_pte, ptep, | |
1133 | pte.pte); | |
1134 | } | |
1135 | ||
1136 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, | |
1137 | pte_t *ptep, pte_t pte) | |
1138 | { | |
1139 | if (sizeof(pteval_t) > sizeof(long)) | |
1140 | /* 5 arg words */ | |
1141 | pv_mmu_ops.set_pte_at(mm, addr, ptep, pte); | |
1142 | else | |
1143 | PVOP_VCALL4(pv_mmu_ops.set_pte_at, mm, addr, ptep, pte.pte); | |
1144 | } | |
1145 | ||
60b3f626 JF |
1146 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
1147 | { | |
1148 | pmdval_t val = native_pmd_val(pmd); | |
1149 | ||
1150 | if (sizeof(pmdval_t) > sizeof(long)) | |
1151 | PVOP_VCALL3(pv_mmu_ops.set_pmd, pmdp, val, (u64)val >> 32); | |
1152 | else | |
1153 | PVOP_VCALL2(pv_mmu_ops.set_pmd, pmdp, val); | |
1154 | } | |
1155 | ||
1fe91514 GOC |
1156 | #if PAGETABLE_LEVELS >= 3 |
1157 | static inline pmd_t __pmd(pmdval_t val) | |
1158 | { | |
1159 | pmdval_t ret; | |
1160 | ||
1161 | if (sizeof(pmdval_t) > sizeof(long)) | |
1162 | ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.make_pmd, | |
1163 | val, (u64)val >> 32); | |
1164 | else | |
1165 | ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.make_pmd, | |
1166 | val); | |
1167 | ||
1168 | return (pmd_t) { ret }; | |
1169 | } | |
1170 | ||
1171 | static inline pmdval_t pmd_val(pmd_t pmd) | |
1172 | { | |
1173 | pmdval_t ret; | |
1174 | ||
1175 | if (sizeof(pmdval_t) > sizeof(long)) | |
1176 | ret = PVOP_CALL2(pmdval_t, pv_mmu_ops.pmd_val, | |
1177 | pmd.pmd, (u64)pmd.pmd >> 32); | |
1178 | else | |
1179 | ret = PVOP_CALL1(pmdval_t, pv_mmu_ops.pmd_val, | |
1180 | pmd.pmd); | |
1181 | ||
1182 | return ret; | |
1183 | } | |
1184 | ||
1185 | static inline void set_pud(pud_t *pudp, pud_t pud) | |
1186 | { | |
1187 | pudval_t val = native_pud_val(pud); | |
1188 | ||
1189 | if (sizeof(pudval_t) > sizeof(long)) | |
1190 | PVOP_VCALL3(pv_mmu_ops.set_pud, pudp, | |
1191 | val, (u64)val >> 32); | |
1192 | else | |
1193 | PVOP_VCALL2(pv_mmu_ops.set_pud, pudp, | |
1194 | val); | |
1195 | } | |
9042219c EH |
1196 | #if PAGETABLE_LEVELS == 4 |
1197 | static inline pud_t __pud(pudval_t val) | |
1198 | { | |
1199 | pudval_t ret; | |
1200 | ||
1201 | if (sizeof(pudval_t) > sizeof(long)) | |
1202 | ret = PVOP_CALL2(pudval_t, pv_mmu_ops.make_pud, | |
1203 | val, (u64)val >> 32); | |
1204 | else | |
1205 | ret = PVOP_CALL1(pudval_t, pv_mmu_ops.make_pud, | |
1206 | val); | |
1207 | ||
1208 | return (pud_t) { ret }; | |
1209 | } | |
1210 | ||
1211 | static inline pudval_t pud_val(pud_t pud) | |
1212 | { | |
1213 | pudval_t ret; | |
1214 | ||
1215 | if (sizeof(pudval_t) > sizeof(long)) | |
1216 | ret = PVOP_CALL2(pudval_t, pv_mmu_ops.pud_val, | |
1217 | pud.pud, (u64)pud.pud >> 32); | |
1218 | else | |
1219 | ret = PVOP_CALL1(pudval_t, pv_mmu_ops.pud_val, | |
1220 | pud.pud); | |
1221 | ||
1222 | return ret; | |
1223 | } | |
1224 | ||
1225 | static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) | |
1226 | { | |
1227 | pgdval_t val = native_pgd_val(pgd); | |
1228 | ||
1229 | if (sizeof(pgdval_t) > sizeof(long)) | |
1230 | PVOP_VCALL3(pv_mmu_ops.set_pgd, pgdp, | |
1231 | val, (u64)val >> 32); | |
1232 | else | |
1233 | PVOP_VCALL2(pv_mmu_ops.set_pgd, pgdp, | |
1234 | val); | |
1235 | } | |
1236 | ||
1237 | static inline void pgd_clear(pgd_t *pgdp) | |
1238 | { | |
1239 | set_pgd(pgdp, __pgd(0)); | |
1240 | } | |
1241 | ||
1242 | static inline void pud_clear(pud_t *pudp) | |
1243 | { | |
1244 | set_pud(pudp, __pud(0)); | |
1245 | } | |
1246 | ||
1247 | #endif /* PAGETABLE_LEVELS == 4 */ | |
1248 | ||
1fe91514 GOC |
1249 | #endif /* PAGETABLE_LEVELS >= 3 */ |
1250 | ||
4eed80cd JF |
1251 | #ifdef CONFIG_X86_PAE |
1252 | /* Special-case pte-setting operations for PAE, which can't update a | |
1253 | 64-bit pte atomically */ | |
1254 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
1255 | { | |
1256 | PVOP_VCALL3(pv_mmu_ops.set_pte_atomic, ptep, | |
1257 | pte.pte, pte.pte >> 32); | |
1258 | } | |
1259 | ||
1260 | static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, | |
1261 | pte_t *ptep, pte_t pte) | |
1262 | { | |
1263 | /* 5 arg words */ | |
1264 | pv_mmu_ops.set_pte_present(mm, addr, ptep, pte); | |
1265 | } | |
1266 | ||
1267 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, | |
1268 | pte_t *ptep) | |
1269 | { | |
1270 | PVOP_VCALL3(pv_mmu_ops.pte_clear, mm, addr, ptep); | |
1271 | } | |
60b3f626 JF |
1272 | |
1273 | static inline void pmd_clear(pmd_t *pmdp) | |
1274 | { | |
1275 | PVOP_VCALL1(pv_mmu_ops.pmd_clear, pmdp); | |
1276 | } | |
4eed80cd JF |
1277 | #else /* !CONFIG_X86_PAE */ |
1278 | static inline void set_pte_atomic(pte_t *ptep, pte_t pte) | |
1279 | { | |
1280 | set_pte(ptep, pte); | |
1281 | } | |
1282 | ||
1283 | static inline void set_pte_present(struct mm_struct *mm, unsigned long addr, | |
1284 | pte_t *ptep, pte_t pte) | |
1285 | { | |
1286 | set_pte(ptep, pte); | |
1287 | } | |
1288 | ||
1289 | static inline void pte_clear(struct mm_struct *mm, unsigned long addr, | |
1290 | pte_t *ptep) | |
1291 | { | |
1292 | set_pte_at(mm, addr, ptep, __pte(0)); | |
1293 | } | |
60b3f626 JF |
1294 | |
1295 | static inline void pmd_clear(pmd_t *pmdp) | |
1296 | { | |
1297 | set_pmd(pmdp, __pmd(0)); | |
1298 | } | |
4eed80cd JF |
1299 | #endif /* CONFIG_X86_PAE */ |
1300 | ||
8965c1c0 JF |
1301 | /* Lazy mode for batching updates / context switch */ |
1302 | enum paravirt_lazy_mode { | |
1303 | PARAVIRT_LAZY_NONE, | |
1304 | PARAVIRT_LAZY_MMU, | |
1305 | PARAVIRT_LAZY_CPU, | |
1306 | }; | |
1307 | ||
1308 | enum paravirt_lazy_mode paravirt_get_lazy_mode(void); | |
1309 | void paravirt_enter_lazy_cpu(void); | |
1310 | void paravirt_leave_lazy_cpu(void); | |
1311 | void paravirt_enter_lazy_mmu(void); | |
1312 | void paravirt_leave_lazy_mmu(void); | |
1313 | void paravirt_leave_lazy(enum paravirt_lazy_mode mode); | |
1314 | ||
9226d125 | 1315 | #define __HAVE_ARCH_ENTER_LAZY_CPU_MODE |
f8822f42 JF |
1316 | static inline void arch_enter_lazy_cpu_mode(void) |
1317 | { | |
8965c1c0 | 1318 | PVOP_VCALL0(pv_cpu_ops.lazy_mode.enter); |
f8822f42 JF |
1319 | } |
1320 | ||
1321 | static inline void arch_leave_lazy_cpu_mode(void) | |
1322 | { | |
8965c1c0 | 1323 | PVOP_VCALL0(pv_cpu_ops.lazy_mode.leave); |
f8822f42 JF |
1324 | } |
1325 | ||
1326 | static inline void arch_flush_lazy_cpu_mode(void) | |
1327 | { | |
8965c1c0 JF |
1328 | if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU)) { |
1329 | arch_leave_lazy_cpu_mode(); | |
1330 | arch_enter_lazy_cpu_mode(); | |
1331 | } | |
f8822f42 JF |
1332 | } |
1333 | ||
9226d125 ZA |
1334 | |
1335 | #define __HAVE_ARCH_ENTER_LAZY_MMU_MODE | |
f8822f42 JF |
1336 | static inline void arch_enter_lazy_mmu_mode(void) |
1337 | { | |
8965c1c0 | 1338 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.enter); |
f8822f42 JF |
1339 | } |
1340 | ||
1341 | static inline void arch_leave_lazy_mmu_mode(void) | |
1342 | { | |
8965c1c0 | 1343 | PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave); |
f8822f42 JF |
1344 | } |
1345 | ||
1346 | static inline void arch_flush_lazy_mmu_mode(void) | |
1347 | { | |
8965c1c0 JF |
1348 | if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU)) { |
1349 | arch_leave_lazy_mmu_mode(); | |
1350 | arch_enter_lazy_mmu_mode(); | |
1351 | } | |
f8822f42 | 1352 | } |
9226d125 | 1353 | |
aeaaa59c JF |
1354 | static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx, |
1355 | unsigned long phys, pgprot_t flags) | |
1356 | { | |
1357 | pv_mmu_ops.set_fixmap(idx, phys, flags); | |
1358 | } | |
1359 | ||
45876233 JF |
1360 | void _paravirt_nop(void); |
1361 | #define paravirt_nop ((void *)_paravirt_nop) | |
1362 | ||
139ec7c4 | 1363 | /* These all sit in the .parainstructions section to tell us what to patch. */ |
98de032b | 1364 | struct paravirt_patch_site { |
139ec7c4 RR |
1365 | u8 *instr; /* original instructions */ |
1366 | u8 instrtype; /* type of this instruction */ | |
1367 | u8 len; /* length of original instruction */ | |
1368 | u16 clobbers; /* what registers you may clobber */ | |
1369 | }; | |
1370 | ||
98de032b JF |
1371 | extern struct paravirt_patch_site __parainstructions[], |
1372 | __parainstructions_end[]; | |
1373 | ||
2e47d3e6 GOC |
1374 | #ifdef CONFIG_X86_32 |
1375 | #define PV_SAVE_REGS "pushl %%ecx; pushl %%edx;" | |
1376 | #define PV_RESTORE_REGS "popl %%edx; popl %%ecx" | |
1377 | #define PV_FLAGS_ARG "0" | |
1378 | #define PV_EXTRA_CLOBBERS | |
1379 | #define PV_VEXTRA_CLOBBERS | |
1380 | #else | |
1381 | /* We save some registers, but all of them, that's too much. We clobber all | |
1382 | * caller saved registers but the argument parameter */ | |
1383 | #define PV_SAVE_REGS "pushq %%rdi;" | |
1384 | #define PV_RESTORE_REGS "popq %%rdi;" | |
1385 | #define PV_EXTRA_CLOBBERS EXTRA_CLOBBERS, "rcx" , "rdx" | |
1386 | #define PV_VEXTRA_CLOBBERS EXTRA_CLOBBERS, "rdi", "rcx" , "rdx" | |
1387 | #define PV_FLAGS_ARG "D" | |
1388 | #endif | |
1389 | ||
139ec7c4 RR |
1390 | static inline unsigned long __raw_local_save_flags(void) |
1391 | { | |
1392 | unsigned long f; | |
1393 | ||
2e47d3e6 | 1394 | asm volatile(paravirt_alt(PV_SAVE_REGS |
d5822035 | 1395 | PARAVIRT_CALL |
2e47d3e6 | 1396 | PV_RESTORE_REGS) |
d5822035 | 1397 | : "=a"(f) |
93b1eab3 | 1398 | : paravirt_type(pv_irq_ops.save_fl), |
42c24fa2 | 1399 | paravirt_clobber(CLBR_EAX) |
2e47d3e6 | 1400 | : "memory", "cc" PV_VEXTRA_CLOBBERS); |
139ec7c4 RR |
1401 | return f; |
1402 | } | |
1403 | ||
1404 | static inline void raw_local_irq_restore(unsigned long f) | |
1405 | { | |
2e47d3e6 | 1406 | asm volatile(paravirt_alt(PV_SAVE_REGS |
d5822035 | 1407 | PARAVIRT_CALL |
2e47d3e6 | 1408 | PV_RESTORE_REGS) |
d5822035 | 1409 | : "=a"(f) |
2e47d3e6 | 1410 | : PV_FLAGS_ARG(f), |
93b1eab3 | 1411 | paravirt_type(pv_irq_ops.restore_fl), |
d5822035 | 1412 | paravirt_clobber(CLBR_EAX) |
2e47d3e6 | 1413 | : "memory", "cc" PV_EXTRA_CLOBBERS); |
139ec7c4 RR |
1414 | } |
1415 | ||
1416 | static inline void raw_local_irq_disable(void) | |
1417 | { | |
2e47d3e6 | 1418 | asm volatile(paravirt_alt(PV_SAVE_REGS |
d5822035 | 1419 | PARAVIRT_CALL |
2e47d3e6 | 1420 | PV_RESTORE_REGS) |
d5822035 | 1421 | : |
93b1eab3 | 1422 | : paravirt_type(pv_irq_ops.irq_disable), |
d5822035 | 1423 | paravirt_clobber(CLBR_EAX) |
2e47d3e6 | 1424 | : "memory", "eax", "cc" PV_EXTRA_CLOBBERS); |
139ec7c4 RR |
1425 | } |
1426 | ||
1427 | static inline void raw_local_irq_enable(void) | |
1428 | { | |
2e47d3e6 | 1429 | asm volatile(paravirt_alt(PV_SAVE_REGS |
d5822035 | 1430 | PARAVIRT_CALL |
2e47d3e6 | 1431 | PV_RESTORE_REGS) |
d5822035 | 1432 | : |
93b1eab3 | 1433 | : paravirt_type(pv_irq_ops.irq_enable), |
d5822035 | 1434 | paravirt_clobber(CLBR_EAX) |
2e47d3e6 | 1435 | : "memory", "eax", "cc" PV_EXTRA_CLOBBERS); |
139ec7c4 RR |
1436 | } |
1437 | ||
1438 | static inline unsigned long __raw_local_irq_save(void) | |
1439 | { | |
1440 | unsigned long f; | |
1441 | ||
d5822035 JF |
1442 | f = __raw_local_save_flags(); |
1443 | raw_local_irq_disable(); | |
139ec7c4 RR |
1444 | return f; |
1445 | } | |
1446 | ||
294688c0 | 1447 | /* Make sure as little as possible of this mess escapes. */ |
d5822035 | 1448 | #undef PARAVIRT_CALL |
1a45b7aa JF |
1449 | #undef __PVOP_CALL |
1450 | #undef __PVOP_VCALL | |
f8822f42 JF |
1451 | #undef PVOP_VCALL0 |
1452 | #undef PVOP_CALL0 | |
1453 | #undef PVOP_VCALL1 | |
1454 | #undef PVOP_CALL1 | |
1455 | #undef PVOP_VCALL2 | |
1456 | #undef PVOP_CALL2 | |
1457 | #undef PVOP_VCALL3 | |
1458 | #undef PVOP_CALL3 | |
1459 | #undef PVOP_VCALL4 | |
1460 | #undef PVOP_CALL4 | |
139ec7c4 | 1461 | |
d3561b7f RR |
1462 | #else /* __ASSEMBLY__ */ |
1463 | ||
658be9d3 | 1464 | #define _PVSITE(ptype, clobbers, ops, word, algn) \ |
139ec7c4 RR |
1465 | 771:; \ |
1466 | ops; \ | |
1467 | 772:; \ | |
1468 | .pushsection .parainstructions,"a"; \ | |
658be9d3 GOC |
1469 | .align algn; \ |
1470 | word 771b; \ | |
139ec7c4 RR |
1471 | .byte ptype; \ |
1472 | .byte 772b-771b; \ | |
1473 | .short clobbers; \ | |
1474 | .popsection | |
1475 | ||
658be9d3 GOC |
1476 | |
1477 | #ifdef CONFIG_X86_64 | |
6057fc82 GOC |
1478 | #define PV_SAVE_REGS pushq %rax; pushq %rdi; pushq %rcx; pushq %rdx |
1479 | #define PV_RESTORE_REGS popq %rdx; popq %rcx; popq %rdi; popq %rax | |
1480 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8) | |
658be9d3 | 1481 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8) |
491eccb7 | 1482 | #define PARA_INDIRECT(addr) *addr(%rip) |
658be9d3 | 1483 | #else |
6057fc82 GOC |
1484 | #define PV_SAVE_REGS pushl %eax; pushl %edi; pushl %ecx; pushl %edx |
1485 | #define PV_RESTORE_REGS popl %edx; popl %ecx; popl %edi; popl %eax | |
1486 | #define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4) | |
658be9d3 | 1487 | #define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4) |
491eccb7 | 1488 | #define PARA_INDIRECT(addr) *%cs:addr |
658be9d3 GOC |
1489 | #endif |
1490 | ||
93b1eab3 JF |
1491 | #define INTERRUPT_RETURN \ |
1492 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \ | |
491eccb7 | 1493 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret)) |
d5822035 JF |
1494 | |
1495 | #define DISABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 1496 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \ |
491eccb7 JF |
1497 | PV_SAVE_REGS; \ |
1498 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable); \ | |
6057fc82 | 1499 | PV_RESTORE_REGS;) \ |
d5822035 JF |
1500 | |
1501 | #define ENABLE_INTERRUPTS(clobbers) \ | |
93b1eab3 | 1502 | PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \ |
491eccb7 JF |
1503 | PV_SAVE_REGS; \ |
1504 | call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable); \ | |
6057fc82 | 1505 | PV_RESTORE_REGS;) |
d5822035 | 1506 | |
2be29982 JF |
1507 | #define USERGS_SYSRET32 \ |
1508 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret32), \ | |
6abcd98f | 1509 | CLBR_NONE, \ |
2be29982 | 1510 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret32)) |
2e47d3e6 | 1511 | |
6057fc82 | 1512 | #ifdef CONFIG_X86_32 |
491eccb7 JF |
1513 | #define GET_CR0_INTO_EAX \ |
1514 | push %ecx; push %edx; \ | |
1515 | call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0); \ | |
42c24fa2 | 1516 | pop %edx; pop %ecx |
2be29982 JF |
1517 | |
1518 | #define ENABLE_INTERRUPTS_SYSEXIT \ | |
1519 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit), \ | |
1520 | CLBR_NONE, \ | |
1521 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_irq_enable_sysexit)) | |
1522 | ||
1523 | ||
1524 | #else /* !CONFIG_X86_32 */ | |
e801f864 GOC |
1525 | #define SWAPGS \ |
1526 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \ | |
1527 | PV_SAVE_REGS; \ | |
491eccb7 | 1528 | call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs); \ |
e801f864 GOC |
1529 | PV_RESTORE_REGS \ |
1530 | ) | |
1531 | ||
491eccb7 JF |
1532 | #define GET_CR2_INTO_RCX \ |
1533 | call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2); \ | |
1534 | movq %rax, %rcx; \ | |
4a8c4c4e GOC |
1535 | xorq %rax, %rax; |
1536 | ||
2be29982 JF |
1537 | #define USERGS_SYSRET64 \ |
1538 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64), \ | |
d75cd22f | 1539 | CLBR_NONE, \ |
2be29982 JF |
1540 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64)) |
1541 | ||
1542 | #define ENABLE_INTERRUPTS_SYSEXIT32 \ | |
1543 | PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit), \ | |
1544 | CLBR_NONE, \ | |
1545 | jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_irq_enable_sysexit)) | |
1546 | #endif /* CONFIG_X86_32 */ | |
139ec7c4 | 1547 | |
d3561b7f RR |
1548 | #endif /* __ASSEMBLY__ */ |
1549 | #endif /* CONFIG_PARAVIRT */ | |
1550 | #endif /* __ASM_PARAVIRT_H */ |