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c2805aa1 TG |
1 | #ifndef _AM_X86_MPSPEC_H |
2 | #define _AM_X86_MPSPEC_H | |
3 | ||
86c9835b IM |
4 | #include <linux/init.h> |
5 | ||
c2805aa1 TG |
6 | #include <asm/mpspec_def.h> |
7 | ||
96a388de | 8 | #ifdef CONFIG_X86_32 |
c2805aa1 TG |
9 | #include <mach_mpspec.h> |
10 | ||
c2805aa1 TG |
11 | extern unsigned int def_to_bigsmp; |
12 | extern int apic_version[MAX_APICS]; | |
ae9d983b | 13 | extern u8 apicid_2_node[]; |
c2805aa1 TG |
14 | extern int pic_mode; |
15 | ||
ae9d983b TG |
16 | #define MAX_APICID 256 |
17 | ||
96a388de | 18 | #else |
c2805aa1 TG |
19 | |
20 | #define MAX_MP_BUSSES 256 | |
21 | /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */ | |
22 | #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4) | |
23 | ||
ab530e1f YL |
24 | #endif |
25 | ||
8643f9d0 YL |
26 | extern void early_find_smp_config(void); |
27 | extern void early_get_smp_config(void); | |
28 | ||
c0a282c2 AS |
29 | #if defined(CONFIG_MCA) || defined(CONFIG_EISA) |
30 | extern int mp_bus_id_to_type[MAX_MP_BUSSES]; | |
31 | #endif | |
32 | ||
a6333c3c | 33 | extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
c0a282c2 | 34 | |
c2805aa1 | 35 | extern unsigned int boot_cpu_physical_apicid; |
e0da3364 | 36 | extern unsigned int max_physical_apicid; |
c2805aa1 | 37 | extern int smp_found_config; |
c2805aa1 TG |
38 | extern int mpc_default_type; |
39 | extern unsigned long mp_lapic_addr; | |
40 | ||
41 | extern void find_smp_config(void); | |
42 | extern void get_smp_config(void); | |
2944e16b | 43 | extern void early_reserve_e820_mpc_new(void); |
c2805aa1 | 44 | |
903dcb5a | 45 | void __cpuinit generic_processor_info(int apicid, int version); |
c2805aa1 | 46 | #ifdef CONFIG_ACPI |
a65d1d64 | 47 | extern void mp_register_ioapic(int id, u32 address, u32 gsi_base); |
c2805aa1 TG |
48 | extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, |
49 | u32 gsi); | |
50 | extern void mp_config_acpi_legacy_irqs(void); | |
51 | extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low); | |
2944e16b | 52 | extern void MP_intsrc_info(struct mpc_config_intsrc *m); |
835fc943 | 53 | #ifdef CONFIG_X86_IO_APIC |
2944e16b YL |
54 | extern int mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin, |
55 | u32 gsi, int triggering, int polarity); | |
835fc943 IM |
56 | #else |
57 | static inline int | |
58 | mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin, | |
59 | u32 gsi, int triggering, int polarity) | |
60 | { | |
61 | return 0; | |
62 | } | |
63 | #endif | |
c2805aa1 TG |
64 | #endif /* CONFIG_ACPI */ |
65 | ||
66 | #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) | |
67 | ||
30971e17 | 68 | struct physid_mask { |
c2805aa1 TG |
69 | unsigned long mask[PHYSID_ARRAY_SIZE]; |
70 | }; | |
71 | ||
72 | typedef struct physid_mask physid_mask_t; | |
73 | ||
74 | #define physid_set(physid, map) set_bit(physid, (map).mask) | |
75 | #define physid_clear(physid, map) clear_bit(physid, (map).mask) | |
76 | #define physid_isset(physid, map) test_bit(physid, (map).mask) | |
30971e17 | 77 | #define physid_test_and_set(physid, map) \ |
c2805aa1 TG |
78 | test_and_set_bit(physid, (map).mask) |
79 | ||
30971e17 | 80 | #define physids_and(dst, src1, src2) \ |
c2805aa1 TG |
81 | bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS) |
82 | ||
30971e17 | 83 | #define physids_or(dst, src1, src2) \ |
c2805aa1 TG |
84 | bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS) |
85 | ||
30971e17 | 86 | #define physids_clear(map) \ |
c2805aa1 TG |
87 | bitmap_zero((map).mask, MAX_APICS) |
88 | ||
30971e17 | 89 | #define physids_complement(dst, src) \ |
c2805aa1 TG |
90 | bitmap_complement((dst).mask, (src).mask, MAX_APICS) |
91 | ||
30971e17 | 92 | #define physids_empty(map) \ |
c2805aa1 TG |
93 | bitmap_empty((map).mask, MAX_APICS) |
94 | ||
30971e17 | 95 | #define physids_equal(map1, map2) \ |
c2805aa1 TG |
96 | bitmap_equal((map1).mask, (map2).mask, MAX_APICS) |
97 | ||
30971e17 | 98 | #define physids_weight(map) \ |
c2805aa1 TG |
99 | bitmap_weight((map).mask, MAX_APICS) |
100 | ||
30971e17 | 101 | #define physids_shift_right(d, s, n) \ |
c2805aa1 TG |
102 | bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS) |
103 | ||
30971e17 | 104 | #define physids_shift_left(d, s, n) \ |
c2805aa1 TG |
105 | bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS) |
106 | ||
107 | #define physids_coerce(map) ((map).mask[0]) | |
108 | ||
109 | #define physids_promote(physids) \ | |
110 | ({ \ | |
111 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
112 | __physid_mask.mask[0] = physids; \ | |
113 | __physid_mask; \ | |
114 | }) | |
115 | ||
116 | #define physid_mask_of_physid(physid) \ | |
117 | ({ \ | |
118 | physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
119 | physid_set(physid, __physid_mask); \ | |
120 | __physid_mask; \ | |
121 | }) | |
122 | ||
123 | #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } | |
124 | #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} } | |
125 | ||
126 | extern physid_mask_t phys_cpu_present_map; | |
127 | ||
96a388de | 128 | #endif |