Commit | Line | Data |
---|---|---|
77ef50a5 VN |
1 | #ifndef ASM_X86__MACH_DEFAULT__MACH_APIC_H |
2 | #define ASM_X86__MACH_DEFAULT__MACH_APIC_H | |
1da177e4 | 3 | |
dd46e3ca GC |
4 | #ifdef CONFIG_X86_LOCAL_APIC |
5 | ||
1da177e4 LT |
6 | #include <mach_apicdef.h> |
7 | #include <asm/smp.h> | |
8 | ||
9 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | |
10 | ||
11 | static inline cpumask_t target_cpus(void) | |
12 | { | |
13 | #ifdef CONFIG_SMP | |
14 | return cpu_online_map; | |
15 | #else | |
16 | return cpumask_of_cpu(0); | |
17 | #endif | |
18 | } | |
1da177e4 LT |
19 | |
20 | #define NO_BALANCE_IRQ (0) | |
21 | #define esr_disable (0) | |
22 | ||
dd46e3ca GC |
23 | #ifdef CONFIG_X86_64 |
24 | #include <asm/genapic.h> | |
25 | #define INT_DELIVERY_MODE (genapic->int_delivery_mode) | |
26 | #define INT_DEST_MODE (genapic->int_dest_mode) | |
27 | #define TARGET_CPUS (genapic->target_cpus()) | |
28 | #define apic_id_registered (genapic->apic_id_registered) | |
29 | #define init_apic_ldr (genapic->init_apic_ldr) | |
30 | #define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid) | |
31 | #define phys_pkg_id (genapic->phys_pkg_id) | |
32 | #define vector_allocation_domain (genapic->vector_allocation_domain) | |
f910a9dc | 33 | #define read_apic_id() (GET_APIC_ID(apic_read(APIC_ID))) |
cff73a6f | 34 | #define send_IPI_self (genapic->send_IPI_self) |
dd46e3ca GC |
35 | extern void setup_apic_routing(void); |
36 | #else | |
1da177e4 LT |
37 | #define INT_DELIVERY_MODE dest_LowestPrio |
38 | #define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */ | |
dd46e3ca | 39 | #define TARGET_CPUS (target_cpus()) |
1da177e4 LT |
40 | /* |
41 | * Set up the logical destination ID. | |
42 | * | |
43 | * Intel recommends to set DFR, LDR and TPR before enabling | |
44 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
45 | * document number 292116). So here it goes... | |
46 | */ | |
47 | static inline void init_apic_ldr(void) | |
48 | { | |
49 | unsigned long val; | |
50 | ||
593f4a78 | 51 | apic_write(APIC_DFR, APIC_DFR_VALUE); |
1da177e4 LT |
52 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; |
53 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); | |
593f4a78 | 54 | apic_write(APIC_LDR, val); |
1da177e4 LT |
55 | } |
56 | ||
dd46e3ca | 57 | static inline int apic_id_registered(void) |
1da177e4 | 58 | { |
4c9961d5 | 59 | return physid_isset(read_apic_id(), phys_cpu_present_map); |
dd46e3ca GC |
60 | } |
61 | ||
62 | static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask) | |
63 | { | |
64 | return cpus_addr(cpumask)[0]; | |
65 | } | |
66 | ||
67 | static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb) | |
68 | { | |
69 | return cpuid_apic >> index_msb; | |
1da177e4 LT |
70 | } |
71 | ||
3c43f039 | 72 | static inline void setup_apic_routing(void) |
1da177e4 | 73 | { |
61048c63 | 74 | #ifdef CONFIG_X86_IO_APIC |
1da177e4 LT |
75 | printk("Enabling APIC mode: %s. Using %d I/O APICs\n", |
76 | "Flat", nr_ioapics); | |
61048c63 | 77 | #endif |
1da177e4 LT |
78 | } |
79 | ||
dd46e3ca | 80 | static inline int apicid_to_node(int logical_apicid) |
1da177e4 | 81 | { |
f47f9d53 YL |
82 | #ifdef CONFIG_SMP |
83 | return apicid_2_node[hard_smp_processor_id()]; | |
84 | #else | |
1da177e4 | 85 | return 0; |
f47f9d53 | 86 | #endif |
1da177e4 | 87 | } |
497c9a19 YL |
88 | |
89 | static inline cpumask_t vector_allocation_domain(int cpu) | |
90 | { | |
91 | /* Careful. Some cpus do not strictly honor the set of cpus | |
92 | * specified in the interrupt destination when using lowest | |
93 | * priority interrupt delivery mode. | |
94 | * | |
95 | * In particular there was a hyperthreading cpu observed to | |
96 | * deliver interrupts to the wrong hyperthread when only one | |
97 | * hyperthread was specified in the interrupt desitination. | |
98 | */ | |
99 | cpumask_t domain = { { [0] = APIC_ALL_CPUS, } }; | |
100 | return domain; | |
101 | } | |
dd46e3ca | 102 | #endif |
1da177e4 | 103 | |
dd46e3ca GC |
104 | static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) |
105 | { | |
106 | return physid_isset(apicid, bitmap); | |
107 | } | |
108 | ||
109 | static inline unsigned long check_apicid_present(int bit) | |
110 | { | |
111 | return physid_isset(bit, phys_cpu_present_map); | |
112 | } | |
113 | ||
114 | static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map) | |
115 | { | |
116 | return phys_map; | |
117 | } | |
118 | ||
119 | static inline int multi_timer_check(int apic, int irq) | |
1da177e4 LT |
120 | { |
121 | return 0; | |
122 | } | |
123 | ||
124 | /* Mapping from cpu number to logical apicid */ | |
125 | static inline int cpu_to_logical_apicid(int cpu) | |
126 | { | |
127 | return 1 << cpu; | |
128 | } | |
129 | ||
130 | static inline int cpu_present_to_apicid(int mps_cpu) | |
131 | { | |
5f464707 | 132 | if (mps_cpu < NR_CPUS && cpu_present(mps_cpu)) |
f6bc4029 | 133 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); |
1da177e4 LT |
134 | else |
135 | return BAD_APICID; | |
136 | } | |
137 | ||
138 | static inline physid_mask_t apicid_to_cpu_present(int phys_apicid) | |
139 | { | |
140 | return physid_mask_of_physid(phys_apicid); | |
141 | } | |
142 | ||
1da177e4 LT |
143 | static inline void setup_portio_remap(void) |
144 | { | |
145 | } | |
146 | ||
147 | static inline int check_phys_apicid_present(int boot_cpu_physical_apicid) | |
148 | { | |
149 | return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map); | |
150 | } | |
151 | ||
1da177e4 LT |
152 | static inline void enable_apic_mode(void) |
153 | { | |
154 | } | |
dd46e3ca | 155 | #endif /* CONFIG_X86_LOCAL_APIC */ |
77ef50a5 | 156 | #endif /* ASM_X86__MACH_DEFAULT__MACH_APIC_H */ |