[linux-block.git] / include / asm-x86 / mach-bigsmp / mach_apic.h

#ifndef __ASM_MACH_APIC_H
#define __ASM_MACH_APIC_H

#define xapic_phys_to_log_apicid(cpu) (per_cpu(x86_bios_cpu_apicid, cpu))
#define esr_disable (1)

static inline int apic_id_registered(void)
{
	return (1);
}

/* Round robin the irqs amoung the online cpus */
static inline cpumask_t target_cpus(void)
{ 
	static unsigned long cpu = NR_CPUS;
	do {
		if (cpu >= NR_CPUS)
			cpu = first_cpu(cpu_online_map);
		else
			cpu = next_cpu(cpu, cpu_online_map);
	} while (cpu >= NR_CPUS);
	return cpumask_of_cpu(cpu);
}

#undef APIC_DEST_LOGICAL
#define APIC_DEST_LOGICAL 	0
#define TARGET_CPUS		(target_cpus())
#define APIC_DFR_VALUE		(APIC_DFR_FLAT)
#define INT_DELIVERY_MODE	(dest_Fixed)
#define INT_DEST_MODE		(0)    /* phys delivery to target proc */
#define NO_BALANCE_IRQ		(0)
#define WAKE_SECONDARY_VIA_INIT


static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
{
	return (0);
}

static inline unsigned long check_apicid_present(int bit)
{
	return (1);
}

static inline unsigned long calculate_ldr(int cpu)
{
	unsigned long val, id;
	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
	id = xapic_phys_to_log_apicid(cpu);
	val |= SET_APIC_LOGICAL_ID(id);
	return val;
}

/*
 * Set up the logical destination ID.
 *
 * Intel recommends to set DFR, LDR and TPR before enabling
 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
 * document number 292116).  So here it goes...
 */
static inline void init_apic_ldr(void)
{
	unsigned long val;
	int cpu = smp_processor_id();

	apic_write(APIC_DFR, APIC_DFR_VALUE);
	val = calculate_ldr(cpu);
	apic_write(APIC_LDR, val);
}

static inline void setup_apic_routing(void)
{
	printk("Enabling APIC mode:  %s.  Using %d I/O APICs\n",
		"Physflat", nr_ioapics);
}

static inline int multi_timer_check(int apic, int irq)
{
	return (0);
}

static inline int apicid_to_node(int logical_apicid)
{
	return apicid_2_node[hard_smp_processor_id()];
}

static inline int cpu_present_to_apicid(int mps_cpu)
{
	if (mps_cpu < NR_CPUS)
		return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);

	return BAD_APICID;
}

static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
{
	return physid_mask_of_physid(phys_apicid);
}

extern u8 cpu_2_logical_apicid[];
/* Mapping from cpu number to logical apicid */
static inline int cpu_to_logical_apicid(int cpu)
{
	if (cpu >= NR_CPUS)
		return BAD_APICID;
	return cpu_physical_id(cpu);
}

static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
{
	/* For clustered we don't have a good way to do this yet - hack */
	return physids_promote(0xFFL);
}

static inline void setup_portio_remap(void)
{
}

static inline void enable_apic_mode(void)
{
}

static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
{
	return (1);
}

/* As we are using single CPU as destination, pick only one CPU here */
static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
{
	int cpu;
	int apicid;	

	cpu = first_cpu(cpumask);
	apicid = cpu_to_logical_apicid(cpu);
	return apicid;
}

static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
{
	return cpuid_apic >> index_msb;
}

#endif /* __ASM_MACH_APIC_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_MACH_APIC_H
1da177e4 LT	2	#define __ASM_MACH_APIC_H
1855a2c4	3
cbe879fc	4	#define xapic_phys_to_log_apicid(cpu) (per_cpu(x86_bios_cpu_apicid, cpu))
1da177e4 LT	5	#define esr_disable (1)
1da177e4 LT	6
1da177e4 LT	7	static inline int apic_id_registered(void)
	8	{
	9	return (1);
	10	}
	11
1da177e4 LT	12	/* Round robin the irqs amoung the online cpus */
	13	static inline cpumask_t target_cpus(void)
	14	{
	15	static unsigned long cpu = NR_CPUS;
	16	do {
	17	if (cpu >= NR_CPUS)
	18	cpu = first_cpu(cpu_online_map);
	19	else
	20	cpu = next_cpu(cpu, cpu_online_map);
	21	} while (cpu >= NR_CPUS);
	22	return cpumask_of_cpu(cpu);
	23	}
1da177e4	24
1855a2c4 AR	25	#undef APIC_DEST_LOGICAL
	26	#define APIC_DEST_LOGICAL 0
	27	#define TARGET_CPUS (target_cpus())
	28	#define APIC_DFR_VALUE (APIC_DFR_FLAT)
	29	#define INT_DELIVERY_MODE (dest_Fixed)
	30	#define INT_DEST_MODE (0) /* phys delivery to target proc */
	31	#define NO_BALANCE_IRQ (0)
	32	#define WAKE_SECONDARY_VIA_INIT
	33
1da177e4 LT	34
	35	static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
	36	{
1855a2c4	37	return (0);
1da177e4 LT	38	}
1da177e4 LT	39
1855a2c4	40	static inline unsigned long check_apicid_present(int bit)
1da177e4	41	{
1855a2c4	42	return (1);
1da177e4 LT	43	}
1da177e4 LT	44
1855a2c4	45	static inline unsigned long calculate_ldr(int cpu)
1da177e4	46	{
1855a2c4 AR	47	unsigned long val, id;
	48	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
	49	id = xapic_phys_to_log_apicid(cpu);
	50	val \|= SET_APIC_LOGICAL_ID(id);
	51	return val;
1da177e4 LT	52	}
	53
	54	/*
	55	* Set up the logical destination ID.
	56	*
	57	* Intel recommends to set DFR, LDR and TPR before enabling
	58	* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
	59	* document number 292116). So here it goes...
	60	*/
	61	static inline void init_apic_ldr(void)
	62	{
	63	unsigned long val;
1855a2c4	64	int cpu = smp_processor_id();
1da177e4	65
593f4a78	66	apic_write(APIC_DFR, APIC_DFR_VALUE);
1855a2c4	67	val = calculate_ldr(cpu);
593f4a78	68	apic_write(APIC_LDR, val);
1da177e4 LT	69	}
1da177e4 LT	70
3c43f039	71	static inline void setup_apic_routing(void)
1da177e4 LT	72	{
1da177e4 LT	73	printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
1855a2c4	74	"Physflat", nr_ioapics);
1da177e4 LT	75	}
	76
	77	static inline int multi_timer_check(int apic, int irq)
	78	{
1855a2c4	79	return (0);
1da177e4 LT	80	}
	81
	82	static inline int apicid_to_node(int logical_apicid)
	83	{
f47f9d53	84	return apicid_2_node[hard_smp_processor_id()];
1da177e4 LT	85	}
1da177e4 LT	86
1da177e4 LT	87	static inline int cpu_present_to_apicid(int mps_cpu)
	88	{
	89	if (mps_cpu < NR_CPUS)
cbe879fc	90	return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);
1855a2c4 AR	91
1855a2c4 AR	92	return BAD_APICID;
1da177e4 LT	93	}
	94
	95	static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
	96	{
	97	return physid_mask_of_physid(phys_apicid);
	98	}
	99
	100	extern u8 cpu_2_logical_apicid[];
	101	/* Mapping from cpu number to logical apicid */
	102	static inline int cpu_to_logical_apicid(int cpu)
	103	{
1855a2c4 AR	104	if (cpu >= NR_CPUS)
	105	return BAD_APICID;
	106	return cpu_physical_id(cpu);
	107	}
1da177e4	108
1da177e4 LT	109	static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
	110	{
	111	/* For clustered we don't have a good way to do this yet - hack */
1855a2c4	112	return physids_promote(0xFFL);
1da177e4 LT	113	}
1da177e4 LT	114
1da177e4 LT	115	static inline void setup_portio_remap(void)
	116	{
	117	}
	118
	119	static inline void enable_apic_mode(void)
	120	{
	121	}
	122
	123	static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
	124	{
	125	return (1);
	126	}
	127
	128	/* As we are using single CPU as destination, pick only one CPU here */
	129	static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
	130	{
	131	int cpu;
	132	int apicid;
	133
	134	cpu = first_cpu(cpumask);
	135	apicid = cpu_to_logical_apicid(cpu);
	136	return apicid;
	137	}
	138
	139	static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
	140	{
	141	return cpuid_apic >> index_msb;
	142	}
	143
	144	#endif /* __ASM_MACH_APIC_H */