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f6a40e3b JY |
1 | #ifndef __LINUX_KVM_X86_H |
2 | #define __LINUX_KVM_X86_H | |
3 | ||
4 | /* | |
5 | * KVM x86 specific structures and definitions | |
6 | * | |
7 | */ | |
8 | ||
9 | #include <asm/types.h> | |
10 | #include <linux/ioctl.h> | |
11 | ||
244d57ec JY |
12 | /* Architectural interrupt line count. */ |
13 | #define KVM_NR_INTERRUPTS 256 | |
14 | ||
f6a40e3b JY |
15 | struct kvm_memory_alias { |
16 | __u32 slot; /* this has a different namespace than memory slots */ | |
17 | __u32 flags; | |
18 | __u64 guest_phys_addr; | |
19 | __u64 memory_size; | |
20 | __u64 target_phys_addr; | |
21 | }; | |
22 | ||
da1386a5 JY |
23 | /* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */ |
24 | struct kvm_pic_state { | |
25 | __u8 last_irr; /* edge detection */ | |
26 | __u8 irr; /* interrupt request register */ | |
27 | __u8 imr; /* interrupt mask register */ | |
28 | __u8 isr; /* interrupt service register */ | |
29 | __u8 priority_add; /* highest irq priority */ | |
30 | __u8 irq_base; | |
31 | __u8 read_reg_select; | |
32 | __u8 poll; | |
33 | __u8 special_mask; | |
34 | __u8 init_state; | |
35 | __u8 auto_eoi; | |
36 | __u8 rotate_on_auto_eoi; | |
37 | __u8 special_fully_nested_mode; | |
38 | __u8 init4; /* true if 4 byte init */ | |
39 | __u8 elcr; /* PIIX edge/trigger selection */ | |
40 | __u8 elcr_mask; | |
41 | }; | |
42 | ||
43 | #define KVM_IOAPIC_NUM_PINS 24 | |
44 | struct kvm_ioapic_state { | |
45 | __u64 base_address; | |
46 | __u32 ioregsel; | |
47 | __u32 id; | |
48 | __u32 irr; | |
49 | __u32 pad; | |
50 | union { | |
51 | __u64 bits; | |
52 | struct { | |
53 | __u8 vector; | |
54 | __u8 delivery_mode:3; | |
55 | __u8 dest_mode:1; | |
56 | __u8 delivery_status:1; | |
57 | __u8 polarity:1; | |
58 | __u8 remote_irr:1; | |
59 | __u8 trig_mode:1; | |
60 | __u8 mask:1; | |
61 | __u8 reserve:7; | |
62 | __u8 reserved[4]; | |
63 | __u8 dest_id; | |
64 | } fields; | |
65 | } redirtbl[KVM_IOAPIC_NUM_PINS]; | |
66 | }; | |
67 | ||
68 | #define KVM_IRQCHIP_PIC_MASTER 0 | |
69 | #define KVM_IRQCHIP_PIC_SLAVE 1 | |
70 | #define KVM_IRQCHIP_IOAPIC 2 | |
71 | ||
19d30b16 JY |
72 | /* for KVM_GET_REGS and KVM_SET_REGS */ |
73 | struct kvm_regs { | |
74 | /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */ | |
75 | __u64 rax, rbx, rcx, rdx; | |
76 | __u64 rsi, rdi, rsp, rbp; | |
77 | __u64 r8, r9, r10, r11; | |
78 | __u64 r12, r13, r14, r15; | |
79 | __u64 rip, rflags; | |
80 | }; | |
81 | ||
d9ecf928 JY |
82 | /* for KVM_GET_LAPIC and KVM_SET_LAPIC */ |
83 | #define KVM_APIC_REG_SIZE 0x400 | |
84 | struct kvm_lapic_state { | |
85 | char regs[KVM_APIC_REG_SIZE]; | |
86 | }; | |
87 | ||
3a56b201 JY |
88 | struct kvm_segment { |
89 | __u64 base; | |
90 | __u32 limit; | |
91 | __u16 selector; | |
92 | __u8 type; | |
93 | __u8 present, dpl, db, s, l, g, avl; | |
94 | __u8 unusable; | |
95 | __u8 padding; | |
96 | }; | |
97 | ||
98 | struct kvm_dtable { | |
99 | __u64 base; | |
100 | __u16 limit; | |
101 | __u16 padding[3]; | |
102 | }; | |
103 | ||
104 | ||
244d57ec JY |
105 | /* for KVM_GET_SREGS and KVM_SET_SREGS */ |
106 | struct kvm_sregs { | |
107 | /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */ | |
108 | struct kvm_segment cs, ds, es, fs, gs, ss; | |
109 | struct kvm_segment tr, ldt; | |
110 | struct kvm_dtable gdt, idt; | |
111 | __u64 cr0, cr2, cr3, cr4, cr8; | |
112 | __u64 efer; | |
113 | __u64 apic_base; | |
114 | __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64]; | |
115 | }; | |
116 | ||
6f723c79 CE |
117 | /* for KVM_GET_FPU and KVM_SET_FPU */ |
118 | struct kvm_fpu { | |
119 | __u8 fpr[8][16]; | |
120 | __u16 fcw; | |
121 | __u16 fsw; | |
122 | __u8 ftwx; /* in fxsave format */ | |
123 | __u8 pad1; | |
124 | __u16 last_opcode; | |
125 | __u64 last_ip; | |
126 | __u64 last_dp; | |
127 | __u8 xmm[16][16]; | |
128 | __u32 mxcsr; | |
129 | __u32 pad2; | |
130 | }; | |
131 | ||
244d57ec JY |
132 | struct kvm_msr_entry { |
133 | __u32 index; | |
134 | __u32 reserved; | |
135 | __u64 data; | |
136 | }; | |
137 | ||
138 | /* for KVM_GET_MSRS and KVM_SET_MSRS */ | |
139 | struct kvm_msrs { | |
140 | __u32 nmsrs; /* number of msrs in entries */ | |
141 | __u32 pad; | |
142 | ||
143 | struct kvm_msr_entry entries[0]; | |
144 | }; | |
145 | ||
146 | /* for KVM_GET_MSR_INDEX_LIST */ | |
147 | struct kvm_msr_list { | |
148 | __u32 nmsrs; /* number of msrs in entries */ | |
149 | __u32 indices[0]; | |
150 | }; | |
151 | ||
152 | ||
a162dd58 JY |
153 | struct kvm_cpuid_entry { |
154 | __u32 function; | |
155 | __u32 eax; | |
156 | __u32 ebx; | |
157 | __u32 ecx; | |
158 | __u32 edx; | |
159 | __u32 padding; | |
160 | }; | |
161 | ||
162 | /* for KVM_SET_CPUID */ | |
163 | struct kvm_cpuid { | |
164 | __u32 nent; | |
165 | __u32 padding; | |
166 | struct kvm_cpuid_entry entries[0]; | |
167 | }; | |
168 | ||
07716717 DK |
169 | struct kvm_cpuid_entry2 { |
170 | __u32 function; | |
171 | __u32 index; | |
172 | __u32 flags; | |
173 | __u32 eax; | |
174 | __u32 ebx; | |
175 | __u32 ecx; | |
176 | __u32 edx; | |
177 | __u32 padding[3]; | |
178 | }; | |
179 | ||
180 | #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX 1 | |
181 | #define KVM_CPUID_FLAG_STATEFUL_FUNC 2 | |
182 | #define KVM_CPUID_FLAG_STATE_READ_NEXT 4 | |
183 | ||
184 | /* for KVM_SET_CPUID2 */ | |
185 | struct kvm_cpuid2 { | |
186 | __u32 nent; | |
187 | __u32 padding; | |
188 | struct kvm_cpuid_entry2 entries[0]; | |
189 | }; | |
a162dd58 | 190 | |
e0f63cb9 SY |
191 | /* for KVM_GET_PIT and KVM_SET_PIT */ |
192 | struct kvm_pit_channel_state { | |
193 | __u32 count; /* can be 65536 */ | |
194 | __u16 latched_count; | |
195 | __u8 count_latched; | |
196 | __u8 status_latched; | |
197 | __u8 status; | |
198 | __u8 read_state; | |
199 | __u8 write_state; | |
200 | __u8 write_latch; | |
201 | __u8 rw_mode; | |
202 | __u8 mode; | |
203 | __u8 bcd; | |
204 | __u8 gate; | |
205 | __s64 count_load_time; | |
206 | }; | |
207 | ||
208 | struct kvm_pit_state { | |
209 | struct kvm_pit_channel_state channels[3]; | |
210 | }; | |
211 | ||
2714d1d3 FEL |
212 | #define KVM_TRC_INJ_VIRQ (KVM_TRC_HANDLER + 0x02) |
213 | #define KVM_TRC_REDELIVER_EVT (KVM_TRC_HANDLER + 0x03) | |
214 | #define KVM_TRC_PEND_INTR (KVM_TRC_HANDLER + 0x04) | |
215 | #define KVM_TRC_IO_READ (KVM_TRC_HANDLER + 0x05) | |
216 | #define KVM_TRC_IO_WRITE (KVM_TRC_HANDLER + 0x06) | |
217 | #define KVM_TRC_CR_READ (KVM_TRC_HANDLER + 0x07) | |
218 | #define KVM_TRC_CR_WRITE (KVM_TRC_HANDLER + 0x08) | |
219 | #define KVM_TRC_DR_READ (KVM_TRC_HANDLER + 0x09) | |
220 | #define KVM_TRC_DR_WRITE (KVM_TRC_HANDLER + 0x0A) | |
221 | #define KVM_TRC_MSR_READ (KVM_TRC_HANDLER + 0x0B) | |
222 | #define KVM_TRC_MSR_WRITE (KVM_TRC_HANDLER + 0x0C) | |
223 | #define KVM_TRC_CPUID (KVM_TRC_HANDLER + 0x0D) | |
224 | #define KVM_TRC_INTR (KVM_TRC_HANDLER + 0x0E) | |
225 | #define KVM_TRC_NMI (KVM_TRC_HANDLER + 0x0F) | |
226 | #define KVM_TRC_VMMCALL (KVM_TRC_HANDLER + 0x10) | |
227 | #define KVM_TRC_HLT (KVM_TRC_HANDLER + 0x11) | |
228 | #define KVM_TRC_CLTS (KVM_TRC_HANDLER + 0x12) | |
229 | #define KVM_TRC_LMSW (KVM_TRC_HANDLER + 0x13) | |
230 | #define KVM_TRC_APIC_ACCESS (KVM_TRC_HANDLER + 0x14) | |
d2ebb410 | 231 | #define KVM_TRC_TDP_FAULT (KVM_TRC_HANDLER + 0x15) |
2714d1d3 | 232 | |
f6a40e3b | 233 | #endif |