[linux-2.6-block.git] / include / asm-x86 / i8259.h

#ifndef __ASM_I8259_H__
#define __ASM_I8259_H__

#include <linux/delay.h>

extern unsigned int cached_irq_mask;

#define __byte(x,y)		(((unsigned char *) &(y))[x])
#define cached_master_mask	(__byte(0, cached_irq_mask))
#define cached_slave_mask	(__byte(1, cached_irq_mask))

/* i8259A PIC registers */
#define PIC_MASTER_CMD		0x20
#define PIC_MASTER_IMR		0x21
#define PIC_MASTER_ISR		PIC_MASTER_CMD
#define PIC_MASTER_POLL		PIC_MASTER_ISR
#define PIC_MASTER_OCW3		PIC_MASTER_ISR
#define PIC_SLAVE_CMD		0xa0
#define PIC_SLAVE_IMR		0xa1

/* i8259A PIC related value */
#define PIC_CASCADE_IR		2
#define MASTER_ICW4_DEFAULT	0x01
#define SLAVE_ICW4_DEFAULT	0x01
#define PIC_ICW4_AEOI		2

extern spinlock_t i8259A_lock;

extern void init_8259A(int auto_eoi);
extern void enable_8259A_irq(unsigned int irq);
extern void disable_8259A_irq(unsigned int irq);
extern unsigned int startup_8259A_irq(unsigned int irq);

/* the PIC may need a careful delay on some platforms, hence specific calls */
static inline unsigned char inb_pic(unsigned int port)
{
	unsigned char value = inb(port);

	/*
	 * delay for some accesses to PIC on motherboard or in chipset
	 * must be at least one microsecond, so be safe here:
	 */
	udelay(2);

	return value;
}

static inline void outb_pic(unsigned char value, unsigned int port)
{
	outb(value, port);
	/*
	 * delay for some accesses to PIC on motherboard or in chipset
	 * must be at least one microsecond, so be safe here:
	 */
	udelay(2);
}

#endif	/* __ASM_I8259_H__ */
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_I8259_H__
	2	#define __ASM_I8259_H__
	3
bc0a733f DR	4	#include <linux/delay.h>
bc0a733f DR	5
1da177e4 LT	6	extern unsigned int cached_irq_mask;
1da177e4 LT	7
f20ebee4	8	#define __byte(x,y) (((unsigned char *) &(y))[x])
1da177e4 LT	9	#define cached_master_mask (__byte(0, cached_irq_mask))
	10	#define cached_slave_mask (__byte(1, cached_irq_mask))
	11
f20ebee4 TG	12	/* i8259A PIC registers */
	13	#define PIC_MASTER_CMD 0x20
	14	#define PIC_MASTER_IMR 0x21
	15	#define PIC_MASTER_ISR PIC_MASTER_CMD
	16	#define PIC_MASTER_POLL PIC_MASTER_ISR
	17	#define PIC_MASTER_OCW3 PIC_MASTER_ISR
	18	#define PIC_SLAVE_CMD 0xa0
	19	#define PIC_SLAVE_IMR 0xa1
	20
	21	/* i8259A PIC related value */
	22	#define PIC_CASCADE_IR 2
	23	#define MASTER_ICW4_DEFAULT 0x01
	24	#define SLAVE_ICW4_DEFAULT 0x01
	25	#define PIC_ICW4_AEOI 2
	26
1da177e4 LT	27	extern spinlock_t i8259A_lock;
	28
	29	extern void init_8259A(int auto_eoi);
	30	extern void enable_8259A_irq(unsigned int irq);
	31	extern void disable_8259A_irq(unsigned int irq);
	32	extern unsigned int startup_8259A_irq(unsigned int irq);
	33
bc0a733f DR	34	/* the PIC may need a careful delay on some platforms, hence specific calls */
	35	static inline unsigned char inb_pic(unsigned int port)
	36	{
	37	unsigned char value = inb(port);
	38
	39	/*
	40	* delay for some accesses to PIC on motherboard or in chipset
	41	* must be at least one microsecond, so be safe here:
	42	*/
	43	udelay(2);
	44
	45	return value;
	46	}
	47
	48	static inline void outb_pic(unsigned char value, unsigned int port)
	49	{
	50	outb(value, port);
	51	/*
	52	* delay for some accesses to PIC on motherboard or in chipset
	53	* must be at least one microsecond, so be safe here:
	54	*/
	55	udelay(2);
	56	}
466eed22	57
1da177e4	58	#endif /* __ASM_I8259_H__ */