[linux-block.git] / include / asm-x86 / desc.h

#ifndef _ASM_DESC_H_
#define _ASM_DESC_H_

#ifndef __ASSEMBLY__
#include <asm/desc_defs.h>
#include <asm/ldt.h>
#include <asm/mmu.h>
#include <linux/smp.h>

static inline void fill_ldt(struct desc_struct *desc,
			    const struct user_desc *info)
{
	desc->limit0 = info->limit & 0x0ffff;
	desc->base0 = info->base_addr & 0x0000ffff;

	desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
	desc->type = (info->read_exec_only ^ 1) << 1;
	desc->type |= info->contents << 2;
	desc->s = 1;
	desc->dpl = 0x3;
	desc->p = info->seg_not_present ^ 1;
	desc->limit = (info->limit & 0xf0000) >> 16;
	desc->avl = info->useable;
	desc->d = info->seg_32bit;
	desc->g = info->limit_in_pages;
	desc->base2 = (info->base_addr & 0xff000000) >> 24;
}

extern struct desc_ptr idt_descr;
extern gate_desc idt_table[];

struct gdt_page {
	struct desc_struct gdt[GDT_ENTRIES];
} __attribute__((aligned(PAGE_SIZE)));
DECLARE_PER_CPU(struct gdt_page, gdt_page);

static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
{
	return per_cpu(gdt_page, cpu).gdt;
}

#ifdef CONFIG_X86_64

static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
			     unsigned dpl, unsigned ist, unsigned seg)
{
	gate->offset_low = PTR_LOW(func);
	gate->segment = __KERNEL_CS;
	gate->ist = ist;
	gate->p = 1;
	gate->dpl = dpl;
	gate->zero0 = 0;
	gate->zero1 = 0;
	gate->type = type;
	gate->offset_middle = PTR_MIDDLE(func);
	gate->offset_high = PTR_HIGH(func);
}

#else
static inline void pack_gate(gate_desc *gate, unsigned char type,
			     unsigned long base, unsigned dpl, unsigned flags,
			     unsigned short seg)
{
	gate->a = (seg << 16) | (base & 0xffff);
	gate->b = (base & 0xffff0000) |
		  (((0x80 | type | (dpl << 5)) & 0xff) << 8);
}

#endif

static inline int desc_empty(const void *ptr)
{
	const u32 *desc = ptr;
	return !(desc[0] | desc[1]);
}

#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#else
#define load_TR_desc() native_load_tr_desc()
#define load_gdt(dtr) native_load_gdt(dtr)
#define load_idt(dtr) native_load_idt(dtr)
#define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
#define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))

#define store_gdt(dtr) native_store_gdt(dtr)
#define store_idt(dtr) native_store_idt(dtr)
#define store_tr(tr) (tr = native_store_tr())
#define store_ldt(ldt) asm("sldt %0":"=m" (ldt))

#define load_TLS(t, cpu) native_load_tls(t, cpu)
#define set_ldt native_set_ldt

#define write_ldt_entry(dt, entry, desc)	\
	native_write_ldt_entry(dt, entry, desc)
#define write_gdt_entry(dt, entry, desc, type)		\
	native_write_gdt_entry(dt, entry, desc, type)
#define write_idt_entry(dt, entry, g)		\
	native_write_idt_entry(dt, entry, g)

static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
{
}

static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
{
}
#endif	/* CONFIG_PARAVIRT */

static inline void native_write_idt_entry(gate_desc *idt, int entry,
					  const gate_desc *gate)
{
	memcpy(&idt[entry], gate, sizeof(*gate));
}

static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry,
					  const void *desc)
{
	memcpy(&ldt[entry], desc, 8);
}

static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry,
					  const void *desc, int type)
{
	unsigned int size;
	switch (type) {
	case DESC_TSS:
		size = sizeof(tss_desc);
		break;
	case DESC_LDT:
		size = sizeof(ldt_desc);
		break;
	default:
		size = sizeof(struct desc_struct);
		break;
	}
	memcpy(&gdt[entry], desc, size);
}

static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
				   unsigned long limit, unsigned char type,
				   unsigned char flags)
{
	desc->a = ((base & 0xffff) << 16) | (limit & 0xffff);
	desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) |
		(limit & 0x000f0000) | ((type & 0xff) << 8) |
		((flags & 0xf) << 20);
	desc->p = 1;
}


static inline void set_tssldt_descriptor(void *d, unsigned long addr,
					 unsigned type, unsigned size)
{
#ifdef CONFIG_X86_64
	struct ldttss_desc64 *desc = d;
	memset(desc, 0, sizeof(*desc));
	desc->limit0 = size & 0xFFFF;
	desc->base0 = PTR_LOW(addr);
	desc->base1 = PTR_MIDDLE(addr) & 0xFF;
	desc->type = type;
	desc->p = 1;
	desc->limit1 = (size >> 16) & 0xF;
	desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF;
	desc->base3 = PTR_HIGH(addr);
#else
	pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0);
#endif
}

static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
{
	struct desc_struct *d = get_cpu_gdt_table(cpu);
	tss_desc tss;

	/*
	 * sizeof(unsigned long) coming from an extra "long" at the end
	 * of the iobitmap. See tss_struct definition in processor.h
	 *
	 * -1? seg base+limit should be pointing to the address of the
	 * last valid byte
	 */
	set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
			      IO_BITMAP_OFFSET + IO_BITMAP_BYTES +
			      sizeof(unsigned long) - 1);
	write_gdt_entry(d, entry, &tss, DESC_TSS);
}

#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)

static inline void native_set_ldt(const void *addr, unsigned int entries)
{
	if (likely(entries == 0))
		asm volatile("lldt %w0"::"q" (0));
	else {
		unsigned cpu = smp_processor_id();
		ldt_desc ldt;

		set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
				      entries * LDT_ENTRY_SIZE - 1);
		write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
				&ldt, DESC_LDT);
		asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
	}
}

static inline void native_load_tr_desc(void)
{
	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
}

static inline void native_load_gdt(const struct desc_ptr *dtr)
{
	asm volatile("lgdt %0"::"m" (*dtr));
}

static inline void native_load_idt(const struct desc_ptr *dtr)
{
	asm volatile("lidt %0"::"m" (*dtr));
}

static inline void native_store_gdt(struct desc_ptr *dtr)
{
	asm volatile("sgdt %0":"=m" (*dtr));
}

static inline void native_store_idt(struct desc_ptr *dtr)
{
	asm volatile("sidt %0":"=m" (*dtr));
}

static inline unsigned long native_store_tr(void)
{
	unsigned long tr;
	asm volatile("str %0":"=r" (tr));
	return tr;
}

static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
{
	unsigned int i;
	struct desc_struct *gdt = get_cpu_gdt_table(cpu);

	for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
		gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
}

#define _LDT_empty(info)				\
	((info)->base_addr		== 0	&&	\
	 (info)->limit			== 0	&&	\
	 (info)->contents		== 0	&&	\
	 (info)->read_exec_only		== 1	&&	\
	 (info)->seg_32bit		== 0	&&	\
	 (info)->limit_in_pages		== 0	&&	\
	 (info)->seg_not_present	== 1	&&	\
	 (info)->useable		== 0)

#ifdef CONFIG_X86_64
#define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
#else
#define LDT_empty(info) (_LDT_empty(info))
#endif

static inline void clear_LDT(void)
{
	set_ldt(NULL, 0);
}

/*
 * load one particular LDT into the current CPU
 */
static inline void load_LDT_nolock(mm_context_t *pc)
{
	set_ldt(pc->ldt, pc->size);
}

static inline void load_LDT(mm_context_t *pc)
{
	preempt_disable();
	load_LDT_nolock(pc);
	preempt_enable();
}

static inline unsigned long get_desc_base(const struct desc_struct *desc)
{
	return desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24);
}

static inline unsigned long get_desc_limit(const struct desc_struct *desc)
{
	return desc->limit0 | (desc->limit << 16);
}

static inline void _set_gate(int gate, unsigned type, void *addr,
			     unsigned dpl, unsigned ist, unsigned seg)
{
	gate_desc s;
	pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
	/*
	 * does not need to be atomic because it is only done once at
	 * setup time
	 */
	write_idt_entry(idt_table, gate, &s);
}

/*
 * This needs to use 'idt_table' rather than 'idt', and
 * thus use the _nonmapped_ version of the IDT, as the
 * Pentium F0 0F bugfix can have resulted in the mapped
 * IDT being write-protected.
 */
static inline void set_intr_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS);
}

#define SYS_VECTOR_FREE		0
#define SYS_VECTOR_ALLOCED	1

extern int first_system_vector;
extern char system_vectors[];

static inline void alloc_system_vector(int vector)
{
	if (system_vectors[vector] == SYS_VECTOR_FREE) {
		system_vectors[vector] = SYS_VECTOR_ALLOCED;
		if (first_system_vector > vector)
			first_system_vector = vector;
	} else
		BUG();
}

static inline void alloc_intr_gate(unsigned int n, void *addr)
{
	alloc_system_vector(n);
	set_intr_gate(n, addr);
}

/*
 * This routine sets up an interrupt gate at directory privilege level 3.
 */
static inline void set_system_intr_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
}

static inline void set_trap_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
}

static inline void set_system_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
#ifdef CONFIG_X86_32
	_set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
#else
	_set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
#endif
}

static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
}

static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
}

static inline void set_system_gate_ist(int n, void *addr, unsigned ist)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
}

#else
/*
 * GET_DESC_BASE reads the descriptor base of the specified segment.
 *
 * Args:
 *    idx - descriptor index
 *    gdt - GDT pointer
 *    base - 32bit register to which the base will be written
 *    lo_w - lo word of the "base" register
 *    lo_b - lo byte of the "base" register
 *    hi_b - hi byte of the low word of the "base" register
 *
 * Example:
 *    GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah)
 *    Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax.
 */
#define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \
	movb idx * 8 + 4(gdt), lo_b;			\
	movb idx * 8 + 7(gdt), hi_b;			\
	shll $16, base;					\
	movw idx * 8 + 2(gdt), lo_w;


#endif /* __ASSEMBLY__ */

#endif
Commit	Line	Data
80fbb69a GOC	1	#ifndef _ASM_DESC_H_
	2	#define _ASM_DESC_H_
	3
	4	#ifndef __ASSEMBLY__
	5	#include <asm/desc_defs.h>
	6	#include <asm/ldt.h>
881c2975	7	#include <asm/mmu.h>
54cd0eac	8	#include <linux/smp.h>
80fbb69a	9
1bd5718c RM	10	static inline void fill_ldt(struct desc_struct *desc,
1bd5718c RM	11	const struct user_desc *info)
80fbb69a GOC	12	{
	13	desc->limit0 = info->limit & 0x0ffff;
	14	desc->base0 = info->base_addr & 0x0000ffff;
	15
	16	desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
	17	desc->type = (info->read_exec_only ^ 1) << 1;
	18	desc->type \|= info->contents << 2;
	19	desc->s = 1;
	20	desc->dpl = 0x3;
	21	desc->p = info->seg_not_present ^ 1;
	22	desc->limit = (info->limit & 0xf0000) >> 16;
	23	desc->avl = info->useable;
	24	desc->d = info->seg_32bit;
	25	desc->g = info->limit_in_pages;
	26	desc->base2 = (info->base_addr & 0xff000000) >> 24;
	27	}
	28
881c2975 GOC	29	extern struct desc_ptr idt_descr;
881c2975 GOC	30	extern gate_desc idt_table[];
80fbb69a	31
a939098a GC	32	struct gdt_page {
	33	struct desc_struct gdt[GDT_ENTRIES];
	34	} __attribute__((aligned(PAGE_SIZE)));
	35	DECLARE_PER_CPU(struct gdt_page, gdt_page);
	36
	37	static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
	38	{
	39	return per_cpu(gdt_page, cpu).gdt;
	40	}
	41
54cd0eac	42	#ifdef CONFIG_X86_64
507f90c9 GOC	43
	44	static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
	45	unsigned dpl, unsigned ist, unsigned seg)
	46	{
	47	gate->offset_low = PTR_LOW(func);
	48	gate->segment = __KERNEL_CS;
	49	gate->ist = ist;
	50	gate->p = 1;
	51	gate->dpl = dpl;
	52	gate->zero0 = 0;
	53	gate->zero1 = 0;
	54	gate->type = type;
	55	gate->offset_middle = PTR_MIDDLE(func);
	56	gate->offset_high = PTR_HIGH(func);
	57	}
	58
54cd0eac	59	#else
507f90c9	60	static inline void pack_gate(gate_desc *gate, unsigned char type,
c1773a16 JP	61	unsigned long base, unsigned dpl, unsigned flags,
c1773a16 JP	62	unsigned short seg)
507f90c9 GOC	63	{
	64	gate->a = (seg << 16) \| (base & 0xffff);
	65	gate->b = (base & 0xffff0000) \|
	66	(((0x80 \| type \| (dpl << 5)) & 0xff) << 8);
	67	}
	68
54cd0eac GOC	69	#endif
54cd0eac GOC	70
746ff60f GOC	71	static inline int desc_empty(const void *ptr)
	72	{
	73	const u32 *desc = ptr;
	74	return !(desc[0] \| desc[1]);
	75	}
	76
54cd0eac GOC	77	#ifdef CONFIG_PARAVIRT
	78	#include <asm/paravirt.h>
	79	#else
	80	#define load_TR_desc() native_load_tr_desc()
	81	#define load_gdt(dtr) native_load_gdt(dtr)
	82	#define load_idt(dtr) native_load_idt(dtr)
c1773a16 JP	83	#define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
c1773a16 JP	84	#define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))
54cd0eac GOC	85
	86	#define store_gdt(dtr) native_store_gdt(dtr)
	87	#define store_idt(dtr) native_store_idt(dtr)
	88	#define store_tr(tr) (tr = native_store_tr())
c1773a16	89	#define store_ldt(ldt) asm("sldt %0":"=m" (ldt))
54cd0eac GOC	90
	91	#define load_TLS(t, cpu) native_load_tls(t, cpu)
	92	#define set_ldt native_set_ldt
	93
c1773a16 JP	94	#define write_ldt_entry(dt, entry, desc) \
	95	native_write_ldt_entry(dt, entry, desc)
	96	#define write_gdt_entry(dt, entry, desc, type) \
	97	native_write_gdt_entry(dt, entry, desc, type)
	98	#define write_idt_entry(dt, entry, g) \
	99	native_write_idt_entry(dt, entry, g)
38ffbe66 JF	100
	101	static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
	102	{
	103	}
	104
	105	static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
	106	{
	107	}
	108	#endif /* CONFIG_PARAVIRT */
54cd0eac GOC	109
	110	static inline void native_write_idt_entry(gate_desc *idt, int entry,
	111	const gate_desc *gate)
	112	{
	113	memcpy(&idt[entry], gate, sizeof(*gate));
	114	}
	115
	116	static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry,
	117	const void *desc)
	118	{
	119	memcpy(&ldt[entry], desc, 8);
	120	}
	121
	122	static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry,
	123	const void *desc, int type)
	124	{
	125	unsigned int size;
	126	switch (type) {
	127	case DESC_TSS:
	128	size = sizeof(tss_desc);
	129	break;
	130	case DESC_LDT:
	131	size = sizeof(ldt_desc);
	132	break;
	133	default:
	134	size = sizeof(struct desc_struct);
	135	break;
	136	}
	137	memcpy(&gdt[entry], desc, size);
	138	}
	139
54cd0eac GOC	140	static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
	141	unsigned long limit, unsigned char type,
	142	unsigned char flags)
	143	{
	144	desc->a = ((base & 0xffff) << 16) \| (limit & 0xffff);
	145	desc->b = (base & 0xff000000) \| ((base & 0xff0000) >> 16) \|
c1773a16 JP	146	(limit & 0x000f0000) \| ((type & 0xff) << 8) \|
c1773a16 JP	147	((flags & 0xf) << 20);
54cd0eac GOC	148	desc->p = 1;
	149	}
	150
54cd0eac	151
f6e0eba1 GOC	152	static inline void set_tssldt_descriptor(void *d, unsigned long addr,
f6e0eba1 GOC	153	unsigned type, unsigned size)
c81c6ca4 GOC	154	{
c81c6ca4 GOC	155	#ifdef CONFIG_X86_64
f6e0eba1 GOC	156	struct ldttss_desc64 *desc = d;
	157	memset(desc, 0, sizeof(*desc));
	158	desc->limit0 = size & 0xFFFF;
	159	desc->base0 = PTR_LOW(addr);
	160	desc->base1 = PTR_MIDDLE(addr) & 0xFF;
	161	desc->type = type;
	162	desc->p = 1;
	163	desc->limit1 = (size >> 16) & 0xF;
	164	desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF;
	165	desc->base3 = PTR_HIGH(addr);
c81c6ca4	166	#else
f6e0eba1	167	pack_descriptor((struct desc_struct *)d, addr, size, 0x80 \| type, 0);
c81c6ca4 GOC	168	#endif
	169	}
	170
	171	static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
	172	{
	173	struct desc_struct *d = get_cpu_gdt_table(cpu);
	174	tss_desc tss;
	175
	176	/*
	177	* sizeof(unsigned long) coming from an extra "long" at the end
	178	* of the iobitmap. See tss_struct definition in processor.h
	179	*
	180	* -1? seg base+limit should be pointing to the address of the
	181	* last valid byte
	182	*/
f6e0eba1	183	set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
c1773a16 JP	184	IO_BITMAP_OFFSET + IO_BITMAP_BYTES +
c1773a16 JP	185	sizeof(unsigned long) - 1);
c81c6ca4 GOC	186	write_gdt_entry(d, entry, &tss, DESC_TSS);
	187	}
	188
	189	#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
	190
54cd0eac GOC	191	static inline void native_set_ldt(const void *addr, unsigned int entries)
	192	{
	193	if (likely(entries == 0))
c1773a16	194	asm volatile("lldt %w0"::"q" (0));
54cd0eac GOC	195	else {
	196	unsigned cpu = smp_processor_id();
	197	ldt_desc ldt;
	198
5ac37f87 MK	199	set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
5ac37f87 MK	200	entries * LDT_ENTRY_SIZE - 1);
54cd0eac GOC	201	write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
54cd0eac GOC	202	&ldt, DESC_LDT);
c1773a16	203	asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
54cd0eac GOC	204	}
	205	}
	206
	207	static inline void native_load_tr_desc(void)
	208	{
	209	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
	210	}
	211
	212	static inline void native_load_gdt(const struct desc_ptr *dtr)
	213	{
	214	asm volatile("lgdt %0"::"m" (*dtr));
	215	}
	216
	217	static inline void native_load_idt(const struct desc_ptr *dtr)
	218	{
	219	asm volatile("lidt %0"::"m" (*dtr));
	220	}
	221
	222	static inline void native_store_gdt(struct desc_ptr *dtr)
	223	{
	224	asm volatile("sgdt %0":"=m" (*dtr));
	225	}
	226
	227	static inline void native_store_idt(struct desc_ptr *dtr)
	228	{
	229	asm volatile("sidt %0":"=m" (*dtr));
	230	}
	231
	232	static inline unsigned long native_store_tr(void)
	233	{
	234	unsigned long tr;
	235	asm volatile("str %0":"=r" (tr));
	236	return tr;
	237	}
	238
	239	static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
	240	{
	241	unsigned int i;
	242	struct desc_struct *gdt = get_cpu_gdt_table(cpu);
	243
	244	for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
	245	gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
	246	}
	247
c1773a16 JP	248	#define _LDT_empty(info) \
	249	((info)->base_addr == 0 && \
	250	(info)->limit == 0 && \
	251	(info)->contents == 0 && \
	252	(info)->read_exec_only == 1 && \
	253	(info)->seg_32bit == 0 && \
	254	(info)->limit_in_pages == 0 && \
	255	(info)->seg_not_present == 1 && \
	256	(info)->useable == 0)
881c2975 GOC	257
	258	#ifdef CONFIG_X86_64
	259	#define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
	260	#else
	261	#define LDT_empty(info) (_LDT_empty(info))
	262	#endif
	263
	264	static inline void clear_LDT(void)
	265	{
	266	set_ldt(NULL, 0);
	267	}
	268
	269	/*
	270	* load one particular LDT into the current CPU
	271	*/
	272	static inline void load_LDT_nolock(mm_context_t *pc)
	273	{
	274	set_ldt(pc->ldt, pc->size);
	275	}
	276
	277	static inline void load_LDT(mm_context_t *pc)
	278	{
	279	preempt_disable();
	280	load_LDT_nolock(pc);
	281	preempt_enable();
	282	}
	283
1bd5718c	284	static inline unsigned long get_desc_base(const struct desc_struct *desc)
cc697852 GOC	285	{
	286	return desc->base0 \| ((desc->base1) << 16) \| ((desc->base2) << 24);
	287	}
1bd5718c RM	288
	289	static inline unsigned long get_desc_limit(const struct desc_struct *desc)
	290	{
	291	return desc->limit0 \| (desc->limit << 16);
	292	}
	293
507f90c9	294	static inline void _set_gate(int gate, unsigned type, void *addr,
c1773a16	295	unsigned dpl, unsigned ist, unsigned seg)
507f90c9 GOC	296	{
	297	gate_desc s;
	298	pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
	299	/*
	300	* does not need to be atomic because it is only done once at
	301	* setup time
	302	*/
	303	write_idt_entry(idt_table, gate, &s);
	304	}
	305
	306	/*
	307	* This needs to use 'idt_table' rather than 'idt', and
	308	* thus use the _nonmapped_ version of the IDT, as the
	309	* Pentium F0 0F bugfix can have resulted in the mapped
	310	* IDT being write-protected.
	311	*/
	312	static inline void set_intr_gate(unsigned int n, void *addr)
	313	{
	314	BUG_ON((unsigned)n > 0xFF);
	315	_set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS);
	316	}
	317
305b92a2 AM	318	#define SYS_VECTOR_FREE 0
	319	#define SYS_VECTOR_ALLOCED 1
	320
	321	extern int first_system_vector;
	322	extern char system_vectors[];
	323
	324	static inline void alloc_system_vector(int vector)
	325	{
	326	if (system_vectors[vector] == SYS_VECTOR_FREE) {
	327	system_vectors[vector] = SYS_VECTOR_ALLOCED;
	328	if (first_system_vector > vector)
	329	first_system_vector = vector;
	330	} else
	331	BUG();
	332	}
	333
	334	static inline void alloc_intr_gate(unsigned int n, void *addr)
	335	{
	336	alloc_system_vector(n);
	337	set_intr_gate(n, addr);
	338	}
	339
507f90c9 GOC	340	/*
	341	* This routine sets up an interrupt gate at directory privilege level 3.
	342	*/
	343	static inline void set_system_intr_gate(unsigned int n, void *addr)
	344	{
	345	BUG_ON((unsigned)n > 0xFF);
	346	_set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
	347	}
	348
	349	static inline void set_trap_gate(unsigned int n, void *addr)
	350	{
	351	BUG_ON((unsigned)n > 0xFF);
	352	_set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
	353	}
	354
	355	static inline void set_system_gate(unsigned int n, void *addr)
	356	{
	357	BUG_ON((unsigned)n > 0xFF);
	358	#ifdef CONFIG_X86_32
	359	_set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
	360	#else
	361	_set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
	362	#endif
	363	}
	364
	365	static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
	366	{
	367	BUG_ON((unsigned)n > 0xFF);
	368	_set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
	369	}
	370
	371	static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
	372	{
	373	BUG_ON((unsigned)n > 0xFF);
	374	_set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
	375	}
	376
	377	static inline void set_system_gate_ist(int n, void *addr, unsigned ist)
	378	{
	379	BUG_ON((unsigned)n > 0xFF);
	380	_set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
	381	}
cc697852	382
881c2975 GOC	383	#else
	384	/*
	385	* GET_DESC_BASE reads the descriptor base of the specified segment.
	386	*
	387	* Args:
	388	* idx - descriptor index
	389	* gdt - GDT pointer
	390	* base - 32bit register to which the base will be written
	391	* lo_w - lo word of the "base" register
	392	* lo_b - lo byte of the "base" register
	393	* hi_b - hi byte of the low word of the "base" register
	394	*
	395	* Example:
	396	* GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah)
	397	* Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax.
	398	*/
	399	#define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \
c1773a16 JP	400	movb idx * 8 + 4(gdt), lo_b; \
	401	movb idx * 8 + 7(gdt), hi_b; \
	402	shll $16, base; \
	403	movw idx * 8 + 2(gdt), lo_w;
881c2975 GOC	404
	405
	406	#endif /* __ASSEMBLY__ */
	407
80fbb69a	408	#endif