Commit | Line | Data |
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80fbb69a GOC |
1 | #ifndef _ASM_DESC_H_ |
2 | #define _ASM_DESC_H_ | |
3 | ||
4 | #ifndef __ASSEMBLY__ | |
5 | #include <asm/desc_defs.h> | |
6 | #include <asm/ldt.h> | |
881c2975 | 7 | #include <asm/mmu.h> |
54cd0eac | 8 | #include <linux/smp.h> |
80fbb69a | 9 | |
1bd5718c RM |
10 | static inline void fill_ldt(struct desc_struct *desc, |
11 | const struct user_desc *info) | |
80fbb69a GOC |
12 | { |
13 | desc->limit0 = info->limit & 0x0ffff; | |
14 | desc->base0 = info->base_addr & 0x0000ffff; | |
15 | ||
16 | desc->base1 = (info->base_addr & 0x00ff0000) >> 16; | |
17 | desc->type = (info->read_exec_only ^ 1) << 1; | |
18 | desc->type |= info->contents << 2; | |
19 | desc->s = 1; | |
20 | desc->dpl = 0x3; | |
21 | desc->p = info->seg_not_present ^ 1; | |
22 | desc->limit = (info->limit & 0xf0000) >> 16; | |
23 | desc->avl = info->useable; | |
24 | desc->d = info->seg_32bit; | |
25 | desc->g = info->limit_in_pages; | |
26 | desc->base2 = (info->base_addr & 0xff000000) >> 24; | |
27 | } | |
28 | ||
881c2975 GOC |
29 | extern struct desc_ptr idt_descr; |
30 | extern gate_desc idt_table[]; | |
80fbb69a | 31 | |
a939098a GC |
32 | struct gdt_page { |
33 | struct desc_struct gdt[GDT_ENTRIES]; | |
34 | } __attribute__((aligned(PAGE_SIZE))); | |
35 | DECLARE_PER_CPU(struct gdt_page, gdt_page); | |
36 | ||
37 | static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu) | |
38 | { | |
39 | return per_cpu(gdt_page, cpu).gdt; | |
40 | } | |
41 | ||
54cd0eac | 42 | #ifdef CONFIG_X86_64 |
507f90c9 GOC |
43 | |
44 | static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func, | |
45 | unsigned dpl, unsigned ist, unsigned seg) | |
46 | { | |
47 | gate->offset_low = PTR_LOW(func); | |
48 | gate->segment = __KERNEL_CS; | |
49 | gate->ist = ist; | |
50 | gate->p = 1; | |
51 | gate->dpl = dpl; | |
52 | gate->zero0 = 0; | |
53 | gate->zero1 = 0; | |
54 | gate->type = type; | |
55 | gate->offset_middle = PTR_MIDDLE(func); | |
56 | gate->offset_high = PTR_HIGH(func); | |
57 | } | |
58 | ||
54cd0eac | 59 | #else |
507f90c9 | 60 | static inline void pack_gate(gate_desc *gate, unsigned char type, |
c1773a16 JP |
61 | unsigned long base, unsigned dpl, unsigned flags, |
62 | unsigned short seg) | |
507f90c9 GOC |
63 | { |
64 | gate->a = (seg << 16) | (base & 0xffff); | |
65 | gate->b = (base & 0xffff0000) | | |
66 | (((0x80 | type | (dpl << 5)) & 0xff) << 8); | |
67 | } | |
68 | ||
54cd0eac GOC |
69 | #endif |
70 | ||
746ff60f GOC |
71 | static inline int desc_empty(const void *ptr) |
72 | { | |
73 | const u32 *desc = ptr; | |
74 | return !(desc[0] | desc[1]); | |
75 | } | |
76 | ||
54cd0eac GOC |
77 | #ifdef CONFIG_PARAVIRT |
78 | #include <asm/paravirt.h> | |
79 | #else | |
80 | #define load_TR_desc() native_load_tr_desc() | |
81 | #define load_gdt(dtr) native_load_gdt(dtr) | |
82 | #define load_idt(dtr) native_load_idt(dtr) | |
c1773a16 JP |
83 | #define load_tr(tr) asm volatile("ltr %0"::"m" (tr)) |
84 | #define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt)) | |
54cd0eac GOC |
85 | |
86 | #define store_gdt(dtr) native_store_gdt(dtr) | |
87 | #define store_idt(dtr) native_store_idt(dtr) | |
88 | #define store_tr(tr) (tr = native_store_tr()) | |
c1773a16 | 89 | #define store_ldt(ldt) asm("sldt %0":"=m" (ldt)) |
54cd0eac GOC |
90 | |
91 | #define load_TLS(t, cpu) native_load_tls(t, cpu) | |
92 | #define set_ldt native_set_ldt | |
93 | ||
c1773a16 JP |
94 | #define write_ldt_entry(dt, entry, desc) \ |
95 | native_write_ldt_entry(dt, entry, desc) | |
96 | #define write_gdt_entry(dt, entry, desc, type) \ | |
97 | native_write_gdt_entry(dt, entry, desc, type) | |
98 | #define write_idt_entry(dt, entry, g) \ | |
99 | native_write_idt_entry(dt, entry, g) | |
54cd0eac GOC |
100 | #endif |
101 | ||
102 | static inline void native_write_idt_entry(gate_desc *idt, int entry, | |
103 | const gate_desc *gate) | |
104 | { | |
105 | memcpy(&idt[entry], gate, sizeof(*gate)); | |
106 | } | |
107 | ||
108 | static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, | |
109 | const void *desc) | |
110 | { | |
111 | memcpy(&ldt[entry], desc, 8); | |
112 | } | |
113 | ||
114 | static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry, | |
115 | const void *desc, int type) | |
116 | { | |
117 | unsigned int size; | |
118 | switch (type) { | |
119 | case DESC_TSS: | |
120 | size = sizeof(tss_desc); | |
121 | break; | |
122 | case DESC_LDT: | |
123 | size = sizeof(ldt_desc); | |
124 | break; | |
125 | default: | |
126 | size = sizeof(struct desc_struct); | |
127 | break; | |
128 | } | |
129 | memcpy(&gdt[entry], desc, size); | |
130 | } | |
131 | ||
54cd0eac GOC |
132 | static inline void pack_descriptor(struct desc_struct *desc, unsigned long base, |
133 | unsigned long limit, unsigned char type, | |
134 | unsigned char flags) | |
135 | { | |
136 | desc->a = ((base & 0xffff) << 16) | (limit & 0xffff); | |
137 | desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) | | |
c1773a16 JP |
138 | (limit & 0x000f0000) | ((type & 0xff) << 8) | |
139 | ((flags & 0xf) << 20); | |
54cd0eac GOC |
140 | desc->p = 1; |
141 | } | |
142 | ||
54cd0eac | 143 | |
f6e0eba1 GOC |
144 | static inline void set_tssldt_descriptor(void *d, unsigned long addr, |
145 | unsigned type, unsigned size) | |
c81c6ca4 GOC |
146 | { |
147 | #ifdef CONFIG_X86_64 | |
f6e0eba1 GOC |
148 | struct ldttss_desc64 *desc = d; |
149 | memset(desc, 0, sizeof(*desc)); | |
150 | desc->limit0 = size & 0xFFFF; | |
151 | desc->base0 = PTR_LOW(addr); | |
152 | desc->base1 = PTR_MIDDLE(addr) & 0xFF; | |
153 | desc->type = type; | |
154 | desc->p = 1; | |
155 | desc->limit1 = (size >> 16) & 0xF; | |
156 | desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF; | |
157 | desc->base3 = PTR_HIGH(addr); | |
c81c6ca4 | 158 | #else |
f6e0eba1 | 159 | pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0); |
c81c6ca4 GOC |
160 | #endif |
161 | } | |
162 | ||
163 | static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr) | |
164 | { | |
165 | struct desc_struct *d = get_cpu_gdt_table(cpu); | |
166 | tss_desc tss; | |
167 | ||
168 | /* | |
169 | * sizeof(unsigned long) coming from an extra "long" at the end | |
170 | * of the iobitmap. See tss_struct definition in processor.h | |
171 | * | |
172 | * -1? seg base+limit should be pointing to the address of the | |
173 | * last valid byte | |
174 | */ | |
f6e0eba1 | 175 | set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS, |
c1773a16 JP |
176 | IO_BITMAP_OFFSET + IO_BITMAP_BYTES + |
177 | sizeof(unsigned long) - 1); | |
c81c6ca4 GOC |
178 | write_gdt_entry(d, entry, &tss, DESC_TSS); |
179 | } | |
180 | ||
181 | #define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr) | |
182 | ||
54cd0eac GOC |
183 | static inline void native_set_ldt(const void *addr, unsigned int entries) |
184 | { | |
185 | if (likely(entries == 0)) | |
c1773a16 | 186 | asm volatile("lldt %w0"::"q" (0)); |
54cd0eac GOC |
187 | else { |
188 | unsigned cpu = smp_processor_id(); | |
189 | ldt_desc ldt; | |
190 | ||
5ac37f87 MK |
191 | set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT, |
192 | entries * LDT_ENTRY_SIZE - 1); | |
54cd0eac GOC |
193 | write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT, |
194 | &ldt, DESC_LDT); | |
c1773a16 | 195 | asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8)); |
54cd0eac GOC |
196 | } |
197 | } | |
198 | ||
199 | static inline void native_load_tr_desc(void) | |
200 | { | |
201 | asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); | |
202 | } | |
203 | ||
204 | static inline void native_load_gdt(const struct desc_ptr *dtr) | |
205 | { | |
206 | asm volatile("lgdt %0"::"m" (*dtr)); | |
207 | } | |
208 | ||
209 | static inline void native_load_idt(const struct desc_ptr *dtr) | |
210 | { | |
211 | asm volatile("lidt %0"::"m" (*dtr)); | |
212 | } | |
213 | ||
214 | static inline void native_store_gdt(struct desc_ptr *dtr) | |
215 | { | |
216 | asm volatile("sgdt %0":"=m" (*dtr)); | |
217 | } | |
218 | ||
219 | static inline void native_store_idt(struct desc_ptr *dtr) | |
220 | { | |
221 | asm volatile("sidt %0":"=m" (*dtr)); | |
222 | } | |
223 | ||
224 | static inline unsigned long native_store_tr(void) | |
225 | { | |
226 | unsigned long tr; | |
227 | asm volatile("str %0":"=r" (tr)); | |
228 | return tr; | |
229 | } | |
230 | ||
231 | static inline void native_load_tls(struct thread_struct *t, unsigned int cpu) | |
232 | { | |
233 | unsigned int i; | |
234 | struct desc_struct *gdt = get_cpu_gdt_table(cpu); | |
235 | ||
236 | for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++) | |
237 | gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]; | |
238 | } | |
239 | ||
c1773a16 JP |
240 | #define _LDT_empty(info) \ |
241 | ((info)->base_addr == 0 && \ | |
242 | (info)->limit == 0 && \ | |
243 | (info)->contents == 0 && \ | |
244 | (info)->read_exec_only == 1 && \ | |
245 | (info)->seg_32bit == 0 && \ | |
246 | (info)->limit_in_pages == 0 && \ | |
247 | (info)->seg_not_present == 1 && \ | |
248 | (info)->useable == 0) | |
881c2975 GOC |
249 | |
250 | #ifdef CONFIG_X86_64 | |
251 | #define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0)) | |
252 | #else | |
253 | #define LDT_empty(info) (_LDT_empty(info)) | |
254 | #endif | |
255 | ||
256 | static inline void clear_LDT(void) | |
257 | { | |
258 | set_ldt(NULL, 0); | |
259 | } | |
260 | ||
261 | /* | |
262 | * load one particular LDT into the current CPU | |
263 | */ | |
264 | static inline void load_LDT_nolock(mm_context_t *pc) | |
265 | { | |
266 | set_ldt(pc->ldt, pc->size); | |
267 | } | |
268 | ||
269 | static inline void load_LDT(mm_context_t *pc) | |
270 | { | |
271 | preempt_disable(); | |
272 | load_LDT_nolock(pc); | |
273 | preempt_enable(); | |
274 | } | |
275 | ||
1bd5718c | 276 | static inline unsigned long get_desc_base(const struct desc_struct *desc) |
cc697852 GOC |
277 | { |
278 | return desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24); | |
279 | } | |
1bd5718c RM |
280 | |
281 | static inline unsigned long get_desc_limit(const struct desc_struct *desc) | |
282 | { | |
283 | return desc->limit0 | (desc->limit << 16); | |
284 | } | |
285 | ||
507f90c9 | 286 | static inline void _set_gate(int gate, unsigned type, void *addr, |
c1773a16 | 287 | unsigned dpl, unsigned ist, unsigned seg) |
507f90c9 GOC |
288 | { |
289 | gate_desc s; | |
290 | pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg); | |
291 | /* | |
292 | * does not need to be atomic because it is only done once at | |
293 | * setup time | |
294 | */ | |
295 | write_idt_entry(idt_table, gate, &s); | |
296 | } | |
297 | ||
298 | /* | |
299 | * This needs to use 'idt_table' rather than 'idt', and | |
300 | * thus use the _nonmapped_ version of the IDT, as the | |
301 | * Pentium F0 0F bugfix can have resulted in the mapped | |
302 | * IDT being write-protected. | |
303 | */ | |
304 | static inline void set_intr_gate(unsigned int n, void *addr) | |
305 | { | |
306 | BUG_ON((unsigned)n > 0xFF); | |
307 | _set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS); | |
308 | } | |
309 | ||
305b92a2 AM |
310 | #define SYS_VECTOR_FREE 0 |
311 | #define SYS_VECTOR_ALLOCED 1 | |
312 | ||
313 | extern int first_system_vector; | |
314 | extern char system_vectors[]; | |
315 | ||
316 | static inline void alloc_system_vector(int vector) | |
317 | { | |
318 | if (system_vectors[vector] == SYS_VECTOR_FREE) { | |
319 | system_vectors[vector] = SYS_VECTOR_ALLOCED; | |
320 | if (first_system_vector > vector) | |
321 | first_system_vector = vector; | |
322 | } else | |
323 | BUG(); | |
324 | } | |
325 | ||
326 | static inline void alloc_intr_gate(unsigned int n, void *addr) | |
327 | { | |
328 | alloc_system_vector(n); | |
329 | set_intr_gate(n, addr); | |
330 | } | |
331 | ||
507f90c9 GOC |
332 | /* |
333 | * This routine sets up an interrupt gate at directory privilege level 3. | |
334 | */ | |
335 | static inline void set_system_intr_gate(unsigned int n, void *addr) | |
336 | { | |
337 | BUG_ON((unsigned)n > 0xFF); | |
338 | _set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS); | |
339 | } | |
340 | ||
341 | static inline void set_trap_gate(unsigned int n, void *addr) | |
342 | { | |
343 | BUG_ON((unsigned)n > 0xFF); | |
344 | _set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS); | |
345 | } | |
346 | ||
347 | static inline void set_system_gate(unsigned int n, void *addr) | |
348 | { | |
349 | BUG_ON((unsigned)n > 0xFF); | |
350 | #ifdef CONFIG_X86_32 | |
351 | _set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS); | |
352 | #else | |
353 | _set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS); | |
354 | #endif | |
355 | } | |
356 | ||
357 | static inline void set_task_gate(unsigned int n, unsigned int gdt_entry) | |
358 | { | |
359 | BUG_ON((unsigned)n > 0xFF); | |
360 | _set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3)); | |
361 | } | |
362 | ||
363 | static inline void set_intr_gate_ist(int n, void *addr, unsigned ist) | |
364 | { | |
365 | BUG_ON((unsigned)n > 0xFF); | |
366 | _set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS); | |
367 | } | |
368 | ||
369 | static inline void set_system_gate_ist(int n, void *addr, unsigned ist) | |
370 | { | |
371 | BUG_ON((unsigned)n > 0xFF); | |
372 | _set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS); | |
373 | } | |
cc697852 | 374 | |
881c2975 GOC |
375 | #else |
376 | /* | |
377 | * GET_DESC_BASE reads the descriptor base of the specified segment. | |
378 | * | |
379 | * Args: | |
380 | * idx - descriptor index | |
381 | * gdt - GDT pointer | |
382 | * base - 32bit register to which the base will be written | |
383 | * lo_w - lo word of the "base" register | |
384 | * lo_b - lo byte of the "base" register | |
385 | * hi_b - hi byte of the low word of the "base" register | |
386 | * | |
387 | * Example: | |
388 | * GET_DESC_BASE(GDT_ENTRY_ESPFIX_SS, %ebx, %eax, %ax, %al, %ah) | |
389 | * Will read the base address of GDT_ENTRY_ESPFIX_SS and put it into %eax. | |
390 | */ | |
391 | #define GET_DESC_BASE(idx, gdt, base, lo_w, lo_b, hi_b) \ | |
c1773a16 JP |
392 | movb idx * 8 + 4(gdt), lo_b; \ |
393 | movb idx * 8 + 7(gdt), hi_b; \ | |
394 | shll $16, base; \ | |
395 | movw idx * 8 + 2(gdt), lo_w; | |
881c2975 GOC |
396 | |
397 | ||
398 | #endif /* __ASSEMBLY__ */ | |
399 | ||
80fbb69a | 400 | #endif |