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77ef50a5 VN |
1 | #ifndef ASM_X86__APIC_H |
2 | #define ASM_X86__APIC_H | |
67c5fc5c TG |
3 | |
4 | #include <linux/pm.h> | |
5 | #include <linux/delay.h> | |
593f4a78 MR |
6 | |
7 | #include <asm/alternative.h> | |
67c5fc5c TG |
8 | #include <asm/fixmap.h> |
9 | #include <asm/apicdef.h> | |
10 | #include <asm/processor.h> | |
11 | #include <asm/system.h> | |
13c88fb5 SS |
12 | #include <asm/cpufeature.h> |
13 | #include <asm/msr.h> | |
67c5fc5c TG |
14 | |
15 | #define ARCH_APICTIMER_STOPS_ON_C3 1 | |
16 | ||
67c5fc5c TG |
17 | /* |
18 | * Debugging macros | |
19 | */ | |
20 | #define APIC_QUIET 0 | |
21 | #define APIC_VERBOSE 1 | |
22 | #define APIC_DEBUG 2 | |
23 | ||
24 | /* | |
25 | * Define the default level of output to be very little | |
26 | * This can be turned up by using apic=verbose for more | |
27 | * information and apic=debug for _lots_ of information. | |
28 | * apic_verbosity is defined in apic.c | |
29 | */ | |
30 | #define apic_printk(v, s, a...) do { \ | |
31 | if ((v) <= apic_verbosity) \ | |
32 | printk(s, ##a); \ | |
33 | } while (0) | |
34 | ||
35 | ||
36 | extern void generic_apic_probe(void); | |
37 | ||
38 | #ifdef CONFIG_X86_LOCAL_APIC | |
39 | ||
baa13188 | 40 | extern unsigned int apic_verbosity; |
67c5fc5c | 41 | extern int local_apic_timer_c2_ok; |
67c5fc5c | 42 | |
67c5fc5c | 43 | extern int ioapic_force; |
67c5fc5c | 44 | |
3c999f14 | 45 | extern int disable_apic; |
67c5fc5c TG |
46 | /* |
47 | * Basic functions accessing APICs. | |
48 | */ | |
49 | #ifdef CONFIG_PARAVIRT | |
50 | #include <asm/paravirt.h> | |
96a388de | 51 | #else |
67c5fc5c TG |
52 | #define setup_boot_clock setup_boot_APIC_clock |
53 | #define setup_secondary_clock setup_secondary_APIC_clock | |
96a388de | 54 | #endif |
67c5fc5c | 55 | |
aa7d8e25 | 56 | extern int is_vsmp_box(void); |
2b97df06 JS |
57 | extern void xapic_wait_icr_idle(void); |
58 | extern u32 safe_xapic_wait_icr_idle(void); | |
59 | extern u64 xapic_icr_read(void); | |
60 | extern void xapic_icr_write(u32, u32); | |
61 | extern int setup_profiling_timer(unsigned int); | |
aa7d8e25 | 62 | |
1b374e4d | 63 | static inline void native_apic_mem_write(u32 reg, u32 v) |
67c5fc5c | 64 | { |
593f4a78 | 65 | volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); |
67c5fc5c | 66 | |
593f4a78 MR |
67 | alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, |
68 | ASM_OUTPUT2("=r" (v), "=m" (*addr)), | |
69 | ASM_OUTPUT2("0" (v), "m" (*addr))); | |
67c5fc5c TG |
70 | } |
71 | ||
1b374e4d | 72 | static inline u32 native_apic_mem_read(u32 reg) |
67c5fc5c TG |
73 | { |
74 | return *((volatile u32 *)(APIC_BASE + reg)); | |
75 | } | |
76 | ||
13c88fb5 SS |
77 | static inline void native_apic_msr_write(u32 reg, u32 v) |
78 | { | |
79 | if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || | |
80 | reg == APIC_LVR) | |
81 | return; | |
82 | ||
83 | wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); | |
84 | } | |
85 | ||
86 | static inline u32 native_apic_msr_read(u32 reg) | |
87 | { | |
88 | u32 low, high; | |
89 | ||
90 | if (reg == APIC_DFR) | |
91 | return -1; | |
92 | ||
93 | rdmsr(APIC_BASE_MSR + (reg >> 4), low, high); | |
94 | return low; | |
95 | } | |
96 | ||
c535b6a1 | 97 | #ifndef CONFIG_X86_32 |
6e1cb38a SS |
98 | extern int x2apic, x2apic_preenabled; |
99 | extern void check_x2apic(void); | |
100 | extern void enable_x2apic(void); | |
101 | extern void enable_IR_x2apic(void); | |
102 | extern void x2apic_icr_write(u32 low, u32 id); | |
c535b6a1 | 103 | #endif |
1b374e4d SS |
104 | |
105 | struct apic_ops { | |
106 | u32 (*read)(u32 reg); | |
107 | void (*write)(u32 reg, u32 v); | |
1b374e4d SS |
108 | u64 (*icr_read)(void); |
109 | void (*icr_write)(u32 low, u32 high); | |
110 | void (*wait_icr_idle)(void); | |
111 | u32 (*safe_wait_icr_idle)(void); | |
112 | }; | |
113 | ||
114 | extern struct apic_ops *apic_ops; | |
115 | ||
116 | #define apic_read (apic_ops->read) | |
117 | #define apic_write (apic_ops->write) | |
1b374e4d SS |
118 | #define apic_icr_read (apic_ops->icr_read) |
119 | #define apic_icr_write (apic_ops->icr_write) | |
120 | #define apic_wait_icr_idle (apic_ops->wait_icr_idle) | |
121 | #define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle) | |
1b374e4d | 122 | |
67c5fc5c TG |
123 | extern int get_physical_broadcast(void); |
124 | ||
89027d35 SS |
125 | #ifdef CONFIG_X86_64 |
126 | static inline void ack_x2APIC_irq(void) | |
127 | { | |
128 | /* Docs say use 0 for future compatibility */ | |
129 | native_apic_msr_write(APIC_EOI, 0); | |
130 | } | |
131 | #endif | |
132 | ||
133 | ||
67c5fc5c TG |
134 | static inline void ack_APIC_irq(void) |
135 | { | |
136 | /* | |
0791e13f | 137 | * ack_APIC_irq() actually gets compiled as a single instruction |
67c5fc5c TG |
138 | * ... yummie. |
139 | */ | |
140 | ||
141 | /* Docs say use 0 for future compatibility */ | |
593f4a78 | 142 | apic_write(APIC_EOI, 0); |
67c5fc5c TG |
143 | } |
144 | ||
145 | extern int lapic_get_maxlvt(void); | |
146 | extern void clear_local_APIC(void); | |
147 | extern void connect_bsp_APIC(void); | |
148 | extern void disconnect_bsp_APIC(int virt_wire_setup); | |
149 | extern void disable_local_APIC(void); | |
150 | extern void lapic_shutdown(void); | |
151 | extern int verify_local_APIC(void); | |
152 | extern void cache_APIC_registers(void); | |
153 | extern void sync_Arb_IDs(void); | |
154 | extern void init_bsp_APIC(void); | |
155 | extern void setup_local_APIC(void); | |
739f33b3 | 156 | extern void end_local_APIC_setup(void); |
67c5fc5c | 157 | extern void init_apic_mappings(void); |
67c5fc5c TG |
158 | extern void setup_boot_APIC_clock(void); |
159 | extern void setup_secondary_APIC_clock(void); | |
160 | extern int APIC_init_uniprocessor(void); | |
e9427101 | 161 | extern void enable_NMI_through_LVT0(void); |
67c5fc5c TG |
162 | |
163 | /* | |
164 | * On 32bit this is mach-xxx local | |
165 | */ | |
166 | #ifdef CONFIG_X86_64 | |
8643f9d0 | 167 | extern void early_init_lapic_mapping(void); |
8fbbc4b4 AK |
168 | extern int apic_is_clustered_box(void); |
169 | #else | |
170 | static inline int apic_is_clustered_box(void) | |
171 | { | |
172 | return 0; | |
173 | } | |
67c5fc5c TG |
174 | #endif |
175 | ||
7b83dae7 RR |
176 | extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); |
177 | extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); | |
67c5fc5c | 178 | |
67c5fc5c TG |
179 | |
180 | #else /* !CONFIG_X86_LOCAL_APIC */ | |
181 | static inline void lapic_shutdown(void) { } | |
182 | #define local_apic_timer_c2_ok 1 | |
f3294a33 | 183 | static inline void init_apic_mappings(void) { } |
67c5fc5c TG |
184 | |
185 | #endif /* !CONFIG_X86_LOCAL_APIC */ | |
186 | ||
77ef50a5 | 187 | #endif /* ASM_X86__APIC_H */ |