[linux-2.6-block.git] / include / asm-sparc64 / tlb.h

#ifndef _SPARC64_TLB_H
#define _SPARC64_TLB_H

#include <linux/swap.h>
#include <linux/pagemap.h>
#include <asm/pgalloc.h>
#include <asm/tlbflush.h>
#include <asm/mmu_context.h>

#define TLB_BATCH_NR	192

/*
 * For UP we don't need to worry about TLB flush
 * and page free order so much..
 */
#ifdef CONFIG_SMP
  #define FREE_PTE_NR	506
  #define tlb_fast_mode(bp) ((bp)->pages_nr == ~0U)
#else
  #define FREE_PTE_NR	1
  #define tlb_fast_mode(bp) 1
#endif

struct mmu_gather {
	struct mm_struct *mm;
	unsigned int pages_nr;
	unsigned int need_flush;
	unsigned int fullmm;
	unsigned int tlb_nr;
	unsigned long vaddrs[TLB_BATCH_NR];
	struct page *pages[FREE_PTE_NR];
};

DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);

#ifdef CONFIG_SMP
extern void smp_flush_tlb_pending(struct mm_struct *,
				  unsigned long, unsigned long *);
#endif

extern void __flush_tlb_pending(unsigned long, unsigned long, unsigned long *);
extern void flush_tlb_pending(void);

static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
{
	struct mmu_gather *mp = &get_cpu_var(mmu_gathers);

	BUG_ON(mp->tlb_nr);

	mp->mm = mm;
	mp->pages_nr = num_online_cpus() > 1 ? 0U : ~0U;
	mp->fullmm = full_mm_flush;

	return mp;
}


static inline void tlb_flush_mmu(struct mmu_gather *mp)
{
	if (mp->need_flush) {
		free_pages_and_swap_cache(mp->pages, mp->pages_nr);
		mp->pages_nr = 0;
		mp->need_flush = 0;
	}

}

#ifdef CONFIG_SMP
extern void smp_flush_tlb_mm(struct mm_struct *mm);
#define do_flush_tlb_mm(mm) smp_flush_tlb_mm(mm)
#else
#define do_flush_tlb_mm(mm) __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT)
#endif

static inline void tlb_finish_mmu(struct mmu_gather *mp, unsigned long start, unsigned long end)
{
	tlb_flush_mmu(mp);

	if (mp->fullmm)
		mp->fullmm = 0;
	else
		flush_tlb_pending();

	/* keep the page table cache within bounds */
	check_pgt_cache();

	put_cpu_var(mmu_gathers);
}

static inline void tlb_remove_page(struct mmu_gather *mp, struct page *page)
{
	if (tlb_fast_mode(mp)) {
		free_page_and_swap_cache(page);
		return;
	}
	mp->need_flush = 1;
	mp->pages[mp->pages_nr++] = page;
	if (mp->pages_nr >= FREE_PTE_NR)
		tlb_flush_mmu(mp);
}

#define tlb_remove_tlb_entry(mp,ptep,addr) do { } while (0)
#define pte_free_tlb(mp, ptepage) pte_free((mp)->mm, ptepage)
#define pmd_free_tlb(mp, pmdp) pmd_free((mp)->mm, pmdp)
#define pud_free_tlb(tlb,pudp) __pud_free_tlb(tlb,pudp)

#define tlb_migrate_finish(mm)	do { } while (0)
#define tlb_start_vma(tlb, vma) do { } while (0)
#define tlb_end_vma(tlb, vma)	do { } while (0)

#endif /* _SPARC64_TLB_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef _SPARC64_TLB_H
	2	#define _SPARC64_TLB_H
	3
1da177e4	4	#include <linux/swap.h>
9f462a1a	5	#include <linux/pagemap.h>
1da177e4 LT	6	#include <asm/pgalloc.h>
	7	#include <asm/tlbflush.h>
	8	#include <asm/mmu_context.h>
	9
	10	#define TLB_BATCH_NR 192
	11
	12	/*
	13	* For UP we don't need to worry about TLB flush
	14	* and page free order so much..
	15	*/
	16	#ifdef CONFIG_SMP
	17	#define FREE_PTE_NR 506
	18	#define tlb_fast_mode(bp) ((bp)->pages_nr == ~0U)
	19	#else
	20	#define FREE_PTE_NR 1
	21	#define tlb_fast_mode(bp) 1
	22	#endif
	23
	24	struct mmu_gather {
	25	struct mm_struct *mm;
	26	unsigned int pages_nr;
	27	unsigned int need_flush;
4d6ddfa9	28	unsigned int fullmm;
1da177e4	29	unsigned int tlb_nr;
1da177e4 LT	30	unsigned long vaddrs[TLB_BATCH_NR];
	31	struct page *pages[FREE_PTE_NR];
	32	};
	33
	34	DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
	35
	36	#ifdef CONFIG_SMP
	37	extern void smp_flush_tlb_pending(struct mm_struct *,
	38	unsigned long, unsigned long *);
	39	#endif
	40
	41	extern void __flush_tlb_pending(unsigned long, unsigned long, unsigned long *);
	42	extern void flush_tlb_pending(void);
	43
	44	static inline struct mmu_gather tlb_gather_mmu(struct mm_struct mm, unsigned int full_mm_flush)
	45	{
15a23ffa	46	struct mmu_gather *mp = &get_cpu_var(mmu_gathers);
1da177e4 LT	47
	48	BUG_ON(mp->tlb_nr);
	49
	50	mp->mm = mm;
	51	mp->pages_nr = num_online_cpus() > 1 ? 0U : ~0U;
4d6ddfa9	52	mp->fullmm = full_mm_flush;
1da177e4 LT	53
	54	return mp;
	55	}
	56
	57
	58	static inline void tlb_flush_mmu(struct mmu_gather *mp)
	59	{
	60	if (mp->need_flush) {
59871bcd HD	61	free_pages_and_swap_cache(mp->pages, mp->pages_nr);
59871bcd HD	62	mp->pages_nr = 0;
1da177e4	63	mp->need_flush = 0;
1da177e4 LT	64	}
	65
	66	}
	67
	68	#ifdef CONFIG_SMP
	69	extern void smp_flush_tlb_mm(struct mm_struct *mm);
	70	#define do_flush_tlb_mm(mm) smp_flush_tlb_mm(mm)
	71	#else
	72	#define do_flush_tlb_mm(mm) __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT)
	73	#endif
	74
	75	static inline void tlb_finish_mmu(struct mmu_gather *mp, unsigned long start, unsigned long end)
	76	{
1da177e4 LT	77	tlb_flush_mmu(mp);
1da177e4 LT	78
62dbec78	79	if (mp->fullmm)
4d6ddfa9	80	mp->fullmm = 0;
62dbec78	81	else
1da177e4 LT	82	flush_tlb_pending();
	83
	84	/* keep the page table cache within bounds */
	85	check_pgt_cache();
15a23ffa HD	86
15a23ffa HD	87	put_cpu_var(mmu_gathers);
1da177e4 LT	88	}
1da177e4 LT	89
1da177e4 LT	90	static inline void tlb_remove_page(struct mmu_gather mp, struct page page)
1da177e4 LT	91	{
1da177e4 LT	92	if (tlb_fast_mode(mp)) {
	93	free_page_and_swap_cache(page);
	94	return;
	95	}
59871bcd	96	mp->need_flush = 1;
1da177e4 LT	97	mp->pages[mp->pages_nr++] = page;
	98	if (mp->pages_nr >= FREE_PTE_NR)
	99	tlb_flush_mmu(mp);
	100	}
	101
	102	#define tlb_remove_tlb_entry(mp,ptep,addr) do { } while (0)
5e541973 BH	103	#define pte_free_tlb(mp, ptepage) pte_free((mp)->mm, ptepage)
5e541973 BH	104	#define pmd_free_tlb(mp, pmdp) pmd_free((mp)->mm, pmdp)
1da177e4 LT	105	#define pud_free_tlb(tlb,pudp) __pud_free_tlb(tlb,pudp)
	106
	107	#define tlb_migrate_finish(mm) do { } while (0)
	108	#define tlb_start_vma(tlb, vma) do { } while (0)
	109	#define tlb_end_vma(tlb, vma) do { } while (0)
	110
	111	#endif /* _SPARC64_TLB_H */