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1da177e4 LT |
1 | /* $Id: system.h,v 1.69 2002/02/09 19:49:31 davem Exp $ */ |
2 | #ifndef __SPARC64_SYSTEM_H | |
3 | #define __SPARC64_SYSTEM_H | |
4 | ||
1da177e4 LT |
5 | #include <asm/ptrace.h> |
6 | #include <asm/processor.h> | |
7 | #include <asm/visasm.h> | |
8 | ||
9 | #ifndef __ASSEMBLY__ | |
10 | /* | |
11 | * Sparc (general) CPU types | |
12 | */ | |
13 | enum sparc_cpu { | |
14 | sun4 = 0x00, | |
15 | sun4c = 0x01, | |
16 | sun4m = 0x02, | |
17 | sun4d = 0x03, | |
18 | sun4e = 0x04, | |
19 | sun4u = 0x05, /* V8 ploos ploos */ | |
20 | sun_unknown = 0x06, | |
21 | ap1000 = 0x07, /* almost a sun4m */ | |
22 | }; | |
23 | ||
24 | #define sparc_cpu_model sun4u | |
25 | ||
26 | /* This cannot ever be a sun4c nor sun4 :) That's just history. */ | |
27 | #define ARCH_SUN4C_SUN4 0 | |
28 | #define ARCH_SUN4 0 | |
29 | ||
4d803fcd DM |
30 | /* These are here in an effort to more fully work around Spitfire Errata |
31 | * #51. Essentially, if a memory barrier occurs soon after a mispredicted | |
32 | * branch, the chip can stop executing instructions until a trap occurs. | |
33 | * Therefore, if interrupts are disabled, the chip can hang forever. | |
34 | * | |
35 | * It used to be believed that the memory barrier had to be right in the | |
36 | * delay slot, but a case has been traced recently wherein the memory barrier | |
37 | * was one instruction after the branch delay slot and the chip still hung. | |
38 | * The offending sequence was the following in sym_wakeup_done() of the | |
39 | * sym53c8xx_2 driver: | |
40 | * | |
41 | * call sym_ccb_from_dsa, 0 | |
42 | * movge %icc, 0, %l0 | |
43 | * brz,pn %o0, .LL1303 | |
44 | * mov %o0, %l2 | |
45 | * membar #LoadLoad | |
46 | * | |
47 | * The branch has to be mispredicted for the bug to occur. Therefore, we put | |
48 | * the memory barrier explicitly into a "branch always, predicted taken" | |
49 | * delay slot to avoid the problem case. | |
50 | */ | |
51 | #define membar_safe(type) \ | |
52 | do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \ | |
53 | " membar " type "\n" \ | |
54 | "1:\n" \ | |
55 | : : : "memory"); \ | |
56 | } while (0) | |
57 | ||
58 | #define mb() \ | |
59 | membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad") | |
60 | #define rmb() \ | |
61 | membar_safe("#LoadLoad") | |
62 | #define wmb() \ | |
63 | membar_safe("#StoreStore") | |
64 | #define membar_storeload() \ | |
65 | membar_safe("#StoreLoad") | |
66 | #define membar_storeload_storestore() \ | |
67 | membar_safe("#StoreLoad | #StoreStore") | |
68 | #define membar_storeload_loadload() \ | |
69 | membar_safe("#StoreLoad | #LoadLoad") | |
70 | #define membar_storestore_loadstore() \ | |
71 | membar_safe("#StoreStore | #LoadStore") | |
4f07118f | 72 | |
1da177e4 LT |
73 | #endif |
74 | ||
75 | #define setipl(__new_ipl) \ | |
76 | __asm__ __volatile__("wrpr %0, %%pil" : : "r" (__new_ipl) : "memory") | |
77 | ||
78 | #define local_irq_disable() \ | |
79 | __asm__ __volatile__("wrpr 15, %%pil" : : : "memory") | |
80 | ||
81 | #define local_irq_enable() \ | |
82 | __asm__ __volatile__("wrpr 0, %%pil" : : : "memory") | |
83 | ||
84 | #define getipl() \ | |
85 | ({ unsigned long retval; __asm__ __volatile__("rdpr %%pil, %0" : "=r" (retval)); retval; }) | |
86 | ||
87 | #define swap_pil(__new_pil) \ | |
88 | ({ unsigned long retval; \ | |
89 | __asm__ __volatile__("rdpr %%pil, %0\n\t" \ | |
90 | "wrpr %1, %%pil" \ | |
91 | : "=&r" (retval) \ | |
92 | : "r" (__new_pil) \ | |
93 | : "memory"); \ | |
94 | retval; \ | |
95 | }) | |
96 | ||
97 | #define read_pil_and_cli() \ | |
98 | ({ unsigned long retval; \ | |
99 | __asm__ __volatile__("rdpr %%pil, %0\n\t" \ | |
100 | "wrpr 15, %%pil" \ | |
101 | : "=r" (retval) \ | |
102 | : : "memory"); \ | |
103 | retval; \ | |
104 | }) | |
105 | ||
106 | #define local_save_flags(flags) ((flags) = getipl()) | |
107 | #define local_irq_save(flags) ((flags) = read_pil_and_cli()) | |
108 | #define local_irq_restore(flags) setipl((flags)) | |
109 | ||
110 | /* On sparc64 IRQ flags are the PIL register. A value of zero | |
111 | * means all interrupt levels are enabled, any other value means | |
112 | * only IRQ levels greater than that value will be received. | |
113 | * Consequently this means that the lowest IRQ level is one. | |
114 | */ | |
115 | #define irqs_disabled() \ | |
116 | ({ unsigned long flags; \ | |
117 | local_save_flags(flags);\ | |
118 | (flags > 0); \ | |
119 | }) | |
120 | ||
121 | #define nop() __asm__ __volatile__ ("nop") | |
122 | ||
1da177e4 LT |
123 | #define read_barrier_depends() do { } while(0) |
124 | #define set_mb(__var, __value) \ | |
4f07118f | 125 | do { __var = __value; membar_storeload_storestore(); } while(0) |
1da177e4 LT |
126 | |
127 | #ifdef CONFIG_SMP | |
128 | #define smp_mb() mb() | |
129 | #define smp_rmb() rmb() | |
130 | #define smp_wmb() wmb() | |
131 | #define smp_read_barrier_depends() read_barrier_depends() | |
132 | #else | |
133 | #define smp_mb() __asm__ __volatile__("":::"memory") | |
134 | #define smp_rmb() __asm__ __volatile__("":::"memory") | |
135 | #define smp_wmb() __asm__ __volatile__("":::"memory") | |
136 | #define smp_read_barrier_depends() do { } while(0) | |
137 | #endif | |
138 | ||
139 | #define flushi(addr) __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory") | |
140 | ||
141 | #define flushw_all() __asm__ __volatile__("flushw") | |
142 | ||
143 | /* Performance counter register access. */ | |
144 | #define read_pcr(__p) __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p)) | |
145 | #define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p)) | |
146 | #define read_pic(__p) __asm__ __volatile__("rd %%pic, %0" : "=r" (__p)) | |
147 | ||
148 | /* Blackbird errata workaround. See commentary in | |
149 | * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt() | |
150 | * for more information. | |
151 | */ | |
152 | #define reset_pic() \ | |
153 | __asm__ __volatile__("ba,pt %xcc, 99f\n\t" \ | |
154 | ".align 64\n" \ | |
155 | "99:wr %g0, 0x0, %pic\n\t" \ | |
156 | "rd %pic, %g0") | |
157 | ||
158 | #ifndef __ASSEMBLY__ | |
159 | ||
160 | extern void sun_do_break(void); | |
161 | extern int serial_console; | |
162 | extern int stop_a_enabled; | |
163 | ||
164 | static __inline__ int con_is_present(void) | |
165 | { | |
166 | return serial_console ? 0 : 1; | |
167 | } | |
168 | ||
169 | extern void synchronize_user_stack(void); | |
170 | ||
171 | extern void __flushw_user(void); | |
172 | #define flushw_user() __flushw_user() | |
173 | ||
174 | #define flush_user_windows flushw_user | |
175 | #define flush_register_windows flushw_all | |
176 | ||
4866cde0 NP |
177 | /* Don't hold the runqueue lock over context switch */ |
178 | #define __ARCH_WANT_UNLOCKED_CTXSW | |
179 | #define prepare_arch_switch(next) \ | |
180 | do { \ | |
1da177e4 LT |
181 | flushw_all(); \ |
182 | } while (0) | |
183 | ||
1da177e4 LT |
184 | /* See what happens when you design the chip correctly? |
185 | * | |
186 | * We tell gcc we clobber all non-fixed-usage registers except | |
187 | * for l0/l1. It will use one for 'next' and the other to hold | |
188 | * the output value of 'last'. 'next' is not referenced again | |
189 | * past the invocation of switch_to in the scheduler, so we need | |
190 | * not preserve it's value. Hairy, but it lets us remove 2 loads | |
191 | * and 2 stores in this critical code path. -DaveM | |
192 | */ | |
1da177e4 | 193 | #define EXTRA_CLOBBER ,"%l1" |
1da177e4 LT |
194 | #define switch_to(prev, next, last) \ |
195 | do { if (test_thread_flag(TIF_PERFCTR)) { \ | |
196 | unsigned long __tmp; \ | |
197 | read_pcr(__tmp); \ | |
198 | current_thread_info()->pcr_reg = __tmp; \ | |
199 | read_pic(__tmp); \ | |
200 | current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\ | |
201 | current_thread_info()->kernel_cntd1 += ((__tmp) >> 32); \ | |
202 | } \ | |
203 | flush_tlb_pending(); \ | |
204 | save_and_clear_fpu(); \ | |
205 | /* If you are tempted to conditionalize the following */ \ | |
206 | /* so that ASI is only written if it changes, think again. */ \ | |
207 | __asm__ __volatile__("wr %%g0, %0, %%asi" \ | |
f3169641 | 208 | : : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\ |
56fb4df6 DM |
209 | trap_block[current_thread_info()->cpu].thread = \ |
210 | task_thread_info(next); \ | |
1da177e4 LT |
211 | __asm__ __volatile__( \ |
212 | "mov %%g4, %%g7\n\t" \ | |
1da177e4 LT |
213 | "stx %%i6, [%%sp + 2047 + 0x70]\n\t" \ |
214 | "stx %%i7, [%%sp + 2047 + 0x78]\n\t" \ | |
215 | "rdpr %%wstate, %%o5\n\t" \ | |
216 | "stx %%o6, [%%g6 + %3]\n\t" \ | |
217 | "stb %%o5, [%%g6 + %2]\n\t" \ | |
218 | "rdpr %%cwp, %%o5\n\t" \ | |
219 | "stb %%o5, [%%g6 + %5]\n\t" \ | |
220 | "mov %1, %%g6\n\t" \ | |
221 | "ldub [%1 + %5], %%g1\n\t" \ | |
222 | "wrpr %%g1, %%cwp\n\t" \ | |
223 | "ldx [%%g6 + %3], %%o6\n\t" \ | |
224 | "ldub [%%g6 + %2], %%o5\n\t" \ | |
db7d9a4e | 225 | "ldub [%%g6 + %4], %%o7\n\t" \ |
1da177e4 LT |
226 | "wrpr %%o5, 0x0, %%wstate\n\t" \ |
227 | "ldx [%%sp + 2047 + 0x70], %%i6\n\t" \ | |
228 | "ldx [%%sp + 2047 + 0x78], %%i7\n\t" \ | |
db7d9a4e | 229 | "ldx [%%g6 + %6], %%g4\n\t" \ |
db7d9a4e | 230 | "brz,pt %%o7, 1f\n\t" \ |
1da177e4 LT |
231 | " mov %%g7, %0\n\t" \ |
232 | "b,a ret_from_syscall\n\t" \ | |
233 | "1:\n\t" \ | |
234 | : "=&r" (last) \ | |
f3169641 | 235 | : "0" (task_thread_info(next)), \ |
db7d9a4e DM |
236 | "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \ |
237 | "i" (TI_CWP), "i" (TI_TASK) \ | |
1da177e4 LT |
238 | : "cc", \ |
239 | "g1", "g2", "g3", "g7", \ | |
240 | "l2", "l3", "l4", "l5", "l6", "l7", \ | |
241 | "i0", "i1", "i2", "i3", "i4", "i5", \ | |
242 | "o0", "o1", "o2", "o3", "o4", "o5", "o7" EXTRA_CLOBBER);\ | |
243 | /* If you fuck with this, update ret_from_syscall code too. */ \ | |
244 | if (test_thread_flag(TIF_PERFCTR)) { \ | |
245 | write_pcr(current_thread_info()->pcr_reg); \ | |
246 | reset_pic(); \ | |
247 | } \ | |
248 | } while(0) | |
249 | ||
4dc7a0bb IM |
250 | /* |
251 | * On SMP systems, when the scheduler does migration-cost autodetection, | |
252 | * it needs a way to flush as much of the CPU's caches as possible. | |
253 | * | |
254 | * TODO: fill this in! | |
255 | */ | |
256 | static inline void sched_cacheflush(void) | |
257 | { | |
258 | } | |
259 | ||
1da177e4 LT |
260 | static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val) |
261 | { | |
262 | unsigned long tmp1, tmp2; | |
263 | ||
264 | __asm__ __volatile__( | |
265 | " membar #StoreLoad | #LoadLoad\n" | |
266 | " mov %0, %1\n" | |
267 | "1: lduw [%4], %2\n" | |
268 | " cas [%4], %2, %0\n" | |
269 | " cmp %2, %0\n" | |
270 | " bne,a,pn %%icc, 1b\n" | |
271 | " mov %1, %0\n" | |
272 | " membar #StoreLoad | #StoreStore\n" | |
273 | : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2) | |
274 | : "0" (val), "r" (m) | |
275 | : "cc", "memory"); | |
276 | return val; | |
277 | } | |
278 | ||
279 | static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val) | |
280 | { | |
281 | unsigned long tmp1, tmp2; | |
282 | ||
283 | __asm__ __volatile__( | |
284 | " membar #StoreLoad | #LoadLoad\n" | |
285 | " mov %0, %1\n" | |
286 | "1: ldx [%4], %2\n" | |
287 | " casx [%4], %2, %0\n" | |
288 | " cmp %2, %0\n" | |
289 | " bne,a,pn %%xcc, 1b\n" | |
290 | " mov %1, %0\n" | |
291 | " membar #StoreLoad | #StoreStore\n" | |
292 | : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2) | |
293 | : "0" (val), "r" (m) | |
294 | : "cc", "memory"); | |
295 | return val; | |
296 | } | |
297 | ||
298 | #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) | |
299 | #define tas(ptr) (xchg((ptr),1)) | |
300 | ||
301 | extern void __xchg_called_with_bad_pointer(void); | |
302 | ||
303 | static __inline__ unsigned long __xchg(unsigned long x, __volatile__ void * ptr, | |
304 | int size) | |
305 | { | |
306 | switch (size) { | |
307 | case 4: | |
308 | return xchg32(ptr, x); | |
309 | case 8: | |
310 | return xchg64(ptr, x); | |
311 | }; | |
312 | __xchg_called_with_bad_pointer(); | |
313 | return x; | |
314 | } | |
315 | ||
316 | extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn)); | |
317 | ||
318 | /* | |
319 | * Atomic compare and exchange. Compare OLD with MEM, if identical, | |
320 | * store NEW in MEM. Return the initial value in MEM. Success is | |
321 | * indicated by comparing RETURN with OLD. | |
322 | */ | |
323 | ||
324 | #define __HAVE_ARCH_CMPXCHG 1 | |
325 | ||
326 | static __inline__ unsigned long | |
327 | __cmpxchg_u32(volatile int *m, int old, int new) | |
328 | { | |
329 | __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n" | |
330 | "cas [%2], %3, %0\n\t" | |
331 | "membar #StoreLoad | #StoreStore" | |
332 | : "=&r" (new) | |
333 | : "0" (new), "r" (m), "r" (old) | |
334 | : "memory"); | |
335 | ||
336 | return new; | |
337 | } | |
338 | ||
339 | static __inline__ unsigned long | |
340 | __cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new) | |
341 | { | |
342 | __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n" | |
343 | "casx [%2], %3, %0\n\t" | |
344 | "membar #StoreLoad | #StoreStore" | |
345 | : "=&r" (new) | |
346 | : "0" (new), "r" (m), "r" (old) | |
347 | : "memory"); | |
348 | ||
349 | return new; | |
350 | } | |
351 | ||
352 | /* This function doesn't exist, so you'll get a linker error | |
353 | if something tries to do an invalid cmpxchg(). */ | |
354 | extern void __cmpxchg_called_with_bad_pointer(void); | |
355 | ||
356 | static __inline__ unsigned long | |
357 | __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) | |
358 | { | |
359 | switch (size) { | |
360 | case 4: | |
361 | return __cmpxchg_u32(ptr, old, new); | |
362 | case 8: | |
363 | return __cmpxchg_u64(ptr, old, new); | |
364 | } | |
365 | __cmpxchg_called_with_bad_pointer(); | |
366 | return old; | |
367 | } | |
368 | ||
369 | #define cmpxchg(ptr,o,n) \ | |
370 | ({ \ | |
371 | __typeof__(*(ptr)) _o_ = (o); \ | |
372 | __typeof__(*(ptr)) _n_ = (n); \ | |
373 | (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ | |
374 | (unsigned long)_n_, sizeof(*(ptr))); \ | |
375 | }) | |
376 | ||
377 | #endif /* !(__ASSEMBLY__) */ | |
378 | ||
379 | #define arch_align_stack(x) (x) | |
380 | ||
381 | #endif /* !(__SPARC64_SYSTEM_H) */ |