[linux-2.6-block.git] / include / asm-sparc64 / mmu.h

#ifndef __MMU_H
#define __MMU_H

#include <linux/const.h>
#include <asm/page.h>
#include <asm/hypervisor.h>

#define CTX_NR_BITS		13

#define TAG_CONTEXT_BITS	((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))

/* UltraSPARC-III+ and later have a feature whereby you can
 * select what page size the various Data-TLB instances in the
 * chip.  In order to gracefully support this, we put the version
 * field in a spot outside of the areas of the context register
 * where this parameter is specified.
 */
#define CTX_VERSION_SHIFT	22
#define CTX_VERSION_MASK	((~0UL) << CTX_VERSION_SHIFT)

#define CTX_PGSZ_8KB		_AC(0x0,UL)
#define CTX_PGSZ_64KB		_AC(0x1,UL)
#define CTX_PGSZ_512KB		_AC(0x2,UL)
#define CTX_PGSZ_4MB		_AC(0x3,UL)
#define CTX_PGSZ_BITS		_AC(0x7,UL)
#define CTX_PGSZ0_NUC_SHIFT	61
#define CTX_PGSZ1_NUC_SHIFT	58
#define CTX_PGSZ0_SHIFT		16
#define CTX_PGSZ1_SHIFT		19
#define CTX_PGSZ_MASK		((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) | \
				 (CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT))

#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
#define CTX_PGSZ_BASE	CTX_PGSZ_8KB
#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
#define CTX_PGSZ_BASE	CTX_PGSZ_64KB
#elif defined(CONFIG_SPARC64_PAGE_SIZE_512KB)
#define CTX_PGSZ_BASE	CTX_PGSZ_512KB
#elif defined(CONFIG_SPARC64_PAGE_SIZE_4MB)
#define CTX_PGSZ_BASE	CTX_PGSZ_4MB
#else
#error No page size specified in kernel configuration
#endif

#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
#define CTX_PGSZ_HUGE		CTX_PGSZ_4MB
#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
#define CTX_PGSZ_HUGE		CTX_PGSZ_512KB
#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
#define CTX_PGSZ_HUGE		CTX_PGSZ_64KB
#endif

#define CTX_PGSZ_KERN	CTX_PGSZ_4MB

/* Thus, when running on UltraSPARC-III+ and later, we use the following
 * PRIMARY_CONTEXT register values for the kernel context.
 */
#define CTX_CHEETAH_PLUS_NUC \
	((CTX_PGSZ_KERN << CTX_PGSZ0_NUC_SHIFT) | \
	 (CTX_PGSZ_BASE << CTX_PGSZ1_NUC_SHIFT))

#define CTX_CHEETAH_PLUS_CTX0 \
	((CTX_PGSZ_KERN << CTX_PGSZ0_SHIFT) | \
	 (CTX_PGSZ_BASE << CTX_PGSZ1_SHIFT))

/* If you want "the TLB context number" use CTX_NR_MASK.  If you
 * want "the bits I program into the context registers" use
 * CTX_HW_MASK.
 */
#define CTX_NR_MASK		TAG_CONTEXT_BITS
#define CTX_HW_MASK		(CTX_NR_MASK | CTX_PGSZ_MASK)

#define CTX_FIRST_VERSION	((_AC(1,UL) << CTX_VERSION_SHIFT) + _AC(1,UL))
#define CTX_VALID(__ctx)	\
	 (!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK))
#define CTX_HWBITS(__ctx)	((__ctx.sparc64_ctx_val) & CTX_HW_MASK)
#define CTX_NRBITS(__ctx)	((__ctx.sparc64_ctx_val) & CTX_NR_MASK)

#ifndef __ASSEMBLY__

#define TSB_ENTRY_ALIGNMENT	16

struct tsb {
	unsigned long tag;
	unsigned long pte;
} __attribute__((aligned(TSB_ENTRY_ALIGNMENT)));

extern void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte);
extern void tsb_flush(unsigned long ent, unsigned long tag);
extern void tsb_init(struct tsb *tsb, unsigned long size);

struct tsb_config {
	struct tsb		*tsb;
	unsigned long		tsb_rss_limit;
	unsigned long		tsb_nentries;
	unsigned long		tsb_reg_val;
	unsigned long		tsb_map_vaddr;
	unsigned long		tsb_map_pte;
};

#define MM_TSB_BASE	0

#ifdef CONFIG_HUGETLB_PAGE
#define MM_TSB_HUGE	1
#define MM_NUM_TSBS	2
#else
#define MM_NUM_TSBS	1
#endif

typedef struct {
	spinlock_t		lock;
	unsigned long		sparc64_ctx_val;
	unsigned long		huge_pte_count;
	struct tsb_config	tsb_block[MM_NUM_TSBS];
	struct hv_tsb_descr	tsb_descr[MM_NUM_TSBS];
} mm_context_t;

#endif /* !__ASSEMBLY__ */

#define TSB_CONFIG_TSB		0x00
#define TSB_CONFIG_RSS_LIMIT	0x08
#define TSB_CONFIG_NENTRIES	0x10
#define TSB_CONFIG_REG_VAL	0x18
#define TSB_CONFIG_MAP_VADDR	0x20
#define TSB_CONFIG_MAP_PTE	0x28

#endif /* __MMU_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef __MMU_H
	2	#define __MMU_H
	3
6df95fd7	4	#include <linux/const.h>
1da177e4	5	#include <asm/page.h>
618e9ed9	6	#include <asm/hypervisor.h>
1da177e4	7
97c4b6f9	8	#define CTX_NR_BITS 13
1da177e4 LT	9
	10	#define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
	11
	12	/* UltraSPARC-III+ and later have a feature whereby you can
	13	* select what page size the various Data-TLB instances in the
	14	* chip. In order to gracefully support this, we put the version
	15	* field in a spot outside of the areas of the context register
	16	* where this parameter is specified.
	17	*/
	18	#define CTX_VERSION_SHIFT 22
	19	#define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT)
	20
	21	#define CTX_PGSZ_8KB _AC(0x0,UL)
	22	#define CTX_PGSZ_64KB _AC(0x1,UL)
	23	#define CTX_PGSZ_512KB _AC(0x2,UL)
	24	#define CTX_PGSZ_4MB _AC(0x3,UL)
	25	#define CTX_PGSZ_BITS _AC(0x7,UL)
	26	#define CTX_PGSZ0_NUC_SHIFT 61
	27	#define CTX_PGSZ1_NUC_SHIFT 58
	28	#define CTX_PGSZ0_SHIFT 16
	29	#define CTX_PGSZ1_SHIFT 19
	30	#define CTX_PGSZ_MASK ((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) \| \
	31	(CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT))
	32
	33	#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
	34	#define CTX_PGSZ_BASE CTX_PGSZ_8KB
	35	#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
	36	#define CTX_PGSZ_BASE CTX_PGSZ_64KB
	37	#elif defined(CONFIG_SPARC64_PAGE_SIZE_512KB)
	38	#define CTX_PGSZ_BASE CTX_PGSZ_512KB
	39	#elif defined(CONFIG_SPARC64_PAGE_SIZE_4MB)
	40	#define CTX_PGSZ_BASE CTX_PGSZ_4MB
	41	#else
	42	#error No page size specified in kernel configuration
	43	#endif
	44
	45	#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
	46	#define CTX_PGSZ_HUGE CTX_PGSZ_4MB
	47	#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
	48	#define CTX_PGSZ_HUGE CTX_PGSZ_512KB
	49	#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
	50	#define CTX_PGSZ_HUGE CTX_PGSZ_64KB
	51	#endif
	52
	53	#define CTX_PGSZ_KERN CTX_PGSZ_4MB
	54
	55	/* Thus, when running on UltraSPARC-III+ and later, we use the following
	56	* PRIMARY_CONTEXT register values for the kernel context.
	57	*/
	58	#define CTX_CHEETAH_PLUS_NUC \
	59	((CTX_PGSZ_KERN << CTX_PGSZ0_NUC_SHIFT) \| \
	60	(CTX_PGSZ_BASE << CTX_PGSZ1_NUC_SHIFT))
	61
	62	#define CTX_CHEETAH_PLUS_CTX0 \
	63	((CTX_PGSZ_KERN << CTX_PGSZ0_SHIFT) \| \
	64	(CTX_PGSZ_BASE << CTX_PGSZ1_SHIFT))
	65
	66	/* If you want "the TLB context number" use CTX_NR_MASK. If you
	67	* want "the bits I program into the context registers" use
	68	* CTX_HW_MASK.
	69	*/
	70	#define CTX_NR_MASK TAG_CONTEXT_BITS
	71	#define CTX_HW_MASK (CTX_NR_MASK \| CTX_PGSZ_MASK)
	72
73	#define CTX_FIRST_VERSION ((_AC(1,UL) << CTX_VERSION_SHIFT) + _AC(1,UL))
74	#define CTX_VALID(__ctx) \
75	(!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK))
76	#define CTX_HWBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_HW_MASK)
77	#define CTX_NRBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_NR_MASK)
78
79	#ifndef __ASSEMBLY__
80
98c5584c DM	81	#define TSB_ENTRY_ALIGNMENT 16
	82
	83	struct tsb {
	84	unsigned long tag;
	85	unsigned long pte;
	86	} __attribute__((aligned(TSB_ENTRY_ALIGNMENT)));
	87
517af332 DM	88	extern void __tsb_insert(unsigned long ent, unsigned long tag, unsigned long pte);
517af332 DM	89	extern void tsb_flush(unsigned long ent, unsigned long tag);
bb8646d8	90	extern void tsb_init(struct tsb *tsb, unsigned long size);
b70c0fa1	91
dcc1e8dd	92	struct tsb_config {
618e9ed9 DM	93	struct tsb *tsb;
	94	unsigned long tsb_rss_limit;
	95	unsigned long tsb_nentries;
	96	unsigned long tsb_reg_val;
	97	unsigned long tsb_map_vaddr;
	98	unsigned long tsb_map_pte;
dcc1e8dd DM	99	};
	100
	101	#define MM_TSB_BASE 0
	102
	103	#ifdef CONFIG_HUGETLB_PAGE
	104	#define MM_TSB_HUGE 1
	105	#define MM_NUM_TSBS 2
	106	#else
	107	#define MM_NUM_TSBS 1
	108	#endif
	109
	110	typedef struct {
	111	spinlock_t lock;
	112	unsigned long sparc64_ctx_val;
	113	unsigned long huge_pte_count;
	114	struct tsb_config tsb_block[MM_NUM_TSBS];
	115	struct hv_tsb_descr tsb_descr[MM_NUM_TSBS];
1da177e4 LT	116	} mm_context_t;
	117
	118	#endif /* !__ASSEMBLY__ */
	119
dcc1e8dd DM	120	#define TSB_CONFIG_TSB 0x00
	121	#define TSB_CONFIG_RSS_LIMIT 0x08
	122	#define TSB_CONFIG_NENTRIES 0x10
	123	#define TSB_CONFIG_REG_VAL 0x18
	124	#define TSB_CONFIG_MAP_VADDR 0x20
	125	#define TSB_CONFIG_MAP_PTE 0x28
	126
1da177e4	127	#endif /* __MMU_H */