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1da177e4 LT |
1 | /* $Id: ide.h,v 1.21 2001/09/25 20:21:48 kanoj Exp $ |
2 | * ide.h: Ultra/PCI specific IDE glue. | |
3 | * | |
4 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
6 | */ | |
7 | ||
8 | #ifndef _SPARC64_IDE_H | |
9 | #define _SPARC64_IDE_H | |
10 | ||
11 | #ifdef __KERNEL__ | |
12 | ||
1da177e4 LT |
13 | #include <asm/pgalloc.h> |
14 | #include <asm/io.h> | |
15 | #include <asm/spitfire.h> | |
16 | #include <asm/cacheflush.h> | |
6a9b490d | 17 | #include <asm/page.h> |
1da177e4 LT |
18 | |
19 | #ifndef MAX_HWIFS | |
20 | # ifdef CONFIG_BLK_DEV_IDEPCI | |
21 | #define MAX_HWIFS 10 | |
22 | # else | |
23 | #define MAX_HWIFS 2 | |
24 | # endif | |
25 | #endif | |
26 | ||
1da177e4 LT |
27 | #define ide_default_io_ctl(base) ((base) + 0x206) /* obsolete */ |
28 | ||
29 | #define __ide_insl(data_reg, buffer, wcount) \ | |
30 | __ide_insw(data_reg, buffer, (wcount)<<1) | |
31 | #define __ide_outsl(data_reg, buffer, wcount) \ | |
32 | __ide_outsw(data_reg, buffer, (wcount)<<1) | |
33 | ||
34 | /* On sparc64, I/O ports and MMIO registers are accessed identically. */ | |
35 | #define __ide_mm_insw __ide_insw | |
36 | #define __ide_mm_insl __ide_insl | |
37 | #define __ide_mm_outsw __ide_outsw | |
38 | #define __ide_mm_outsl __ide_outsl | |
39 | ||
40 | static inline unsigned int inw_be(void __iomem *addr) | |
41 | { | |
42 | unsigned int ret; | |
43 | ||
44 | __asm__ __volatile__("lduha [%1] %2, %0" | |
45 | : "=r" (ret) | |
46 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | |
47 | ||
48 | return ret; | |
49 | } | |
50 | ||
51 | static inline void __ide_insw(void __iomem *port, void *dst, u32 count) | |
52 | { | |
53 | #ifdef DCACHE_ALIASING_POSSIBLE | |
54 | unsigned long end = (unsigned long)dst + (count << 1); | |
55 | #endif | |
56 | u16 *ps = dst; | |
57 | u32 *pi; | |
58 | ||
59 | if(((u64)ps) & 0x2) { | |
60 | *ps++ = inw_be(port); | |
61 | count--; | |
62 | } | |
63 | pi = (u32 *)ps; | |
64 | while(count >= 2) { | |
65 | u32 w; | |
66 | ||
67 | w = inw_be(port) << 16; | |
68 | w |= inw_be(port); | |
69 | *pi++ = w; | |
70 | count -= 2; | |
71 | } | |
72 | ps = (u16 *)pi; | |
73 | if(count) | |
74 | *ps++ = inw_be(port); | |
75 | ||
76 | #ifdef DCACHE_ALIASING_POSSIBLE | |
77 | __flush_dcache_range((unsigned long)dst, end); | |
78 | #endif | |
79 | } | |
80 | ||
81 | static inline void outw_be(unsigned short w, void __iomem *addr) | |
82 | { | |
83 | __asm__ __volatile__("stha %0, [%1] %2" | |
84 | : /* no outputs */ | |
85 | : "r" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | |
86 | } | |
87 | ||
88 | static inline void __ide_outsw(void __iomem *port, void *src, u32 count) | |
89 | { | |
90 | #ifdef DCACHE_ALIASING_POSSIBLE | |
91 | unsigned long end = (unsigned long)src + (count << 1); | |
92 | #endif | |
93 | const u16 *ps = src; | |
94 | const u32 *pi; | |
95 | ||
96 | if(((u64)src) & 0x2) { | |
97 | outw_be(*ps++, port); | |
98 | count--; | |
99 | } | |
100 | pi = (const u32 *)ps; | |
101 | while(count >= 2) { | |
102 | u32 w; | |
103 | ||
104 | w = *pi++; | |
105 | outw_be((w >> 16), port); | |
106 | outw_be(w, port); | |
107 | count -= 2; | |
108 | } | |
109 | ps = (const u16 *)pi; | |
110 | if(count) | |
111 | outw_be(*ps, port); | |
112 | ||
113 | #ifdef DCACHE_ALIASING_POSSIBLE | |
114 | __flush_dcache_range((unsigned long)src, end); | |
115 | #endif | |
116 | } | |
117 | ||
118 | #endif /* __KERNEL__ */ | |
119 | ||
120 | #endif /* _SPARC64_IDE_H */ |