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Merge master.kernel.org:/pub/scm/linux/kernel/git/jejb/scsi-rc-fixes-2.6
[linux-2.6-block.git] / include / asm-sparc64 / cpudata.h
CommitLineData
1da177e4
LT		 1/* cpudata.h: Per-cpu parameters.
2 *
56fb4df6 3 * Copyright (C) 2003, 2005, 2006 David S. Miller (davem@davemloft.net)
1da177e4
LT		 4 */
5
6#ifndef _SPARC64_CPUDATA_H
7#define _SPARC64_CPUDATA_H
8
d257d5da 9#include <asm/hypervisor.h>
89a5264f 10#include <asm/asi.h>
d257d5da 11
56fb4df6
DM		 12#ifndef __ASSEMBLY__
13
1da177e4 14#include <linux/percpu.h>
56fb4df6 15#include <linux/threads.h>
1da177e4
LT		 16
17typedef struct {
18 /* Dcache line 1 */
d7ce78fd 19 unsigned int __softirq_pending; /* must be 1st, see rtrap.S */
5cbc3073 20 unsigned int __pad0;
1da177e4
LT		 21 unsigned long clock_tick; /* %tick's per second */
22 unsigned long udelay_val;
5cbc3073
DM		 23 unsigned int __pad1;
24 unsigned int __pad2;
1da177e4 25
3c936465 26 /* Dcache line 2, rarely used */
80dc0d6b
DM		 27 unsigned int dcache_size;
28 unsigned int dcache_line_size;
29 unsigned int icache_size;
30 unsigned int icache_line_size;
31 unsigned int ecache_size;
32 unsigned int ecache_line_size;
5cbc3073 33 int core_id;
f78eae2e 34 int proc_id;
1da177e4
LT		 35} cpuinfo_sparc;
36
37DECLARE_PER_CPU(cpuinfo_sparc, __cpu_data);
38#define cpu_data(__cpu) per_cpu(__cpu_data, (__cpu))
39#define local_cpu_data() __get_cpu_var(__cpu_data)
40
56fb4df6
DM		 41/* Trap handling code needs to get at a few critical values upon
42 * trap entry and to process TSB misses. These cannot be in the
43 * per_cpu() area as we really need to lock them into the TLB and
44 * thus make them part of the main kernel image. As a result we
45 * try to make this as small as possible.
46 *
47 * This is padded out and aligned to 64-bytes to avoid false sharing
48 * on SMP.
49 */
50
51/* If you modify the size of this structure, please update
52 * TRAP_BLOCK_SZ_SHIFT below.
53 */
54struct thread_info;
55struct trap_per_cpu {
5b0c0572 56/* D-cache line 1: Basic thread information, cpu and device mondo queues */
56fb4df6
DM		 57 struct thread_info *thread;
58 unsigned long pgd_paddr;
7202c55c
DM		 59 unsigned long cpu_mondo_pa;
60 unsigned long dev_mondo_pa;
5b0c0572
DM		 61
62/* D-cache line 2: Error Mondo Queue and kernel buffer pointers */
7202c55c 63 unsigned long resum_mondo_pa;
5b0c0572 64 unsigned long resum_kernel_buf_pa;
7202c55c 65 unsigned long nonresum_mondo_pa;
5b0c0572 66 unsigned long nonresum_kernel_buf_pa;
d257d5da 67
1d2f1f90 68/* Dcache lines 3, 4, 5, and 6: Hypervisor Fault Status */
d257d5da 69 struct hv_fault_status fault_info;
1d2f1f90
DM		 70
71/* Dcache line 7: Physical addresses of CPU send mondo block and CPU list. */
72 unsigned long cpu_mondo_block_pa;
73 unsigned long cpu_list_pa;
dcc1e8dd
DM		 74 unsigned long tsb_huge;
75 unsigned long tsb_huge_temp;
1d2f1f90 76
fd0504c3
DM		 77/* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size. */
78 unsigned int irq_worklist;
5cbc3073
DM		 79 unsigned int cpu_mondo_qmask;
80 unsigned int dev_mondo_qmask;
81 unsigned int resum_qmask;
82 unsigned int nonresum_qmask;
83 unsigned int __pad2[3];
56fb4df6
DM		 84} __attribute__((aligned(64)));
85extern struct trap_per_cpu trap_block[NR_CPUS];
72aff53f 86extern void init_cur_cpu_trap(struct thread_info *);
a8b900d8 87extern void setup_tba(void);
5cbc3073
DM		 88extern int ncpus_probed;
89
90extern unsigned long real_hard_smp_processor_id(void);
56fb4df6 91
92704a1c
DM		 92struct cpuid_patch_entry {
93 unsigned int addr;
94 unsigned int cheetah_safari[4];
95 unsigned int cheetah_jbus[4];
96 unsigned int starfire[4];
d96b8153 97 unsigned int sun4v[4];
92704a1c
DM		 98};
99extern struct cpuid_patch_entry __cpuid_patch, __cpuid_patch_end;
92704a1c 100
df7d6aec 101struct sun4v_1insn_patch_entry {
936f482a
DM		 102 unsigned int addr;
103 unsigned int insn;
104};
df7d6aec
DM		 105extern struct sun4v_1insn_patch_entry __sun4v_1insn_patch,
106 __sun4v_1insn_patch_end;
45fec05f 107
df7d6aec 108struct sun4v_2insn_patch_entry {
45fec05f
DM		 109 unsigned int addr;
110 unsigned int insns[2];
111};
df7d6aec
DM		 112extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
113 __sun4v_2insn_patch_end;
114
56fb4df6
DM		 115#endif /* !(__ASSEMBLY__) */
116
7202c55c
DM		 117#define TRAP_PER_CPU_THREAD 0x00
118#define TRAP_PER_CPU_PGD_PADDR 0x08
5b0c0572
DM		 119#define TRAP_PER_CPU_CPU_MONDO_PA 0x10
120#define TRAP_PER_CPU_DEV_MONDO_PA 0x18
121#define TRAP_PER_CPU_RESUM_MONDO_PA 0x20
122#define TRAP_PER_CPU_RESUM_KBUF_PA 0x28
123#define TRAP_PER_CPU_NONRESUM_MONDO_PA 0x30
124#define TRAP_PER_CPU_NONRESUM_KBUF_PA 0x38
7202c55c 125#define TRAP_PER_CPU_FAULT_INFO 0x40
1d2f1f90
DM		 126#define TRAP_PER_CPU_CPU_MONDO_BLOCK_PA 0xc0
127#define TRAP_PER_CPU_CPU_LIST_PA 0xc8
dcc1e8dd
DM		 128#define TRAP_PER_CPU_TSB_HUGE 0xd0
129#define TRAP_PER_CPU_TSB_HUGE_TEMP 0xd8
fd0504c3 130#define TRAP_PER_CPU_IRQ_WORKLIST 0xe0
5cbc3073
DM		 131#define TRAP_PER_CPU_CPU_MONDO_QMASK 0xe4
132#define TRAP_PER_CPU_DEV_MONDO_QMASK 0xe8
133#define TRAP_PER_CPU_RESUM_QMASK 0xec
134#define TRAP_PER_CPU_NONRESUM_QMASK 0xf0
56fb4df6 135
1d2f1f90 136#define TRAP_BLOCK_SZ_SHIFT 8
56fb4df6 137
d96b8153
DM		 138#include <asm/scratchpad.h>
139
92704a1c
DM		 140#define __GET_CPUID(REG) \
141 /* Spitfire implementation (default). */ \
142661: ldxa [%g0] ASI_UPA_CONFIG, REG; \
143 srlx REG, 17, REG; \
144 and REG, 0x1f, REG; \
145 nop; \
146 .section .cpuid_patch, "ax"; \
147 /* Instruction location. */ \
148 .word 661b; \
149 /* Cheetah Safari implementation. */ \
150 ldxa [%g0] ASI_SAFARI_CONFIG, REG; \
151 srlx REG, 17, REG; \
152 and REG, 0x3ff, REG; \
153 nop; \
154 /* Cheetah JBUS implementation. */ \
155 ldxa [%g0] ASI_JBUS_CONFIG, REG; \
156 srlx REG, 17, REG; \
157 and REG, 0x1f, REG; \
158 nop; \
159 /* Starfire implementation. */ \
160 sethi %hi(0x1fff40000d0 >> 9), REG; \
161 sllx REG, 9, REG; \
162 or REG, 0xd0, REG; \
163 lduwa [REG] ASI_PHYS_BYPASS_EC_E, REG;\
d96b8153
DM		 164 /* sun4v implementation. */ \
165 mov SCRATCHPAD_CPUID, REG; \
d96b8153
DM		 166 ldxa [REG] ASI_SCRATCHPAD, REG; \
167 nop; \
89a5264f 168 nop; \
92704a1c 169 .previous;
56fb4df6 170
ebd8c56c
DM		 171#ifdef CONFIG_SMP
172
12eaa328 173#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
ffe483d5
DM		 174 __GET_CPUID(TMP) \
175 sethi %hi(trap_block), DEST; \
176 sllx TMP, TRAP_BLOCK_SZ_SHIFT, TMP; \
177 or DEST, %lo(trap_block), DEST; \
178 add DEST, TMP, DEST; \
12eaa328
DM		 179
180/* Clobbers TMP, current address space PGD phys address into DEST. */
181#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
182 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
ffe483d5
DM		 183 ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
184
185/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
186#define TRAP_LOAD_IRQ_WORK(DEST, TMP) \
fd0504c3
DM		 187 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
188 add DEST, TRAP_PER_CPU_IRQ_WORKLIST, DEST;
ffe483d5
DM		 189
190/* Clobbers TMP, loads DEST with current thread info pointer. */
191#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
12eaa328
DM		 192 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
193 ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
ffe483d5
DM		 194
195/* Given the current thread info pointer in THR, load the per-cpu
196 * area base of the current processor into DEST. REG1, REG2, and REG3 are
56fb4df6 197 * clobbered.
86b81868 198 *
ffe483d5 199 * You absolutely cannot use DEST as a temporary in this code. The
86b81868 200 * reason is that traps can happen during execution, and return from
ffe483d5 201 * trap will load the fully resolved DEST per-cpu base. This can corrupt
86b81868 202 * the calculations done by the macro mid-stream.
56fb4df6 203 */
ffe483d5 204#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3) \
22adb358 205 lduh [THR + TI_CPU], REG1; \
86b81868 206 sethi %hi(__per_cpu_shift), REG3; \
56fb4df6 207 sethi %hi(__per_cpu_base), REG2; \
86b81868 208 ldx [REG3 + %lo(__per_cpu_shift)], REG3; \
56fb4df6 209 ldx [REG2 + %lo(__per_cpu_base)], REG2; \
86b81868 210 sllx REG1, REG3, REG3; \
ffe483d5 211 add REG3, REG2, DEST;
92704a1c 212
56fb4df6 213#else
92704a1c 214
12eaa328
DM		 215#define TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
216 sethi %hi(trap_block), DEST; \
217 or DEST, %lo(trap_block), DEST; \
5b0c0572 218
92704a1c 219/* Uniprocessor versions, we know the cpuid is zero. */
ffe483d5 220#define TRAP_LOAD_PGD_PHYS(DEST, TMP) \
12eaa328 221 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
ffe483d5 222 ldx [DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
92704a1c 223
fd0504c3 224/* Clobbers TMP, loads local processor's IRQ work area into DEST. */
ffe483d5 225#define TRAP_LOAD_IRQ_WORK(DEST, TMP) \
fd0504c3
DM		 226 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
227 add DEST, TRAP_PER_CPU_IRQ_WORKLIST, DEST;
92704a1c 228
ffe483d5 229#define TRAP_LOAD_THREAD_REG(DEST, TMP) \
12eaa328
DM		 230 TRAP_LOAD_TRAP_BLOCK(DEST, TMP) \
231 ldx [DEST + TRAP_PER_CPU_THREAD], DEST;
92704a1c 232
ffe483d5
DM		 233/* No per-cpu areas on uniprocessor, so no need to load DEST. */
234#define LOAD_PER_CPU_BASE(DEST, THR, REG1, REG2, REG3)
92704a1c
DM		 235
236#endif /* !(CONFIG_SMP) */
56fb4df6 237
1da177e4 238#endif /* _SPARC64_CPUDATA_H */
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