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1da177e4 LT |
1 | /* $Id: dma.h,v 1.35 1999/12/27 06:37:09 anton Exp $ |
2 | * include/asm-sparc/dma.h | |
3 | * | |
4 | * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu) | |
5 | */ | |
6 | ||
7 | #ifndef _ASM_SPARC_DMA_H | |
8 | #define _ASM_SPARC_DMA_H | |
9 | ||
10 | #include <linux/config.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/types.h> | |
13 | ||
14 | #include <asm/vac-ops.h> /* for invalidate's, etc. */ | |
15 | #include <asm/sbus.h> | |
16 | #include <asm/delay.h> | |
17 | #include <asm/oplib.h> | |
18 | #include <asm/system.h> | |
19 | #include <asm/io.h> | |
20 | #include <linux/spinlock.h> | |
21 | ||
22 | struct page; | |
23 | extern spinlock_t dma_spin_lock; | |
24 | ||
25 | static __inline__ unsigned long claim_dma_lock(void) | |
26 | { | |
27 | unsigned long flags; | |
28 | spin_lock_irqsave(&dma_spin_lock, flags); | |
29 | return flags; | |
30 | } | |
31 | ||
32 | static __inline__ void release_dma_lock(unsigned long flags) | |
33 | { | |
34 | spin_unlock_irqrestore(&dma_spin_lock, flags); | |
35 | } | |
36 | ||
37 | /* These are irrelevant for Sparc DMA, but we leave it in so that | |
38 | * things can compile. | |
39 | */ | |
40 | #define MAX_DMA_CHANNELS 8 | |
41 | #define MAX_DMA_ADDRESS (~0UL) | |
42 | #define DMA_MODE_READ 1 | |
43 | #define DMA_MODE_WRITE 2 | |
44 | ||
45 | /* Useful constants */ | |
46 | #define SIZE_16MB (16*1024*1024) | |
47 | #define SIZE_64K (64*1024) | |
48 | ||
49 | /* SBUS DMA controller reg offsets */ | |
50 | #define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */ | |
51 | #define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */ | |
52 | #define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */ | |
53 | #define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */ | |
54 | ||
55 | /* DVMA chip revisions */ | |
56 | enum dvma_rev { | |
57 | dvmarev0, | |
58 | dvmaesc1, | |
59 | dvmarev1, | |
60 | dvmarev2, | |
61 | dvmarev3, | |
62 | dvmarevplus, | |
63 | dvmahme | |
64 | }; | |
65 | ||
66 | #define DMA_HASCOUNT(rev) ((rev)==dvmaesc1) | |
67 | ||
68 | /* Linux DMA information structure, filled during probe. */ | |
69 | struct sbus_dma { | |
70 | struct sbus_dma *next; | |
71 | struct sbus_dev *sdev; | |
72 | void __iomem *regs; | |
73 | ||
74 | /* Status, misc info */ | |
75 | int node; /* Prom node for this DMA device */ | |
76 | int running; /* Are we doing DMA now? */ | |
77 | int allocated; /* Are we "owned" by anyone yet? */ | |
78 | ||
79 | /* Transfer information. */ | |
80 | unsigned long addr; /* Start address of current transfer */ | |
81 | int nbytes; /* Size of current transfer */ | |
82 | int realbytes; /* For splitting up large transfers, etc. */ | |
83 | ||
84 | /* DMA revision */ | |
85 | enum dvma_rev revision; | |
86 | }; | |
87 | ||
88 | extern struct sbus_dma *dma_chain; | |
89 | ||
90 | /* Broken hardware... */ | |
91 | #ifdef CONFIG_SUN4 | |
92 | /* Have to sort this out. Does rev0 work fine on sun4[cmd] without isbroken? | |
93 | * Or is rev0 present only on sun4 boxes? -jj */ | |
94 | #define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev0 || (dma)->revision == dvmarev1) | |
95 | #else | |
96 | #define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1) | |
97 | #endif | |
98 | #define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1) | |
99 | ||
100 | /* Main routines in dma.c */ | |
101 | extern void dvma_init(struct sbus_bus *); | |
102 | ||
103 | /* Fields in the cond_reg register */ | |
104 | /* First, the version identification bits */ | |
105 | #define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */ | |
106 | #define DMA_VERS0 0x00000000 /* Sunray DMA version */ | |
107 | #define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */ | |
108 | #define DMA_VERS1 0x80000000 /* DMA rev 1 */ | |
109 | #define DMA_VERS2 0xa0000000 /* DMA rev 2 */ | |
110 | #define DMA_VERHME 0xb0000000 /* DMA hme gate array */ | |
111 | #define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */ | |
112 | ||
113 | #define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */ | |
114 | #define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */ | |
115 | #define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */ | |
116 | #define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */ | |
117 | #define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */ | |
118 | #define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */ | |
119 | #define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */ | |
120 | #define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */ | |
121 | #define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */ | |
122 | #define DMA_RST_BPP DMA_RST_SCSI /* Reset the BPP controller */ | |
123 | #define DMA_ST_WRITE 0x00000100 /* write from device to memory */ | |
124 | #define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */ | |
125 | #define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */ | |
126 | #define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */ | |
127 | #define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */ | |
128 | #define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */ | |
129 | #define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */ | |
130 | #define DMA_TERM_CNTR 0x00004000 /* Terminal counter */ | |
131 | #define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */ | |
132 | #define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */ | |
133 | #define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */ | |
134 | #define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */ | |
135 | #define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */ | |
136 | #define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */ | |
137 | #define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */ | |
138 | #define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */ | |
139 | #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */ | |
140 | #define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */ | |
141 | #define DMA_BRST32 0x00040000 /* SCSI/BPP: 32byte bursts */ | |
142 | #define DMA_BRST16 0x00000000 /* SCSI/BPP: 16byte bursts */ | |
143 | #define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */ | |
144 | #define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */ | |
145 | #define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */ | |
146 | #define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */ | |
147 | #define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */ | |
148 | #define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */ | |
149 | #define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */ | |
150 | #define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */ | |
151 | #define DMA_BPP_ON DMA_SCSI_ON /* Enable BPP dma */ | |
152 | #define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */ | |
153 | #define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */ | |
154 | #define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */ | |
155 | #define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */ | |
156 | ||
157 | /* Values describing the burst-size property from the PROM */ | |
158 | #define DMA_BURST1 0x01 | |
159 | #define DMA_BURST2 0x02 | |
160 | #define DMA_BURST4 0x04 | |
161 | #define DMA_BURST8 0x08 | |
162 | #define DMA_BURST16 0x10 | |
163 | #define DMA_BURST32 0x20 | |
164 | #define DMA_BURST64 0x40 | |
165 | #define DMA_BURSTBITS 0x7f | |
166 | ||
167 | /* Determine highest possible final transfer address given a base */ | |
168 | #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL)) | |
169 | ||
170 | /* Yes, I hack a lot of elisp in my spare time... */ | |
171 | #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR)) | |
172 | #define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))) | |
173 | #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE)) | |
174 | #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE))) | |
175 | #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB))) | |
176 | #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB))) | |
177 | #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV)) | |
178 | #define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr)) | |
179 | #define DMA_BEGINDMA_W(regs) \ | |
180 | ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB)))) | |
181 | #define DMA_BEGINDMA_R(regs) \ | |
182 | ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE))))) | |
183 | ||
184 | /* For certain DMA chips, we need to disable ints upon irq entry | |
185 | * and turn them back on when we are done. So in any ESP interrupt | |
186 | * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT | |
187 | * when leaving the handler. You have been warned... | |
188 | */ | |
189 | #define DMA_IRQ_ENTRY(dma, dregs) do { \ | |
190 | if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \ | |
191 | } while (0) | |
192 | ||
193 | #define DMA_IRQ_EXIT(dma, dregs) do { \ | |
194 | if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \ | |
195 | } while(0) | |
196 | ||
197 | #if 0 /* P3 this stuff is inline in ledma.c:init_restart_ledma() */ | |
198 | /* Pause until counter runs out or BIT isn't set in the DMA condition | |
199 | * register. | |
200 | */ | |
3115624e | 201 | static inline void sparc_dma_pause(struct sparc_dma_registers *regs, |
1da177e4 LT |
202 | unsigned long bit) |
203 | { | |
204 | int ctr = 50000; /* Let's find some bugs ;) */ | |
205 | ||
206 | /* Busy wait until the bit is not set any more */ | |
207 | while((regs->cond_reg&bit) && (ctr>0)) { | |
208 | ctr--; | |
209 | __delay(5); | |
210 | } | |
211 | ||
212 | /* Check for bogus outcome. */ | |
213 | if(!ctr) | |
214 | panic("DMA timeout"); | |
215 | } | |
216 | ||
217 | /* Reset the friggin' thing... */ | |
218 | #define DMA_RESET(dma) do { \ | |
219 | struct sparc_dma_registers *regs = dma->regs; \ | |
220 | /* Let the current FIFO drain itself */ \ | |
221 | sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \ | |
222 | /* Reset the logic */ \ | |
223 | regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \ | |
224 | __delay(400); /* let the bits set ;) */ \ | |
225 | regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \ | |
226 | sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \ | |
227 | /* Enable FAST transfers if available */ \ | |
228 | if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \ | |
229 | dma->running = 0; \ | |
230 | } while(0) | |
231 | #endif | |
232 | ||
233 | #define for_each_dvma(dma) \ | |
234 | for((dma) = dma_chain; (dma); (dma) = (dma)->next) | |
235 | ||
236 | extern int get_dma_list(char *); | |
237 | extern int request_dma(unsigned int, __const__ char *); | |
238 | extern void free_dma(unsigned int); | |
239 | ||
240 | /* From PCI */ | |
241 | ||
242 | #ifdef CONFIG_PCI | |
243 | extern int isa_dma_bridge_buggy; | |
244 | #else | |
245 | #define isa_dma_bridge_buggy (0) | |
246 | #endif | |
247 | ||
248 | /* Routines for data transfer buffers. */ | |
249 | BTFIXUPDEF_CALL(char *, mmu_lockarea, char *, unsigned long) | |
250 | BTFIXUPDEF_CALL(void, mmu_unlockarea, char *, unsigned long) | |
251 | ||
252 | #define mmu_lockarea(vaddr,len) BTFIXUP_CALL(mmu_lockarea)(vaddr,len) | |
253 | #define mmu_unlockarea(vaddr,len) BTFIXUP_CALL(mmu_unlockarea)(vaddr,len) | |
254 | ||
255 | /* These are implementations for sbus_map_sg/sbus_unmap_sg... collapse later */ | |
256 | BTFIXUPDEF_CALL(__u32, mmu_get_scsi_one, char *, unsigned long, struct sbus_bus *sbus) | |
257 | BTFIXUPDEF_CALL(void, mmu_get_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus) | |
258 | BTFIXUPDEF_CALL(void, mmu_release_scsi_one, __u32, unsigned long, struct sbus_bus *sbus) | |
259 | BTFIXUPDEF_CALL(void, mmu_release_scsi_sgl, struct scatterlist *, int, struct sbus_bus *sbus) | |
260 | ||
261 | #define mmu_get_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_get_scsi_one)(vaddr,len,sbus) | |
262 | #define mmu_get_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_get_scsi_sgl)(sg,sz,sbus) | |
263 | #define mmu_release_scsi_one(vaddr,len,sbus) BTFIXUP_CALL(mmu_release_scsi_one)(vaddr,len,sbus) | |
264 | #define mmu_release_scsi_sgl(sg,sz,sbus) BTFIXUP_CALL(mmu_release_scsi_sgl)(sg,sz,sbus) | |
265 | ||
266 | /* | |
267 | * mmu_map/unmap are provided by iommu/iounit; Invalid to call on IIep. | |
268 | * | |
269 | * The mmu_map_dma_area establishes two mappings in one go. | |
270 | * These mappings point to pages normally mapped at 'va' (linear address). | |
271 | * First mapping is for CPU visible address at 'a', uncached. | |
272 | * This is an alias, but it works because it is an uncached mapping. | |
273 | * Second mapping is for device visible address, or "bus" address. | |
274 | * The bus address is returned at '*pba'. | |
275 | * | |
276 | * These functions seem distinct, but are hard to split. On sun4c, | |
277 | * at least for now, 'a' is equal to bus address, and retured in *pba. | |
278 | * On sun4m, page attributes depend on the CPU type, so we have to | |
279 | * know if we are mapping RAM or I/O, so it has to be an additional argument | |
280 | * to a separate mapping function for CPU visible mappings. | |
281 | */ | |
282 | BTFIXUPDEF_CALL(int, mmu_map_dma_area, dma_addr_t *, unsigned long, unsigned long, int len) | |
283 | BTFIXUPDEF_CALL(struct page *, mmu_translate_dvma, unsigned long busa) | |
284 | BTFIXUPDEF_CALL(void, mmu_unmap_dma_area, unsigned long busa, int len) | |
285 | ||
286 | #define mmu_map_dma_area(pba,va,a,len) BTFIXUP_CALL(mmu_map_dma_area)(pba,va,a,len) | |
287 | #define mmu_unmap_dma_area(ba,len) BTFIXUP_CALL(mmu_unmap_dma_area)(ba,len) | |
288 | #define mmu_translate_dvma(ba) BTFIXUP_CALL(mmu_translate_dvma)(ba) | |
289 | ||
290 | #endif /* !(_ASM_SPARC_DMA_H) */ |