[linux-block.git] / include / asm-sh / system.h

#ifndef __ASM_SH_SYSTEM_H
#define __ASM_SH_SYSTEM_H

/*
 * Copyright (C) 1999, 2000  Niibe Yutaka  &  Kaz Kojima
 * Copyright (C) 2002 Paul Mundt
 */

#include <asm/types.h>

/*
 *	switch_to() should switch tasks to task nr n, first
 */

#define switch_to(prev, next, last) do {				\
 struct task_struct *__last;						\
 register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp;	\
 register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc;	\
 register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev;	\
 register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next;	\
 register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp;	\
 register unsigned long __ts7 __asm__ ("r7") = next->thread.pc;		\
 __asm__ __volatile__ (".balign 4\n\t" 					\
		       "stc.l	gbr, @-r15\n\t" 			\
		       "sts.l	pr, @-r15\n\t" 				\
		       "mov.l	r8, @-r15\n\t" 				\
		       "mov.l	r9, @-r15\n\t" 				\
		       "mov.l	r10, @-r15\n\t" 			\
		       "mov.l	r11, @-r15\n\t" 			\
		       "mov.l	r12, @-r15\n\t" 			\
		       "mov.l	r13, @-r15\n\t" 			\
		       "mov.l	r14, @-r15\n\t" 			\
		       "mov.l	r15, @r1	! save SP\n\t"		\
		       "mov.l	@r6, r15	! change to new stack\n\t" \
		       "mova	1f, %0\n\t" 				\
		       "mov.l	%0, @r2		! save PC\n\t" 		\
		       "mov.l	2f, %0\n\t" 				\
		       "jmp	@%0		! call __switch_to\n\t" \
		       " lds	r7, pr		!  with return to new PC\n\t" \
		       ".balign	4\n"					\
		       "2:\n\t"						\
		       ".long	__switch_to\n"				\
		       "1:\n\t"						\
		       "mov.l	@r15+, r14\n\t"				\
		       "mov.l	@r15+, r13\n\t"				\
		       "mov.l	@r15+, r12\n\t"				\
		       "mov.l	@r15+, r11\n\t"				\
		       "mov.l	@r15+, r10\n\t"				\
		       "mov.l	@r15+, r9\n\t"				\
		       "mov.l	@r15+, r8\n\t"				\
		       "lds.l	@r15+, pr\n\t"				\
		       "ldc.l	@r15+, gbr\n\t"				\
		       : "=z" (__last)					\
		       : "r" (__ts1), "r" (__ts2), "r" (__ts4), 	\
			 "r" (__ts5), "r" (__ts6), "r" (__ts7) 		\
		       : "r3", "t");					\
	last = __last;							\
} while (0)

/*
 * On SMP systems, when the scheduler does migration-cost autodetection,
 * it needs a way to flush as much of the CPU's caches as possible.
 *
 * TODO: fill this in!
 */
static inline void sched_cacheflush(void)
{
}

#ifdef CONFIG_CPU_SH4A
#define __icbi()			\
{					\
	unsigned long __addr;		\
	__addr = 0xa8000000;		\
	__asm__ __volatile__(		\
		"icbi   %0\n\t"		\
		: /* no output */	\
		: "m" (__m(__addr)));	\
}
#endif

static __inline__ unsigned long tas(volatile int *m)
{
	unsigned long retval;

	__asm__ __volatile__ ("tas.b	@%1\n\t"
			      "movt	%0"
			      : "=r" (retval): "r" (m): "t", "memory");
	return retval;
}

/*
 * A brief note on ctrl_barrier(), the control register write barrier.
 *
 * Legacy SH cores typically require a sequence of 8 nops after
 * modification of a control register in order for the changes to take
 * effect. On newer cores (like the sh4a and sh5) this is accomplished
 * with icbi.
 *
 * Also note that on sh4a in the icbi case we can forego a synco for the
 * write barrier, as it's not necessary for control registers.
 *
 * Historically we have only done this type of barrier for the MMUCR, but
 * it's also necessary for the CCR, so we make it generic here instead.
 */
#ifdef CONFIG_CPU_SH4A
#define mb()		__asm__ __volatile__ ("synco": : :"memory")
#define rmb()		mb()
#define wmb()		__asm__ __volatile__ ("synco": : :"memory")
#define ctrl_barrier()	__icbi()
#define read_barrier_depends()	do { } while(0)
#else
#define mb()		__asm__ __volatile__ ("": : :"memory")
#define rmb()		mb()
#define wmb()		__asm__ __volatile__ ("": : :"memory")
#define ctrl_barrier()	__asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
#define read_barrier_depends()	do { } while(0)
#endif

#ifdef CONFIG_SMP
#define smp_mb()	mb()
#define smp_rmb()	rmb()
#define smp_wmb()	wmb()
#define smp_read_barrier_depends()	read_barrier_depends()
#else
#define smp_mb()	barrier()
#define smp_rmb()	barrier()
#define smp_wmb()	barrier()
#define smp_read_barrier_depends()	do { } while(0)
#endif

#define set_mb(var, value) do { xchg(&var, value); } while (0)

/* Interrupt Control */
#ifdef CONFIG_CPU_HAS_SR_RB
static inline void local_irq_enable(void)
{
	unsigned long __dummy0, __dummy1;

	__asm__ __volatile__("stc	sr, %0\n\t"
			     "and	%1, %0\n\t"
			     "stc	r6_bank, %1\n\t"
			     "or	%1, %0\n\t"
			     "ldc	%0, sr"
			     : "=&r" (__dummy0), "=r" (__dummy1)
			     : "1" (~0x000000f0)
			     : "memory");
}
#else
static inline void local_irq_enable(void)
{
	unsigned long __dummy0, __dummy1;

	__asm__ __volatile__ (
		"stc	sr, %0\n\t"
		"and	%1, %0\n\t"
		"ldc	%0, sr\n\t"
		: "=&r" (__dummy0), "=r" (__dummy1)
		: "1" (~0x000000f0)
		: "memory");
}
#endif

static __inline__ void local_irq_disable(void)
{
	unsigned long __dummy;
	__asm__ __volatile__("stc	sr, %0\n\t"
			     "or	#0xf0, %0\n\t"
			     "ldc	%0, sr"
			     : "=&z" (__dummy)
			     : /* no inputs */
			     : "memory");
}

static __inline__ void set_bl_bit(void)
{
	unsigned long __dummy0, __dummy1;

	__asm__ __volatile__ ("stc	sr, %0\n\t"
			     "or	%2, %0\n\t"
			     "and	%3, %0\n\t"
			     "ldc	%0, sr"
			     : "=&r" (__dummy0), "=r" (__dummy1)
			     : "r" (0x10000000), "r" (0xffffff0f)
			     : "memory");
}

static __inline__ void clear_bl_bit(void)
{
	unsigned long __dummy0, __dummy1;

	__asm__ __volatile__ ("stc	sr, %0\n\t"
			     "and	%2, %0\n\t"
			     "ldc	%0, sr"
			     : "=&r" (__dummy0), "=r" (__dummy1)
			     : "1" (~0x10000000)
			     : "memory");
}

#define local_save_flags(x) \
	__asm__("stc sr, %0; and #0xf0, %0" : "=&z" (x) :/**/: "memory" )

#define irqs_disabled()			\
({					\
	unsigned long flags;		\
	local_save_flags(flags);	\
	(flags != 0);			\
})

static __inline__ unsigned long local_irq_save(void)
{
	unsigned long flags, __dummy;

	__asm__ __volatile__("stc	sr, %1\n\t"
			     "mov	%1, %0\n\t"
			     "or	#0xf0, %0\n\t"
			     "ldc	%0, sr\n\t"
			     "mov	%1, %0\n\t"
			     "and	#0xf0, %0"
			     : "=&z" (flags), "=&r" (__dummy)
			     :/**/
			     : "memory" );
	return flags;
}

#ifdef DEBUG_CLI_STI
static __inline__ void  local_irq_restore(unsigned long x)
{
	if ((x & 0x000000f0) != 0x000000f0)
		local_irq_enable();
	else {
		unsigned long flags;
		local_save_flags(flags);

		if (flags == 0) {
			extern void dump_stack(void);
			printk(KERN_ERR "BUG!\n");
			dump_stack();
			local_irq_disable();
		}
	}
}
#else
#define local_irq_restore(x) do {			\
	if ((x & 0x000000f0) != 0x000000f0)		\
		local_irq_enable();			\
} while (0)
#endif

#define really_restore_flags(x) do {			\
	if ((x & 0x000000f0) != 0x000000f0)		\
		local_irq_enable();			\
	else						\
		local_irq_disable();			\
} while (0)

/*
 * Jump to P2 area.
 * When handling TLB or caches, we need to do it from P2 area.
 */
#define jump_to_P2()			\
do {					\
	unsigned long __dummy;		\
	__asm__ __volatile__(		\
		"mov.l	1f, %0\n\t"	\
		"or	%1, %0\n\t"	\
		"jmp	@%0\n\t"	\
		" nop\n\t" 		\
		".balign 4\n"		\
		"1:	.long 2f\n"	\
		"2:"			\
		: "=&r" (__dummy)	\
		: "r" (0x20000000));	\
} while (0)

/*
 * Back to P1 area.
 */
#define back_to_P1()					\
do {							\
	unsigned long __dummy;				\
	ctrl_barrier();					\
	__asm__ __volatile__(				\
		"mov.l	1f, %0\n\t"			\
		"jmp	@%0\n\t"			\
		" nop\n\t"				\
		".balign 4\n"				\
		"1:	.long 2f\n"			\
		"2:"					\
		: "=&r" (__dummy));			\
} while (0)

/* For spinlocks etc */
#define local_irq_save(x)	x = local_irq_save()

static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
{
	unsigned long flags, retval;

	local_irq_save(flags);
	retval = *m;
	*m = val;
	local_irq_restore(flags);
	return retval;
}

static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
{
	unsigned long flags, retval;

	local_irq_save(flags);
	retval = *m;
	*m = val & 0xff;
	local_irq_restore(flags);
	return retval;
}

extern void __xchg_called_with_bad_pointer(void);

#define __xchg(ptr, x, size)				\
({							\
	unsigned long __xchg__res;			\
	volatile void *__xchg_ptr = (ptr);		\
	switch (size) {					\
	case 4:						\
		__xchg__res = xchg_u32(__xchg_ptr, x);	\
		break;					\
	case 1:						\
		__xchg__res = xchg_u8(__xchg_ptr, x);	\
		break;					\
	default:					\
		__xchg_called_with_bad_pointer();	\
		__xchg__res = x;			\
		break;					\
	}						\
							\
	__xchg__res;					\
})

#define xchg(ptr,x)	\
	((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))

static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
	unsigned long new)
{
	__u32 retval;
	unsigned long flags;

	local_irq_save(flags);
	retval = *m;
	if (retval == old)
		*m = new;
	local_irq_restore(flags);       /* implies memory barrier  */
	return retval;
}

/* This function doesn't exist, so you'll get a linker error
 * if something tries to do an invalid cmpxchg(). */
extern void __cmpxchg_called_with_bad_pointer(void);

#define __HAVE_ARCH_CMPXCHG 1

static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
		unsigned long new, int size)
{
	switch (size) {
	case 4:
		return __cmpxchg_u32(ptr, old, new);
	}
	__cmpxchg_called_with_bad_pointer();
	return old;
}

#define cmpxchg(ptr,o,n)						 \
  ({									 \
     __typeof__(*(ptr)) _o_ = (o);					 \
     __typeof__(*(ptr)) _n_ = (n);					 \
     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,		 \
				    (unsigned long)_n_, sizeof(*(ptr))); \
  })

/* XXX
 * disable hlt during certain critical i/o operations
 */
#define HAVE_DISABLE_HLT
void disable_hlt(void);
void enable_hlt(void);

#define arch_align_stack(x) (x)

#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_SH_SYSTEM_H
	2	#define __ASM_SH_SYSTEM_H
	3
	4	/*
	5	* Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
	6	* Copyright (C) 2002 Paul Mundt
	7	*/
	8
e4e3b5cc	9	#include <asm/types.h>
1da177e4 LT	10
	11	/*
	12	* switch_to() should switch tasks to task nr n, first
	13	*/
	14
	15	#define switch_to(prev, next, last) do { \
36c8b586	16	struct task_struct *__last; \
1da177e4 LT	17	register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \
	18	register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \
	19	register unsigned long __ts4 __asm__ ("r4") = (unsigned long )prev; \
	20	register unsigned long __ts5 __asm__ ("r5") = (unsigned long )next; \
	21	register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \
	22	register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \
	23	__asm__ __volatile__ (".balign 4\n\t" \
	24	"stc.l gbr, @-r15\n\t" \
	25	"sts.l pr, @-r15\n\t" \
	26	"mov.l r8, @-r15\n\t" \
	27	"mov.l r9, @-r15\n\t" \
	28	"mov.l r10, @-r15\n\t" \
	29	"mov.l r11, @-r15\n\t" \
	30	"mov.l r12, @-r15\n\t" \
	31	"mov.l r13, @-r15\n\t" \
	32	"mov.l r14, @-r15\n\t" \
	33	"mov.l r15, @r1 ! save SP\n\t" \
	34	"mov.l @r6, r15 ! change to new stack\n\t" \
	35	"mova 1f, %0\n\t" \
	36	"mov.l %0, @r2 ! save PC\n\t" \
	37	"mov.l 2f, %0\n\t" \
	38	"jmp @%0 ! call __switch_to\n\t" \
	39	" lds r7, pr ! with return to new PC\n\t" \
	40	".balign 4\n" \
	41	"2:\n\t" \
	42	".long __switch_to\n" \
	43	"1:\n\t" \
	44	"mov.l @r15+, r14\n\t" \
	45	"mov.l @r15+, r13\n\t" \
	46	"mov.l @r15+, r12\n\t" \
	47	"mov.l @r15+, r11\n\t" \
	48	"mov.l @r15+, r10\n\t" \
	49	"mov.l @r15+, r9\n\t" \
	50	"mov.l @r15+, r8\n\t" \
	51	"lds.l @r15+, pr\n\t" \
	52	"ldc.l @r15+, gbr\n\t" \
	53	: "=z" (__last) \
	54	: "r" (__ts1), "r" (__ts2), "r" (__ts4), \
	55	"r" (__ts5), "r" (__ts6), "r" (__ts7) \
	56	: "r3", "t"); \
	57	last = __last; \
	58	} while (0)
	59
4dc7a0bb IM	60	/*
	61	* On SMP systems, when the scheduler does migration-cost autodetection,
	62	* it needs a way to flush as much of the CPU's caches as possible.
	63	*
	64	* TODO: fill this in!
	65	*/
	66	static inline void sched_cacheflush(void)
	67	{
	68	}
	69
29847622 PM	70	#ifdef CONFIG_CPU_SH4A
	71	#define __icbi() \
	72	{ \
	73	unsigned long __addr; \
	74	__addr = 0xa8000000; \
	75	__asm__ __volatile__( \
	76	"icbi %0\n\t" \
	77	: /* no output */ \
	78	: "m" (__m(__addr))); \
	79	}
	80	#endif
1da177e4	81
1da177e4	82	static __inline__ unsigned long tas(volatile int *m)
00b3aa3f	83	{
1da177e4 LT	84	unsigned long retval;
	85
	86	__asm__ __volatile__ ("tas.b @%1\n\t"
	87	"movt %0"
	88	: "=r" (retval): "r" (m): "t", "memory");
	89	return retval;
	90	}
	91
29847622 PM	92	/*
	93	* A brief note on ctrl_barrier(), the control register write barrier.
	94	*
	95	* Legacy SH cores typically require a sequence of 8 nops after
	96	* modification of a control register in order for the changes to take
	97	* effect. On newer cores (like the sh4a and sh5) this is accomplished
	98	* with icbi.
	99	*
	100	* Also note that on sh4a in the icbi case we can forego a synco for the
	101	* write barrier, as it's not necessary for control registers.
	102	*
	103	* Historically we have only done this type of barrier for the MMUCR, but
	104	* it's also necessary for the CCR, so we make it generic here instead.
	105	*/
fdfc74f9	106	#ifdef CONFIG_CPU_SH4A
29847622 PM	107	#define mb() __asm__ __volatile__ ("synco": : :"memory")
	108	#define rmb() mb()
	109	#define wmb() __asm__ __volatile__ ("synco": : :"memory")
	110	#define ctrl_barrier() __icbi()
fdfc74f9 PM	111	#define read_barrier_depends() do { } while(0)
fdfc74f9 PM	112	#else
29847622 PM	113	#define mb() __asm__ __volatile__ ("": : :"memory")
	114	#define rmb() mb()
	115	#define wmb() __asm__ __volatile__ ("": : :"memory")
	116	#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
1da177e4	117	#define read_barrier_depends() do { } while(0)
fdfc74f9	118	#endif
1da177e4 LT	119
	120	#ifdef CONFIG_SMP
	121	#define smp_mb() mb()
	122	#define smp_rmb() rmb()
	123	#define smp_wmb() wmb()
	124	#define smp_read_barrier_depends() read_barrier_depends()
	125	#else
	126	#define smp_mb() barrier()
	127	#define smp_rmb() barrier()
	128	#define smp_wmb() barrier()
	129	#define smp_read_barrier_depends() do { } while(0)
	130	#endif
	131
	132	#define set_mb(var, value) do { xchg(&var, value); } while (0)
1da177e4 LT	133
1da177e4 LT	134	/* Interrupt Control */
f1517494 PM	135	#ifdef CONFIG_CPU_HAS_SR_RB
f1517494 PM	136	static inline void local_irq_enable(void)
1da177e4 LT	137	{
	138	unsigned long __dummy0, __dummy1;
	139
	140	__asm__ __volatile__("stc sr, %0\n\t"
	141	"and %1, %0\n\t"
	142	"stc r6_bank, %1\n\t"
	143	"or %1, %0\n\t"
	144	"ldc %0, sr"
	145	: "=&r" (__dummy0), "=r" (__dummy1)
	146	: "1" (~0x000000f0)
	147	: "memory");
	148	}
f1517494 PM	149	#else
	150	static inline void local_irq_enable(void)
	151	{
	152	unsigned long __dummy0, __dummy1;
	153
	154	__asm__ __volatile__ (
	155	"stc sr, %0\n\t"
	156	"and %1, %0\n\t"
	157	"ldc %0, sr\n\t"
	158	: "=&r" (__dummy0), "=r" (__dummy1)
	159	: "1" (~0x000000f0)
	160	: "memory");
	161	}
	162	#endif
1da177e4 LT	163
	164	static __inline__ void local_irq_disable(void)
	165	{
	166	unsigned long __dummy;
	167	__asm__ __volatile__("stc sr, %0\n\t"
	168	"or #0xf0, %0\n\t"
	169	"ldc %0, sr"
	170	: "=&z" (__dummy)
	171	: /* no inputs */
	172	: "memory");
	173	}
	174
3aa770e7 AS	175	static __inline__ void set_bl_bit(void)
	176	{
	177	unsigned long __dummy0, __dummy1;
	178
	179	__asm__ __volatile__ ("stc sr, %0\n\t"
	180	"or %2, %0\n\t"
	181	"and %3, %0\n\t"
	182	"ldc %0, sr"
	183	: "=&r" (__dummy0), "=r" (__dummy1)
	184	: "r" (0x10000000), "r" (0xffffff0f)
	185	: "memory");
	186	}
	187
	188	static __inline__ void clear_bl_bit(void)
	189	{
	190	unsigned long __dummy0, __dummy1;
	191
	192	__asm__ __volatile__ ("stc sr, %0\n\t"
	193	"and %2, %0\n\t"
	194	"ldc %0, sr"
	195	: "=&r" (__dummy0), "=r" (__dummy1)
	196	: "1" (~0x10000000)
	197	: "memory");
	198	}
	199
1da177e4 LT	200	#define local_save_flags(x) \
	201	__asm__("stc sr, %0; and #0xf0, %0" : "=&z" (x) :/**/: "memory" )
	202
	203	#define irqs_disabled() \
	204	({ \
	205	unsigned long flags; \
	206	local_save_flags(flags); \
	207	(flags != 0); \
	208	})
	209
	210	static __inline__ unsigned long local_irq_save(void)
	211	{
	212	unsigned long flags, __dummy;
	213
	214	__asm__ __volatile__("stc sr, %1\n\t"
	215	"mov %1, %0\n\t"
	216	"or #0xf0, %0\n\t"
	217	"ldc %0, sr\n\t"
	218	"mov %1, %0\n\t"
	219	"and #0xf0, %0"
	220	: "=&z" (flags), "=&r" (__dummy)
	221	:/**/
	222	: "memory" );
	223	return flags;
	224	}
	225
	226	#ifdef DEBUG_CLI_STI
	227	static __inline__ void local_irq_restore(unsigned long x)
	228	{
	229	if ((x & 0x000000f0) != 0x000000f0)
	230	local_irq_enable();
	231	else {
	232	unsigned long flags;
	233	local_save_flags(flags);
	234
	235	if (flags == 0) {
	236	extern void dump_stack(void);
	237	printk(KERN_ERR "BUG!\n");
	238	dump_stack();
	239	local_irq_disable();
	240	}
	241	}
	242	}
	243	#else
00b3aa3f	244	#define local_irq_restore(x) do { \
1da177e4	245	if ((x & 0x000000f0) != 0x000000f0) \
00b3aa3f	246	local_irq_enable(); \
1da177e4 LT	247	} while (0)
	248	#endif
	249
00b3aa3f	250	#define really_restore_flags(x) do { \
1da177e4	251	if ((x & 0x000000f0) != 0x000000f0) \
00b3aa3f	252	local_irq_enable(); \
1da177e4	253	else \
00b3aa3f	254	local_irq_disable(); \
1da177e4 LT	255	} while (0)
	256
	257	/*
	258	* Jump to P2 area.
	259	* When handling TLB or caches, we need to do it from P2 area.
	260	*/
	261	#define jump_to_P2() \
	262	do { \
	263	unsigned long __dummy; \
	264	__asm__ __volatile__( \
	265	"mov.l 1f, %0\n\t" \
	266	"or %1, %0\n\t" \
	267	"jmp @%0\n\t" \
	268	" nop\n\t" \
	269	".balign 4\n" \
	270	"1: .long 2f\n" \
	271	"2:" \
	272	: "=&r" (__dummy) \
	273	: "r" (0x20000000)); \
	274	} while (0)
	275
	276	/*
	277	* Back to P1 area.
	278	*/
	279	#define back_to_P1() \
	280	do { \
	281	unsigned long __dummy; \
29847622	282	ctrl_barrier(); \
1da177e4	283	__asm__ __volatile__( \
1da177e4 LT	284	"mov.l 1f, %0\n\t" \
	285	"jmp @%0\n\t" \
	286	" nop\n\t" \
	287	".balign 4\n" \
	288	"1: .long 2f\n" \
	289	"2:" \
	290	: "=&r" (__dummy)); \
	291	} while (0)
	292
	293	/* For spinlocks etc */
	294	#define local_irq_save(x) x = local_irq_save()
	295
00b3aa3f	296	static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
1da177e4 LT	297	{
	298	unsigned long flags, retval;
	299
	300	local_irq_save(flags);
	301	retval = *m;
	302	*m = val;
	303	local_irq_restore(flags);
	304	return retval;
	305	}
	306
00b3aa3f	307	static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
1da177e4 LT	308	{
	309	unsigned long flags, retval;
	310
	311	local_irq_save(flags);
	312	retval = *m;
	313	*m = val & 0xff;
	314	local_irq_restore(flags);
	315	return retval;
	316	}
	317
00b3aa3f PM	318	extern void __xchg_called_with_bad_pointer(void);
	319
	320	#define __xchg(ptr, x, size) \
	321	({ \
	322	unsigned long __xchg__res; \
	323	volatile void *__xchg_ptr = (ptr); \
	324	switch (size) { \
	325	case 4: \
	326	__xchg__res = xchg_u32(__xchg_ptr, x); \
	327	break; \
	328	case 1: \
	329	__xchg__res = xchg_u8(__xchg_ptr, x); \
	330	break; \
	331	default: \
	332	__xchg_called_with_bad_pointer(); \
	333	__xchg__res = x; \
	334	break; \
	335	} \
	336	\
	337	__xchg__res; \
	338	})
	339
	340	#define xchg(ptr,x) \
	341	((__typeof__((ptr)))__xchg((ptr),(unsigned long)(x), sizeof((ptr))))
1da177e4	342
e4e3b5cc TR	343	static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
	344	unsigned long new)
	345	{
	346	__u32 retval;
	347	unsigned long flags;
	348
	349	local_irq_save(flags);
	350	retval = *m;
	351	if (retval == old)
	352	*m = new;
	353	local_irq_restore(flags); /* implies memory barrier */
	354	return retval;
	355	}
	356
	357	/* This function doesn't exist, so you'll get a linker error
	358	* if something tries to do an invalid cmpxchg(). */
	359	extern void __cmpxchg_called_with_bad_pointer(void);
	360
	361	#define __HAVE_ARCH_CMPXCHG 1
	362
	363	static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
	364	unsigned long new, int size)
	365	{
	366	switch (size) {
	367	case 4:
	368	return __cmpxchg_u32(ptr, old, new);
	369	}
	370	__cmpxchg_called_with_bad_pointer();
	371	return old;
	372	}
	373
	374	#define cmpxchg(ptr,o,n) \
	375	({ \
	376	__typeof__(*(ptr)) _o_ = (o); \
	377	__typeof__(*(ptr)) _n_ = (n); \
	378	(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
	379	(unsigned long)_n_, sizeof(*(ptr))); \
	380	})
	381
1da177e4 LT	382	/* XXX
	383	* disable hlt during certain critical i/o operations
	384	*/
	385	#define HAVE_DISABLE_HLT
	386	void disable_hlt(void);
	387	void enable_hlt(void);
	388
	389	#define arch_align_stack(x) (x)
	390
	391	#endif