projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 6865f0ea RS |
1 | #ifndef __ASM_SH_SE7722_H |
| 2 | #define __ASM_SH_SE7722_H | |
| 3 | ||
| 4 | /* | |
| 5 | * linux/include/asm-sh/se7722.h | |
| 6 | * | |
| 7 | * Copyright (C) 2007 Nobuhiro Iwamatsu | |
| 8 | * | |
| 9 | * Hitachi UL SolutionEngine 7722 Support. | |
| 10 | * | |
| 11 | * This file is subject to the terms and conditions of the GNU General Public | |
| 12 | * License. See the file "COPYING" in the main directory of this archive | |
| 13 | * for more details. | |
| 14 | * | |
| 15 | */ | |
| 16 | #include <asm/addrspace.h> | |
| 17 | ||
| 18 | /* Box specific addresses. */ | |
| 19 | #define SE_AREA0_WIDTH 4 /* Area0: 32bit */ | |
| 20 | #define PA_ROM 0xa0000000 /* EPROM */ | |
| 21 | #define PA_ROM_SIZE 0x00200000 /* EPROM size 2M byte */ | |
| 22 | #define PA_FROM 0xa1000000 /* Flash-ROM */ | |
| 23 | #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */ | |
| 24 | #define PA_EXT1 0xa4000000 | |
| 25 | #define PA_EXT1_SIZE 0x04000000 | |
| 26 | #define PA_SDRAM 0xaC000000 /* DDR-SDRAM(Area3) 64MB */ | |
| 27 | #define PA_SDRAM_SIZE 0x04000000 | |
| 28 | ||
| 29 | #define PA_EXT4 0xb0000000 | |
| 30 | #define PA_EXT4_SIZE 0x04000000 | |
| 31 | ||
| 32 | #define PA_PERIPHERAL 0xB0000000 | |
| 33 | ||
| 34 | #define PA_PCIC PA_PERIPHERAL /* MR-SHPC-01 PCMCIA */ | |
| 35 | #define PA_MRSHPC (PA_PERIPHERAL + 0x003fffe0) /* MR-SHPC-01 PCMCIA controller */ | |
| 36 | #define PA_MRSHPC_MW1 (PA_PERIPHERAL + 0x00400000) /* MR-SHPC-01 memory window base */ | |
| 37 | #define PA_MRSHPC_MW2 (PA_PERIPHERAL + 0x00500000) /* MR-SHPC-01 attribute window base */ | |
| 38 | #define PA_MRSHPC_IO (PA_PERIPHERAL + 0x00600000) /* MR-SHPC-01 I/O window base */ | |
| 39 | #define MRSHPC_OPTION (PA_MRSHPC + 6) | |
| 40 | #define MRSHPC_CSR (PA_MRSHPC + 8) | |
| 41 | #define MRSHPC_ISR (PA_MRSHPC + 10) | |
| 42 | #define MRSHPC_ICR (PA_MRSHPC + 12) | |
| 43 | #define MRSHPC_CPWCR (PA_MRSHPC + 14) | |
| 44 | #define MRSHPC_MW0CR1 (PA_MRSHPC + 16) | |
| 45 | #define MRSHPC_MW1CR1 (PA_MRSHPC + 18) | |
| 46 | #define MRSHPC_IOWCR1 (PA_MRSHPC + 20) | |
| 47 | #define MRSHPC_MW0CR2 (PA_MRSHPC + 22) | |
| 48 | #define MRSHPC_MW1CR2 (PA_MRSHPC + 24) | |
| 49 | #define MRSHPC_IOWCR2 (PA_MRSHPC + 26) | |
| 50 | #define MRSHPC_CDCR (PA_MRSHPC + 28) | |
| 51 | #define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) | |
| 52 | ||
| 53 | #define PA_LED (PA_PERIPHERAL + 0x00800000) /* 8bit LED */ | |
| 54 | #define PA_FPGA (PA_PERIPHERAL + 0x01800000) /* FPGA base address */ | |
| 55 | ||
| 56 | #define PA_LAN (PA_AREA6_IO + 0) /* SMC LAN91C111 */ | |
| 57 | /* GPIO */ | |
| 58 | #define MSTPCR0 0xA4150030UL | |
| 59 | #define MSTPCR1 0xA4150034UL | |
| 60 | #define MSTPCR2 0xA4150038UL | |
| 61 | ||
| 62 | #define FPGA_IN 0xb1840000UL | |
| 63 | #define FPGA_OUT 0xb1840004UL | |
| 64 | ||
| 65 | #define PORT_PECR 0xA4050108UL | |
| 66 | #define PORT_PJCR 0xA4050110UL | |
| 67 | #define PORT_PSELD 0xA4050154UL | |
| 68 | #define PORT_PSELB 0xA4050150UL | |
| 69 | ||
| 70 | #define PORT_PSELC 0xA4050152UL | |
| 71 | #define PORT_PKCR 0xA4050112UL | |
| 72 | #define PORT_PHCR 0xA405010EUL | |
| 73 | #define PORT_PLCR 0xA4050114UL | |
| 74 | #define PORT_PMCR 0xA4050116UL | |
| 75 | #define PORT_PRCR 0xA405011CUL | |
| 76 | #define PORT_PXCR 0xA4050148UL | |
| 77 | #define PORT_PSELA 0xA405014EUL | |
| 78 | #define PORT_PYCR 0xA405014AUL | |
| 79 | #define PORT_PZCR 0xA405014CUL | |
| 80 | ||
| 81 | /* IRQ */ | |
| 82 | #define IRQ0_IRQ 32 | |
| 83 | #define IRQ1_IRQ 33 | |
| 84 | #define INTC_ICR0 0xA4140000UL | |
| 85 | #define INTC_ICR1 0xA414001CUL | |
| 86 | ||
| 87 | #define INTMSK0 0xa4140044 | |
| 88 | #define INTMSKCLR0 0xa4140064 | |
| 89 | #define INTC_INTPRI0 0xa4140010 | |
| 90 | ||
| 91 | #define IRQ01_MODE 0xb1800000 | |
| 92 | #define IRQ01_STS 0xb1800004 | |
| 93 | #define IRQ01_MASK 0xb1800008 | |
| 94 | #define EXT_BIT (0x3fc0) /* SH IRQ1 */ | |
| 95 | #define MRSHPC_BIT0 (0x0004) /* SH IRQ1 */ | |
| 96 | #define MRSHPC_BIT1 (0x0008) /* SH IRQ1 */ | |
| 97 | #define MRSHPC_BIT2 (0x0010) /* SH IRQ1 */ | |
| 98 | #define MRSHPC_BIT3 (0x0020) /* SH IRQ1 */ | |
| 99 | #define SMC_BIT (0x0002) /* SH IRQ0 */ | |
| 100 | #define USB_BIT (0x0001) /* SH IRQ0 */ | |
| 101 | ||
| 102 | #define MRSHPC_IRQ3 11 | |
| 103 | #define MRSHPC_IRQ2 12 | |
| 104 | #define MRSHPC_IRQ1 13 | |
| 105 | #define MRSHPC_IRQ0 14 | |
| 106 | #define SMC_IRQ 10 | |
| 107 | #define EXT_IRQ 5 | |
| 108 | #define USB_IRQ 6 | |
| 109 | ||
| 110 | ||
| 111 | /* arch/sh/boards/se/7722/irq.c */ | |
| 112 | void init_se7722_IRQ(void); | |
| 113 | int se7722_irq_demux(int); | |
| 114 | ||
| 115 | #define __IO_PREFIX se7722 | |
| 116 | #include <asm/io_generic.h> | |
| 117 | ||
| 118 | #endif /* __ASM_SH_SE7722_H */ |