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1da177e4 LT |
1 | #ifndef __ASM_SH_IRQ_H |
2 | #define __ASM_SH_IRQ_H | |
3 | ||
4 | /* | |
5 | * | |
6 | * linux/include/asm-sh/irq.h | |
7 | * | |
8 | * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi | |
9 | * Copyright (C) 2000 Kazumoto Kojima | |
10 | * Copyright (C) 2003 Paul Mundt | |
11 | * | |
12 | */ | |
13 | ||
14 | #include <linux/config.h> | |
15 | #include <asm/machvec.h> | |
16 | #include <asm/ptrace.h> /* for pt_regs */ | |
17 | ||
18 | #if defined(CONFIG_SH_HP600) || \ | |
19 | defined(CONFIG_SH_RTS7751R2D) || \ | |
20 | defined(CONFIG_SH_HS7751RVOIP) || \ | |
21 | defined(CONFIG_SH_SH03) | |
22 | #include <asm/mach/ide.h> | |
23 | #endif | |
24 | ||
25 | #if defined(CONFIG_CPU_SH3) | |
26 | #define INTC_IPRA 0xfffffee2UL | |
27 | #define INTC_IPRB 0xfffffee4UL | |
28 | #elif defined(CONFIG_CPU_SH4) | |
29 | #define INTC_IPRA 0xffd00004UL | |
30 | #define INTC_IPRB 0xffd00008UL | |
31 | #define INTC_IPRC 0xffd0000cUL | |
32 | #define INTC_IPRD 0xffd00010UL | |
33 | #endif | |
34 | ||
35 | #ifdef CONFIG_IDE | |
36 | # ifndef IRQ_CFCARD | |
37 | # define IRQ_CFCARD 14 | |
38 | # endif | |
39 | # ifndef IRQ_PCMCIA | |
40 | # define IRQ_PCMCIA 15 | |
41 | # endif | |
42 | #endif | |
43 | ||
44 | #define TIMER_IRQ 16 | |
45 | #define TIMER_IPR_ADDR INTC_IPRA | |
46 | #define TIMER_IPR_POS 3 | |
47 | #define TIMER_PRIORITY 2 | |
48 | ||
49 | #define TIMER1_IRQ 17 | |
50 | #define TIMER1_IPR_ADDR INTC_IPRA | |
51 | #define TIMER1_IPR_POS 2 | |
52 | #define TIMER1_PRIORITY 4 | |
53 | ||
54 | #define RTC_IRQ 22 | |
55 | #define RTC_IPR_ADDR INTC_IPRA | |
56 | #define RTC_IPR_POS 0 | |
57 | #define RTC_PRIORITY TIMER_PRIORITY | |
58 | ||
59 | #if defined(CONFIG_CPU_SH3) | |
60 | #define DMTE0_IRQ 48 | |
61 | #define DMTE1_IRQ 49 | |
62 | #define DMTE2_IRQ 50 | |
63 | #define DMTE3_IRQ 51 | |
64 | #define DMA_IPR_ADDR INTC_IPRE | |
65 | #define DMA_IPR_POS 3 | |
66 | #define DMA_PRIORITY 7 | |
67 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) | |
68 | /* TMU2 */ | |
69 | #define TIMER2_IRQ 18 | |
70 | #define TIMER2_IPR_ADDR INTC_IPRA | |
71 | #define TIMER2_IPR_POS 1 | |
72 | #define TIMER2_PRIORITY 2 | |
73 | ||
74 | /* WDT */ | |
75 | #define WDT_IRQ 27 | |
76 | #define WDT_IPR_ADDR INTC_IPRB | |
77 | #define WDT_IPR_POS 3 | |
78 | #define WDT_PRIORITY 2 | |
79 | ||
80 | /* SIM (SIM Card Module) */ | |
81 | #define SIM_ERI_IRQ 23 | |
82 | #define SIM_RXI_IRQ 24 | |
83 | #define SIM_TXI_IRQ 25 | |
84 | #define SIM_TEND_IRQ 26 | |
85 | #define SIM_IPR_ADDR INTC_IPRB | |
86 | #define SIM_IPR_POS 1 | |
87 | #define SIM_PRIORITY 2 | |
88 | ||
89 | /* VIO (Video I/O) */ | |
90 | #define VIO_IRQ 52 | |
91 | #define VIO_IPR_ADDR INTC_IPRE | |
92 | #define VIO_IPR_POS 2 | |
93 | #define VIO_PRIORITY 2 | |
94 | ||
95 | /* MFI (Multi Functional Interface) */ | |
96 | #define MFI_IRQ 56 | |
97 | #define MFI_IPR_ADDR INTC_IPRE | |
98 | #define MFI_IPR_POS 1 | |
99 | #define MFI_PRIORITY 2 | |
100 | ||
101 | /* VPU (Video Processing Unit) */ | |
102 | #define VPU_IRQ 60 | |
103 | #define VPU_IPR_ADDR INTC_IPRE | |
104 | #define VPU_IPR_POS 0 | |
105 | #define VPU_PRIORITY 2 | |
106 | ||
107 | /* KEY (Key Scan Interface) */ | |
108 | #define KEY_IRQ 79 | |
109 | #define KEY_IPR_ADDR INTC_IPRF | |
110 | #define KEY_IPR_POS 3 | |
111 | #define KEY_PRIORITY 2 | |
112 | ||
113 | /* CMT (Compare Match Timer) */ | |
114 | #define CMT_IRQ 104 | |
115 | #define CMT_IPR_ADDR INTC_IPRF | |
116 | #define CMT_IPR_POS 0 | |
117 | #define CMT_PRIORITY 2 | |
118 | ||
119 | /* DMAC(1) */ | |
120 | #define DMTE0_IRQ 48 | |
121 | #define DMTE1_IRQ 49 | |
122 | #define DMTE2_IRQ 50 | |
123 | #define DMTE3_IRQ 51 | |
124 | #define DMA1_IPR_ADDR INTC_IPRE | |
125 | #define DMA1_IPR_POS 3 | |
126 | #define DMA1_PRIORITY 7 | |
127 | ||
128 | /* DMAC(2) */ | |
129 | #define DMTE4_IRQ 76 | |
130 | #define DMTE5_IRQ 77 | |
131 | #define DMA2_IPR_ADDR INTC_IPRF | |
132 | #define DMA2_IPR_POS 2 | |
133 | #define DMA2_PRIORITY 7 | |
134 | ||
135 | /* SIOF0 */ | |
136 | #define SIOF0_IRQ 84 | |
137 | #define SIOF0_IPR_ADDR INTC_IPRH | |
138 | #define SIOF0_IPR_POS 3 | |
139 | #define SIOF0_PRIORITY 3 | |
140 | ||
141 | /* FLCTL (Flash Memory Controller) */ | |
142 | #define FLSTE_IRQ 92 | |
143 | #define FLTEND_IRQ 93 | |
144 | #define FLTRQ0_IRQ 94 | |
145 | #define FLTRQ1_IRQ 95 | |
146 | #define FLCTL_IPR_ADDR INTC_IPRH | |
147 | #define FLCTL_IPR_POS 1 | |
148 | #define FLCTL_PRIORITY 3 | |
149 | ||
150 | /* IIC (IIC Bus Interface) */ | |
151 | #define IIC_ALI_IRQ 96 | |
152 | #define IIC_TACKI_IRQ 97 | |
153 | #define IIC_WAITI_IRQ 98 | |
154 | #define IIC_DTEI_IRQ 99 | |
155 | #define IIC_IPR_ADDR INTC_IPRH | |
156 | #define IIC_IPR_POS 0 | |
157 | #define IIC_PRIORITY 3 | |
158 | ||
159 | /* SIO0 */ | |
160 | #define SIO0_IRQ 88 | |
161 | #define SIO0_IPR_ADDR INTC_IPRI | |
162 | #define SIO0_IPR_POS 3 | |
163 | #define SIO0_PRIORITY 3 | |
164 | ||
165 | /* SIU (Sound Interface Unit) */ | |
166 | #define SIU_IRQ 108 | |
167 | #define SIU_IPR_ADDR INTC_IPRJ | |
168 | #define SIU_IPR_POS 1 | |
169 | #define SIU_PRIORITY 3 | |
170 | ||
171 | #endif | |
172 | #elif defined(CONFIG_CPU_SH4) | |
173 | #define DMTE0_IRQ 34 | |
174 | #define DMTE1_IRQ 35 | |
175 | #define DMTE2_IRQ 36 | |
176 | #define DMTE3_IRQ 37 | |
177 | #define DMTE4_IRQ 44 /* 7751R only */ | |
178 | #define DMTE5_IRQ 45 /* 7751R only */ | |
179 | #define DMTE6_IRQ 46 /* 7751R only */ | |
180 | #define DMTE7_IRQ 47 /* 7751R only */ | |
181 | #define DMAE_IRQ 38 | |
182 | #define DMA_IPR_ADDR INTC_IPRC | |
183 | #define DMA_IPR_POS 2 | |
184 | #define DMA_PRIORITY 7 | |
185 | #endif | |
186 | ||
187 | #if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \ | |
188 | defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \ | |
189 | defined (CONFIG_CPU_SUBTYPE_SH7751) | |
190 | #define SCI_ERI_IRQ 23 | |
191 | #define SCI_RXI_IRQ 24 | |
192 | #define SCI_TXI_IRQ 25 | |
193 | #define SCI_IPR_ADDR INTC_IPRB | |
194 | #define SCI_IPR_POS 1 | |
195 | #define SCI_PRIORITY 3 | |
196 | #endif | |
197 | ||
198 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) | |
199 | #define SCIF0_IRQ 80 | |
200 | #define SCIF0_IPR_ADDR INTC_IPRG | |
201 | #define SCIF0_IPR_POS 3 | |
202 | #define SCIF0_PRIORITY 3 | |
203 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | |
204 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | |
205 | defined(CONFIG_CPU_SUBTYPE_SH7709) | |
206 | #define SCIF_ERI_IRQ 56 | |
207 | #define SCIF_RXI_IRQ 57 | |
208 | #define SCIF_BRI_IRQ 58 | |
209 | #define SCIF_TXI_IRQ 59 | |
210 | #define SCIF_IPR_ADDR INTC_IPRE | |
211 | #define SCIF_IPR_POS 1 | |
212 | #define SCIF_PRIORITY 3 | |
213 | ||
214 | #define IRDA_ERI_IRQ 52 | |
215 | #define IRDA_RXI_IRQ 53 | |
216 | #define IRDA_BRI_IRQ 54 | |
217 | #define IRDA_TXI_IRQ 55 | |
218 | #define IRDA_IPR_ADDR INTC_IPRE | |
219 | #define IRDA_IPR_POS 2 | |
220 | #define IRDA_PRIORITY 3 | |
221 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
222 | defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202) | |
223 | #define SCIF_ERI_IRQ 40 | |
224 | #define SCIF_RXI_IRQ 41 | |
225 | #define SCIF_BRI_IRQ 42 | |
226 | #define SCIF_TXI_IRQ 43 | |
227 | #define SCIF_IPR_ADDR INTC_IPRC | |
228 | #define SCIF_IPR_POS 1 | |
229 | #define SCIF_PRIORITY 3 | |
230 | #if defined(CONFIG_CPU_SUBTYPE_ST40STB1) | |
231 | #define SCIF1_ERI_IRQ 23 | |
232 | #define SCIF1_RXI_IRQ 24 | |
233 | #define SCIF1_BRI_IRQ 25 | |
234 | #define SCIF1_TXI_IRQ 26 | |
235 | #define SCIF1_IPR_ADDR INTC_IPRB | |
236 | #define SCIF1_IPR_POS 1 | |
237 | #define SCIF1_PRIORITY 3 | |
238 | #endif | |
239 | #endif | |
240 | ||
241 | /* NR_IRQS is made from three components: | |
242 | * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules | |
243 | * 2. PINT_NR_IRQS - number of PINT interrupts | |
244 | * 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules | |
245 | */ | |
246 | ||
247 | /* 1. ONCHIP_NR_IRQS */ | |
248 | #ifdef CONFIG_SH_GENERIC | |
249 | # define ONCHIP_NR_IRQS 144 | |
250 | #else | |
251 | # if defined(CONFIG_CPU_SUBTYPE_SH7604) | |
252 | # define ONCHIP_NR_IRQS 24 // Actually 21 | |
253 | # elif defined(CONFIG_CPU_SUBTYPE_SH7707) | |
254 | # define ONCHIP_NR_IRQS 64 | |
255 | # define PINT_NR_IRQS 16 | |
256 | # elif defined(CONFIG_CPU_SUBTYPE_SH7708) | |
257 | # define ONCHIP_NR_IRQS 32 | |
258 | # elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \ | |
259 | defined(CONFIG_CPU_SUBTYPE_SH7705) | |
260 | # define ONCHIP_NR_IRQS 64 // Actually 61 | |
261 | # define PINT_NR_IRQS 16 | |
262 | # elif defined(CONFIG_CPU_SUBTYPE_SH7750) | |
263 | # define ONCHIP_NR_IRQS 48 // Actually 44 | |
264 | # elif defined(CONFIG_CPU_SUBTYPE_SH7751) | |
265 | # define ONCHIP_NR_IRQS 72 | |
266 | # elif defined(CONFIG_CPU_SUBTYPE_SH7760) | |
267 | # define ONCHIP_NR_IRQS 110 | |
268 | # elif defined(CONFIG_CPU_SUBTYPE_SH4_202) | |
269 | # define ONCHIP_NR_IRQS 72 | |
270 | # elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) | |
271 | # define ONCHIP_NR_IRQS 144 | |
272 | # elif defined(CONFIG_CPU_SUBTYPE_SH7300) | |
273 | # define ONCHIP_NR_IRQS 109 | |
274 | # endif | |
275 | #endif | |
276 | ||
277 | /* 2. PINT_NR_IRQS */ | |
278 | #ifdef CONFIG_SH_GENERIC | |
279 | # define PINT_NR_IRQS 16 | |
280 | #else | |
281 | # ifndef PINT_NR_IRQS | |
282 | # define PINT_NR_IRQS 0 | |
283 | # endif | |
284 | #endif | |
285 | ||
286 | #if PINT_NR_IRQS > 0 | |
287 | # define PINT_IRQ_BASE ONCHIP_NR_IRQS | |
288 | #endif | |
289 | ||
290 | /* 3. OFFCHIP_NR_IRQS */ | |
291 | #ifdef CONFIG_SH_GENERIC | |
292 | # define OFFCHIP_NR_IRQS 16 | |
293 | #else | |
294 | # if defined(CONFIG_HD64461) | |
295 | # define OFFCHIP_NR_IRQS 18 | |
296 | # elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */ | |
297 | # define OFFCHIP_NR_IRQS 48 | |
298 | # elif defined(CONFIG_HD64465) | |
299 | # define OFFCHIP_NR_IRQS 16 | |
300 | # elif defined (CONFIG_SH_EC3104) | |
301 | # define OFFCHIP_NR_IRQS 16 | |
302 | # elif defined (CONFIG_SH_DREAMCAST) | |
303 | # define OFFCHIP_NR_IRQS 96 | |
304 | # else | |
305 | # define OFFCHIP_NR_IRQS 0 | |
306 | # endif | |
307 | #endif | |
308 | ||
309 | #if OFFCHIP_NR_IRQS > 0 | |
310 | # define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS) | |
311 | #endif | |
312 | ||
313 | /* NR_IRQS. 1+2+3 */ | |
314 | #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS) | |
315 | ||
316 | /* In a generic kernel, NR_IRQS is an upper bound, and we should use | |
317 | * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value. | |
318 | */ | |
319 | #ifdef CONFIG_SH_GENERIC | |
320 | # define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs) | |
321 | #else | |
322 | # define ACTUAL_NR_IRQS NR_IRQS | |
323 | #endif | |
324 | ||
325 | ||
326 | extern void disable_irq(unsigned int); | |
327 | extern void disable_irq_nosync(unsigned int); | |
328 | extern void enable_irq(unsigned int); | |
329 | ||
330 | /* | |
331 | * Simple Mask Register Support | |
332 | */ | |
333 | extern void make_maskreg_irq(unsigned int irq); | |
334 | extern unsigned short *irq_mask_register; | |
335 | ||
336 | /* | |
337 | * Function for "on chip support modules". | |
338 | */ | |
339 | extern void make_ipr_irq(unsigned int irq, unsigned int addr, | |
340 | int pos, int priority); | |
341 | extern void make_imask_irq(unsigned int irq); | |
342 | ||
343 | #if defined(CONFIG_CPU_SUBTYPE_SH7300) | |
344 | #undef INTC_IPRA | |
345 | #undef INTC_IPRB | |
346 | #define INTC_IPRA 0xA414FEE2UL | |
347 | #define INTC_IPRB 0xA414FEE4UL | |
348 | #define INTC_IPRC 0xA4140016UL | |
349 | #define INTC_IPRD 0xA4140018UL | |
350 | #define INTC_IPRE 0xA414001AUL | |
351 | #define INTC_IPRF 0xA4080000UL | |
352 | #define INTC_IPRG 0xA4080002UL | |
353 | #define INTC_IPRH 0xA4080004UL | |
354 | #define INTC_IPRI 0xA4080006UL | |
355 | #define INTC_IPRJ 0xA4080008UL | |
356 | ||
357 | #define INTC_IMR0 0xA4080040UL | |
358 | #define INTC_IMR1 0xA4080042UL | |
359 | #define INTC_IMR2 0xA4080044UL | |
360 | #define INTC_IMR3 0xA4080046UL | |
361 | #define INTC_IMR4 0xA4080048UL | |
362 | #define INTC_IMR5 0xA408004AUL | |
363 | #define INTC_IMR6 0xA408004CUL | |
364 | #define INTC_IMR7 0xA408004EUL | |
365 | #define INTC_IMR8 0xA4080050UL | |
366 | #define INTC_IMR9 0xA4080052UL | |
367 | #define INTC_IMR10 0xA4080054UL | |
368 | ||
369 | #define INTC_IMCR0 0xA4080060UL | |
370 | #define INTC_IMCR1 0xA4080062UL | |
371 | #define INTC_IMCR2 0xA4080064UL | |
372 | #define INTC_IMCR3 0xA4080066UL | |
373 | #define INTC_IMCR4 0xA4080068UL | |
374 | #define INTC_IMCR5 0xA408006AUL | |
375 | #define INTC_IMCR6 0xA408006CUL | |
376 | #define INTC_IMCR7 0xA408006EUL | |
377 | #define INTC_IMCR8 0xA4080070UL | |
378 | #define INTC_IMCR9 0xA4080072UL | |
379 | #define INTC_IMCR10 0xA4080074UL | |
380 | ||
381 | #define INTC_ICR0 0xA414FEE0UL | |
382 | #define INTC_ICR1 0xA4140010UL | |
383 | ||
384 | #define INTC_IRR0 0xA4140004UL | |
385 | ||
386 | #define PORT_PACR 0xA4050100UL | |
387 | #define PORT_PBCR 0xA4050102UL | |
388 | #define PORT_PCCR 0xA4050104UL | |
389 | #define PORT_PDCR 0xA4050106UL | |
390 | #define PORT_PECR 0xA4050108UL | |
391 | #define PORT_PFCR 0xA405010AUL | |
392 | #define PORT_PGCR 0xA405010CUL | |
393 | #define PORT_PHCR 0xA405010EUL | |
394 | #define PORT_PJCR 0xA4050110UL | |
395 | #define PORT_PKCR 0xA4050112UL | |
396 | #define PORT_PLCR 0xA4050114UL | |
397 | #define PORT_SCPCR 0xA4050116UL | |
398 | #define PORT_PMCR 0xA4050118UL | |
399 | #define PORT_PNCR 0xA405011AUL | |
400 | #define PORT_PQCR 0xA405011CUL | |
401 | ||
402 | #define PORT_PSELA 0xA4050140UL | |
403 | #define PORT_PSELB 0xA4050142UL | |
404 | #define PORT_PSELC 0xA4050144UL | |
405 | ||
406 | #define PORT_HIZCRA 0xA4050146UL | |
407 | #define PORT_HIZCRB 0xA4050148UL | |
408 | #define PORT_DRVCR 0xA4050150UL | |
409 | ||
410 | #define PORT_PADR 0xA4050120UL | |
411 | #define PORT_PBDR 0xA4050122UL | |
412 | #define PORT_PCDR 0xA4050124UL | |
413 | #define PORT_PDDR 0xA4050126UL | |
414 | #define PORT_PEDR 0xA4050128UL | |
415 | #define PORT_PFDR 0xA405012AUL | |
416 | #define PORT_PGDR 0xA405012CUL | |
417 | #define PORT_PHDR 0xA405012EUL | |
418 | #define PORT_PJDR 0xA4050130UL | |
419 | #define PORT_PKDR 0xA4050132UL | |
420 | #define PORT_PLDR 0xA4050134UL | |
421 | #define PORT_SCPDR 0xA4050136UL | |
422 | #define PORT_PMDR 0xA4050138UL | |
423 | #define PORT_PNDR 0xA405013AUL | |
424 | #define PORT_PQDR 0xA405013CUL | |
425 | ||
426 | #define IRQ0_IRQ 32 | |
427 | #define IRQ1_IRQ 33 | |
428 | #define IRQ2_IRQ 34 | |
429 | #define IRQ3_IRQ 35 | |
430 | #define IRQ4_IRQ 36 | |
431 | #define IRQ5_IRQ 37 | |
432 | ||
433 | #define IRQ0_IPR_ADDR INTC_IPRC | |
434 | #define IRQ1_IPR_ADDR INTC_IPRC | |
435 | #define IRQ2_IPR_ADDR INTC_IPRC | |
436 | #define IRQ3_IPR_ADDR INTC_IPRC | |
437 | #define IRQ4_IPR_ADDR INTC_IPRD | |
438 | #define IRQ5_IPR_ADDR INTC_IPRD | |
439 | ||
440 | #define IRQ0_IPR_POS 0 | |
441 | #define IRQ1_IPR_POS 1 | |
442 | #define IRQ2_IPR_POS 2 | |
443 | #define IRQ3_IPR_POS 3 | |
444 | #define IRQ4_IPR_POS 0 | |
445 | #define IRQ5_IPR_POS 1 | |
446 | ||
447 | #define IRQ0_PRIORITY 1 | |
448 | #define IRQ1_PRIORITY 1 | |
449 | #define IRQ2_PRIORITY 1 | |
450 | #define IRQ3_PRIORITY 1 | |
451 | #define IRQ4_PRIORITY 1 | |
452 | #define IRQ5_PRIORITY 1 | |
453 | ||
454 | extern int ipr_irq_demux(int irq); | |
455 | #define __irq_demux(irq) ipr_irq_demux(irq) | |
456 | ||
457 | #elif defined(CONFIG_CPU_SUBTYPE_SH7604) | |
458 | #define INTC_IPRA 0xfffffee2UL | |
459 | #define INTC_IPRB 0xfffffe60UL | |
460 | ||
461 | #define INTC_VCRA 0xfffffe62UL | |
462 | #define INTC_VCRB 0xfffffe64UL | |
463 | #define INTC_VCRC 0xfffffe66UL | |
464 | #define INTC_VCRD 0xfffffe68UL | |
465 | ||
466 | #define INTC_VCRWDT 0xfffffee4UL | |
467 | #define INTC_VCRDIV 0xffffff0cUL | |
468 | #define INTC_VCRDMA0 0xffffffa0UL | |
469 | #define INTC_VCRDMA1 0xffffffa8UL | |
470 | ||
471 | #define INTC_ICR 0xfffffee0UL | |
472 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ | |
473 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | |
474 | defined(CONFIG_CPU_SUBTYPE_SH7709) | |
475 | #define INTC_IRR0 0xa4000004UL | |
476 | #define INTC_IRR1 0xa4000006UL | |
477 | #define INTC_IRR2 0xa4000008UL | |
478 | ||
479 | #define INTC_ICR0 0xfffffee0UL | |
480 | #define INTC_ICR1 0xa4000010UL | |
481 | #define INTC_ICR2 0xa4000012UL | |
482 | #define INTC_INTER 0xa4000014UL | |
483 | ||
484 | #define INTC_IPRC 0xa4000016UL | |
485 | #define INTC_IPRD 0xa4000018UL | |
486 | #define INTC_IPRE 0xa400001aUL | |
487 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) | |
488 | #define INTC_IPRF 0xa400001cUL | |
489 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | |
490 | #define INTC_IPRF 0xa4080000UL | |
491 | #define INTC_IPRG 0xa4080002UL | |
492 | #define INTC_IPRH 0xa4080004UL | |
493 | #endif | |
494 | ||
495 | #define PORT_PACR 0xa4000100UL | |
496 | #define PORT_PBCR 0xa4000102UL | |
497 | #define PORT_PCCR 0xa4000104UL | |
498 | #define PORT_PFCR 0xa400010aUL | |
499 | #define PORT_PADR 0xa4000120UL | |
500 | #define PORT_PBDR 0xa4000122UL | |
501 | #define PORT_PCDR 0xa4000124UL | |
502 | #define PORT_PFDR 0xa400012aUL | |
503 | ||
504 | #define IRQ0_IRQ 32 | |
505 | #define IRQ1_IRQ 33 | |
506 | #define IRQ2_IRQ 34 | |
507 | #define IRQ3_IRQ 35 | |
508 | #define IRQ4_IRQ 36 | |
509 | #define IRQ5_IRQ 37 | |
510 | ||
511 | #define IRQ0_IPR_ADDR INTC_IPRC | |
512 | #define IRQ1_IPR_ADDR INTC_IPRC | |
513 | #define IRQ2_IPR_ADDR INTC_IPRC | |
514 | #define IRQ3_IPR_ADDR INTC_IPRC | |
515 | #define IRQ4_IPR_ADDR INTC_IPRD | |
516 | #define IRQ5_IPR_ADDR INTC_IPRD | |
517 | ||
518 | #define IRQ0_IPR_POS 0 | |
519 | #define IRQ1_IPR_POS 1 | |
520 | #define IRQ2_IPR_POS 2 | |
521 | #define IRQ3_IPR_POS 3 | |
522 | #define IRQ4_IPR_POS 0 | |
523 | #define IRQ5_IPR_POS 1 | |
524 | ||
525 | #define IRQ0_PRIORITY 1 | |
526 | #define IRQ1_PRIORITY 1 | |
527 | #define IRQ2_PRIORITY 1 | |
528 | #define IRQ3_PRIORITY 1 | |
529 | #define IRQ4_PRIORITY 1 | |
530 | #define IRQ5_PRIORITY 1 | |
531 | ||
532 | #define PINT0_IRQ 40 | |
533 | #define PINT8_IRQ 41 | |
534 | ||
535 | #define PINT0_IPR_ADDR INTC_IPRD | |
536 | #define PINT8_IPR_ADDR INTC_IPRD | |
537 | ||
538 | #define PINT0_IPR_POS 3 | |
539 | #define PINT8_IPR_POS 2 | |
540 | #define PINT0_PRIORITY 2 | |
541 | #define PINT8_PRIORITY 2 | |
542 | ||
543 | extern int ipr_irq_demux(int irq); | |
544 | #define __irq_demux(irq) ipr_irq_demux(irq) | |
545 | ||
546 | #else | |
547 | #define __irq_demux(irq) irq | |
548 | #endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */ | |
549 | ||
550 | #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | |
551 | defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202) | |
552 | #define INTC_ICR 0xffd00000 | |
553 | #define INTC_ICR_NMIL (1<<15) | |
554 | #define INTC_ICR_MAI (1<<14) | |
555 | #define INTC_ICR_NMIB (1<<9) | |
556 | #define INTC_ICR_NMIE (1<<8) | |
557 | #define INTC_ICR_IRLM (1<<7) | |
558 | #endif | |
559 | ||
560 | #ifdef CONFIG_CPU_SUBTYPE_ST40STB1 | |
561 | ||
562 | #define INTC2_FIRST_IRQ 64 | |
563 | #define NR_INTC2_IRQS 25 | |
564 | ||
565 | #define INTC2_BASE 0xfe080000 | |
566 | #define INTC2_INTC2MODE (INTC2_BASE+0x80) | |
567 | ||
568 | #define INTC2_INTPRI_OFFSET 0x00 | |
569 | #define INTC2_INTREQ_OFFSET 0x20 | |
570 | #define INTC2_INTMSK_OFFSET 0x40 | |
571 | #define INTC2_INTMSKCLR_OFFSET 0x60 | |
572 | ||
573 | void make_intc2_irq(unsigned int irq, | |
574 | unsigned int ipr_offset, unsigned int ipr_shift, | |
575 | unsigned int msk_offset, unsigned int msk_shift, | |
576 | unsigned int priority); | |
577 | void init_IRQ_intc2(void); | |
578 | void intc2_add_clear_irq(int irq, int (*fn)(int)); | |
579 | ||
580 | #endif /* CONFIG_CPU_SUBTYPE_ST40STB1 */ | |
581 | ||
582 | static inline int generic_irq_demux(int irq) | |
583 | { | |
584 | return irq; | |
585 | } | |
586 | ||
587 | #define irq_canonicalize(irq) (irq) | |
588 | #define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq)) | |
589 | ||
1da177e4 LT |
590 | #if defined(CONFIG_CPU_SUBTYPE_SH73180) |
591 | #include <asm/irq-sh73180.h> | |
592 | #endif | |
593 | ||
594 | #endif /* __ASM_SH_IRQ_H */ |