[linux-block.git] / include / asm-sh / hw_irq.h

#ifndef __ASM_SH_HW_IRQ_H
#define __ASM_SH_HW_IRQ_H

#include <linux/init.h>
#include <asm/atomic.h>

extern atomic_t irq_err_count;

struct intc2_data {
	unsigned short irq;
	unsigned char ipr_offset, ipr_shift;
	unsigned char msk_offset, msk_shift;
	unsigned char priority;
};

struct intc2_desc {
	unsigned long prio_base;
	unsigned long msk_base;
	unsigned long mskclr_base;
	struct intc2_data *intc2_data;
	unsigned int nr_irqs;
	struct irq_chip chip;
};

void register_intc2_controller(struct intc2_desc *);

struct ipr_data {
	unsigned char irq;
	unsigned char ipr_idx;		/* Index for the IPR registered */
	unsigned char shift;		/* Number of bits to shift the data */
	unsigned char priority;		/* The priority */
};

struct ipr_desc {
	unsigned long *ipr_offsets;
	unsigned int nr_offsets;
	struct ipr_data *ipr_data;
	unsigned int nr_irqs;
	struct irq_chip chip;
};

void register_ipr_controller(struct ipr_desc *);

typedef unsigned char intc_enum;

struct intc_vect {
	intc_enum enum_id;
	unsigned short vect;
};

#define INTC_VECT(enum_id, vect) { enum_id, vect }
#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))

struct intc_prio {
	intc_enum enum_id;
	unsigned char priority;
};

#define INTC_PRIO(enum_id, prio) { enum_id, prio }

struct intc_group {
	intc_enum enum_id;
	intc_enum *enum_ids;
};

#define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } }

struct intc_mask_reg {
	unsigned long set_reg, clr_reg, reg_width;
	intc_enum enum_ids[32];
};

struct intc_prio_reg {
	unsigned long reg, reg_width, field_width;
	intc_enum enum_ids[16];
};

struct intc_sense_reg {
	unsigned long reg, reg_width, field_width;
	intc_enum enum_ids[16];
};

struct intc_desc {
	struct intc_vect *vectors;
	unsigned int nr_vectors;
	struct intc_group *groups;
	unsigned int nr_groups;
	struct intc_prio *priorities;
	unsigned int nr_priorities;
	struct intc_mask_reg *mask_regs;
	unsigned int nr_mask_regs;
	struct intc_prio_reg *prio_regs;
	unsigned int nr_prio_regs;
	struct intc_sense_reg *sense_regs;
	unsigned int nr_sense_regs;
	struct irq_chip chip;
};

#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups,		\
	priorities, mask_regs, prio_regs, sense_regs)			\
struct intc_desc symbol = {						\
	_INTC_ARRAY(vectors), _INTC_ARRAY(groups),			\
	_INTC_ARRAY(priorities),					\
	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),			\
	_INTC_ARRAY(sense_regs),					\
	.chip.name = chipname,						\
}

void __init register_intc_controller(struct intc_desc *desc);

void __init plat_irq_setup(void);

enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
       IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
void __init plat_irq_setup_pins(int mode);

#endif /* __ASM_SH_HW_IRQ_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef __ASM_SH_HW_IRQ_H
	2	#define __ASM_SH_HW_IRQ_H
	3
02ab3f70	4	#include <linux/init.h>
35f3c518 PM	5	#include <asm/atomic.h>
	6
	7	extern atomic_t irq_err_count;
	8
d619500a MD	9	struct intc2_data {
	10	unsigned short irq;
	11	unsigned char ipr_offset, ipr_shift;
	12	unsigned char msk_offset, msk_shift;
	13	unsigned char priority;
	14	};
	15
	16	struct intc2_desc {
	17	unsigned long prio_base;
	18	unsigned long msk_base;
	19	unsigned long mskclr_base;
	20	struct intc2_data *intc2_data;
	21	unsigned int nr_irqs;
	22	struct irq_chip chip;
	23	};
	24
	25	void register_intc2_controller(struct intc2_desc *);
d619500a	26
68abdbbb MD	27	struct ipr_data {
	28	unsigned char irq;
	29	unsigned char ipr_idx; /* Index for the IPR registered */
	30	unsigned char shift; /* Number of bits to shift the data */
	31	unsigned char priority; /* The priority */
	32	};
	33
	34	struct ipr_desc {
	35	unsigned long *ipr_offsets;
	36	unsigned int nr_offsets;
	37	struct ipr_data *ipr_data;
	38	unsigned int nr_irqs;
	39	struct irq_chip chip;
	40	};
	41
	42	void register_ipr_controller(struct ipr_desc *);
68abdbbb	43
02ab3f70 MD	44	typedef unsigned char intc_enum;
	45
	46	struct intc_vect {
	47	intc_enum enum_id;
	48	unsigned short vect;
	49	};
	50
	51	#define INTC_VECT(enum_id, vect) { enum_id, vect }
51da6426	52	#define INTC_IRQ(enum_id, irq) INTC_VECT(enum_id, irq2evt(irq))
02ab3f70 MD	53
	54	struct intc_prio {
	55	intc_enum enum_id;
	56	unsigned char priority;
	57	};
	58
	59	#define INTC_PRIO(enum_id, prio) { enum_id, prio }
	60
	61	struct intc_group {
	62	intc_enum enum_id;
	63	intc_enum *enum_ids;
	64	};
	65
	66	#define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } }
	67
	68	struct intc_mask_reg {
	69	unsigned long set_reg, clr_reg, reg_width;
	70	intc_enum enum_ids[32];
	71	};
	72
	73	struct intc_prio_reg {
	74	unsigned long reg, reg_width, field_width;
	75	intc_enum enum_ids[16];
	76	};
	77
	78	struct intc_sense_reg {
	79	unsigned long reg, reg_width, field_width;
	80	intc_enum enum_ids[16];
	81	};
	82
	83	struct intc_desc {
	84	struct intc_vect *vectors;
	85	unsigned int nr_vectors;
	86	struct intc_group *groups;
	87	unsigned int nr_groups;
	88	struct intc_prio *priorities;
	89	unsigned int nr_priorities;
	90	struct intc_mask_reg *mask_regs;
	91	unsigned int nr_mask_regs;
	92	struct intc_prio_reg *prio_regs;
	93	unsigned int nr_prio_regs;
	94	struct intc_sense_reg *sense_regs;
	95	unsigned int nr_sense_regs;
	96	struct irq_chip chip;
	97	};
	98
	99	#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
	100	#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
	101	priorities, mask_regs, prio_regs, sense_regs) \
1b06428e	102	struct intc_desc symbol = { \
02ab3f70 MD	103	_INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
	104	_INTC_ARRAY(priorities), \
	105	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
	106	_INTC_ARRAY(sense_regs), \
	107	.chip.name = chipname, \
	108	}
	109
	110	void __init register_intc_controller(struct intc_desc *desc);
	111
90015c89 MD	112	void __init plat_irq_setup(void);
90015c89 MD	113
a0e23267 MD	114	enum { IRQ_MODE_IRQ, IRQ_MODE_IRQ7654, IRQ_MODE_IRQ3210,
a0e23267 MD	115	IRQ_MODE_IRL7654, IRQ_MODE_IRL3210 };
39c7aa9e MD	116	void __init plat_irq_setup_pins(int mode);
39c7aa9e MD	117
1da177e4	118	#endif /* __ASM_SH_HW_IRQ_H */