projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * include/asm-sh/cpu-sh4/timer.h | |
| 3 | * | |
| 2b1bd1ac | 4 | * Copyright (C) 2004 Lineo Solutions, Inc. |
| 1da177e4 LT |
5 | * |
| 6 | * This file is subject to the terms and conditions of the GNU General Public | |
| 7 | * License. See the file "COPYING" in the main directory of this archive | |
| 8 | * for more details. | |
| 9 | */ | |
| 10 | #ifndef __ASM_CPU_SH4_TIMER_H | |
| 11 | #define __ASM_CPU_SH4_TIMER_H | |
| 12 | ||
| 13 | /* | |
| 14 | * --------------------------------------------------------------------------- | |
| 15 | * TMU Common definitions for SH4 processors | |
| 16 | * SH7750S/SH7750R | |
| 17 | * SH7751/SH7751R | |
| 18 | * SH7760 | |
| 2b1bd1ac | 19 | * SH-X3 |
| 1da177e4 LT |
20 | * --------------------------------------------------------------------------- |
| 21 | */ | |
| 2b1bd1ac PM |
22 | #ifdef CONFIG_CPU_SUBTYPE_SHX3 |
| 23 | #define TMU_012_BASE 0xffc10000 | |
| 24 | #define TMU_345_BASE 0xffc20000 | |
| 25 | #else | |
| 26 | #define TMU_012_BASE 0xffd80000 | |
| 27 | #define TMU_345_BASE 0xfe100000 | |
| 1da177e4 | 28 | #endif |
| 1da177e4 | 29 | |
| 2b1bd1ac | 30 | #define TMU_TOCR TMU_012_BASE /* Not supported on all CPUs */ |
| 1da177e4 | 31 | |
| 2b1bd1ac PM |
32 | #define TMU_012_TSTR (TMU_012_BASE + 0x04) |
| 33 | #define TMU_345_TSTR (TMU_345_BASE + 0x04) | |
| 1da177e4 | 34 | |
| 2b1bd1ac PM |
35 | #define TMU0_TCOR (TMU_012_BASE + 0x08) |
| 36 | #define TMU0_TCNT (TMU_012_BASE + 0x0c) | |
| 37 | #define TMU0_TCR (TMU_012_BASE + 0x10) | |
| 1da177e4 | 38 | |
| 2b1bd1ac PM |
39 | #define TMU1_TCOR (TMU_012_BASE + 0x14) |
| 40 | #define TMU1_TCNT (TMU_012_BASE + 0x18) | |
| 41 | #define TMU1_TCR (TMU_012_BASE + 0x1c) | |
| 1da177e4 | 42 | |
| 2b1bd1ac PM |
43 | #define TMU2_TCOR (TMU_012_BASE + 0x20) |
| 44 | #define TMU2_TCNT (TMU_012_BASE + 0x24) | |
| 45 | #define TMU2_TCR (TMU_012_BASE + 0x28) | |
| 46 | #define TMU2_TCPR (TMU_012_BASE + 0x2c) | |
| 1da177e4 | 47 | |
| 2b1bd1ac PM |
48 | #define TMU3_TCOR (TMU_345_BASE + 0x08) |
| 49 | #define TMU3_TCNT (TMU_345_BASE + 0x0c) | |
| 50 | #define TMU3_TCR (TMU_345_BASE + 0x10) | |
| 1da177e4 | 51 | |
| 2b1bd1ac PM |
52 | #define TMU4_TCOR (TMU_345_BASE + 0x14) |
| 53 | #define TMU4_TCNT (TMU_345_BASE + 0x18) | |
| 54 | #define TMU4_TCR (TMU_345_BASE + 0x1c) | |
| 55 | ||
| 56 | #define TMU5_TCOR (TMU_345_BASE + 0x20) | |
| 57 | #define TMU5_TCNT (TMU_345_BASE + 0x24) | |
| 58 | #define TMU5_TCR (TMU_345_BASE + 0x28) | |
| 59 | ||
| 60 | #endif /* __ASM_CPU_SH4_TIMER_H */ |