[linux-block.git] / include / asm-s390 / system.h

/*
 *  include/asm-s390/system.h
 *
 *  S390 version
 *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
 *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
 *
 *  Derived from "include/asm-i386/system.h"
 */

#ifndef __ASM_SYSTEM_H
#define __ASM_SYSTEM_H

#include <linux/kernel.h>
#include <asm/types.h>
#include <asm/ptrace.h>
#include <asm/setup.h>
#include <asm/processor.h>
#include <asm/lowcore.h>

#ifdef __KERNEL__

struct task_struct;

extern struct task_struct *__switch_to(void *, void *);

static inline void save_fp_regs(s390_fp_regs *fpregs)
{
	asm volatile(
		"	std	0,8(%1)\n"
		"	std	2,24(%1)\n"
		"	std	4,40(%1)\n"
		"	std	6,56(%1)"
		: "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory");
	if (!MACHINE_HAS_IEEE)
		return;
	asm volatile(
		"	stfpc	0(%1)\n"
		"	std	1,16(%1)\n"
		"	std	3,32(%1)\n"
		"	std	5,48(%1)\n"
		"	std	7,64(%1)\n"
		"	std	8,72(%1)\n"
		"	std	9,80(%1)\n"
		"	std	10,88(%1)\n"
		"	std	11,96(%1)\n"
		"	std	12,104(%1)\n"
		"	std	13,112(%1)\n"
		"	std	14,120(%1)\n"
		"	std	15,128(%1)\n"
		: "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory");
}

static inline void restore_fp_regs(s390_fp_regs *fpregs)
{
	asm volatile(
		"	ld	0,8(%0)\n"
		"	ld	2,24(%0)\n"
		"	ld	4,40(%0)\n"
		"	ld	6,56(%0)"
		: : "a" (fpregs), "m" (*fpregs));
	if (!MACHINE_HAS_IEEE)
		return;
	asm volatile(
		"	lfpc	0(%0)\n"
		"	ld	1,16(%0)\n"
		"	ld	3,32(%0)\n"
		"	ld	5,48(%0)\n"
		"	ld	7,64(%0)\n"
		"	ld	8,72(%0)\n"
		"	ld	9,80(%0)\n"
		"	ld	10,88(%0)\n"
		"	ld	11,96(%0)\n"
		"	ld	12,104(%0)\n"
		"	ld	13,112(%0)\n"
		"	ld	14,120(%0)\n"
		"	ld	15,128(%0)\n"
		: : "a" (fpregs), "m" (*fpregs));
}

static inline void save_access_regs(unsigned int *acrs)
{
	asm volatile("stam 0,15,0(%0)" : : "a" (acrs) : "memory");
}

static inline void restore_access_regs(unsigned int *acrs)
{
	asm volatile("lam 0,15,0(%0)" : : "a" (acrs));
}

#define switch_to(prev,next,last) do {					     \
	if (prev == next)						     \
		break;							     \
	save_fp_regs(&prev->thread.fp_regs);				     \
	restore_fp_regs(&next->thread.fp_regs);				     \
	save_access_regs(&prev->thread.acrs[0]);			     \
	restore_access_regs(&next->thread.acrs[0]);			     \
	prev = __switch_to(prev,next);					     \
} while (0)

#ifdef CONFIG_VIRT_CPU_ACCOUNTING
extern void account_vtime(struct task_struct *);
extern void account_tick_vtime(struct task_struct *);
extern void account_system_vtime(struct task_struct *);
#else
#define account_vtime(x) do { /* empty */ } while (0)
#endif

#ifdef CONFIG_PFAULT
extern void pfault_irq_init(void);
extern int pfault_init(void);
extern void pfault_fini(void);
#else /* CONFIG_PFAULT */
#define pfault_irq_init()	do { } while (0)
#define pfault_init()		({-1;})
#define pfault_fini()		do { } while (0)
#endif /* CONFIG_PFAULT */

#define finish_arch_switch(prev) do {					     \
	set_fs(current->thread.mm_segment);				     \
	account_vtime(prev);						     \
} while (0)

#define nop() asm volatile("nop")

#define xchg(ptr,x)							  \
({									  \
	__typeof__(*(ptr)) __ret;					  \
	__ret = (__typeof__(*(ptr)))					  \
		__xchg((unsigned long)(x), (void *)(ptr),sizeof(*(ptr))); \
	__ret;								  \
})

extern void __xchg_called_with_bad_pointer(void);

static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
{
	unsigned long addr, old;
	int shift;

        switch (size) {
	case 1:
		addr = (unsigned long) ptr;
		shift = (3 ^ (addr & 3)) << 3;
		addr ^= addr & 3;
		asm volatile(
			"	l	%0,0(%4)\n"
			"0:	lr	0,%0\n"
			"	nr	0,%3\n"
			"	or	0,%2\n"
			"	cs	%0,0,0(%4)\n"
			"	jl	0b\n"
			: "=&d" (old), "=m" (*(int *) addr)
			: "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
			  "m" (*(int *) addr) : "memory", "cc", "0");
		return old >> shift;
	case 2:
		addr = (unsigned long) ptr;
		shift = (2 ^ (addr & 2)) << 3;
		addr ^= addr & 2;
		asm volatile(
			"	l	%0,0(%4)\n"
			"0:	lr	0,%0\n"
			"	nr	0,%3\n"
			"	or	0,%2\n"
			"	cs	%0,0,0(%4)\n"
			"	jl	0b\n"
			: "=&d" (old), "=m" (*(int *) addr)
			: "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
			  "m" (*(int *) addr) : "memory", "cc", "0");
		return old >> shift;
	case 4:
		asm volatile(
			"	l	%0,0(%3)\n"
			"0:	cs	%0,%2,0(%3)\n"
			"	jl	0b\n"
			: "=&d" (old), "=m" (*(int *) ptr)
			: "d" (x), "a" (ptr), "m" (*(int *) ptr)
			: "memory", "cc");
		return old;
#ifdef __s390x__
	case 8:
		asm volatile(
			"	lg	%0,0(%3)\n"
			"0:	csg	%0,%2,0(%3)\n"
			"	jl	0b\n"
			: "=&d" (old), "=m" (*(long *) ptr)
			: "d" (x), "a" (ptr), "m" (*(long *) ptr)
			: "memory", "cc");
		return old;
#endif /* __s390x__ */
	}
	__xchg_called_with_bad_pointer();
	return x;
}

/*
 * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 * store NEW in MEM.  Return the initial value in MEM.  Success is
 * indicated by comparing RETURN with OLD.
 */

#define __HAVE_ARCH_CMPXCHG 1

#define cmpxchg(ptr, o, n)						\
	((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o),	\
					(unsigned long)(n), sizeof(*(ptr))))

extern void __cmpxchg_called_with_bad_pointer(void);

static inline unsigned long
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
{
	unsigned long addr, prev, tmp;
	int shift;

        switch (size) {
	case 1:
		addr = (unsigned long) ptr;
		shift = (3 ^ (addr & 3)) << 3;
		addr ^= addr & 3;
		asm volatile(
			"	l	%0,0(%4)\n"
			"0:	nr	%0,%5\n"
			"	lr	%1,%0\n"
			"	or	%0,%2\n"
			"	or	%1,%3\n"
			"	cs	%0,%1,0(%4)\n"
			"	jnl	1f\n"
			"	xr	%1,%0\n"
			"	nr	%1,%5\n"
			"	jnz	0b\n"
			"1:"
			: "=&d" (prev), "=&d" (tmp)
			: "d" (old << shift), "d" (new << shift), "a" (ptr),
			  "d" (~(255 << shift))
			: "memory", "cc");
		return prev >> shift;
	case 2:
		addr = (unsigned long) ptr;
		shift = (2 ^ (addr & 2)) << 3;
		addr ^= addr & 2;
		asm volatile(
			"	l	%0,0(%4)\n"
			"0:	nr	%0,%5\n"
			"	lr	%1,%0\n"
			"	or	%0,%2\n"
			"	or	%1,%3\n"
			"	cs	%0,%1,0(%4)\n"
			"	jnl	1f\n"
			"	xr	%1,%0\n"
			"	nr	%1,%5\n"
			"	jnz	0b\n"
			"1:"
			: "=&d" (prev), "=&d" (tmp)
			: "d" (old << shift), "d" (new << shift), "a" (ptr),
			  "d" (~(65535 << shift))
			: "memory", "cc");
		return prev >> shift;
	case 4:
		asm volatile(
			"	cs	%0,%2,0(%3)\n"
			: "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
			: "memory", "cc");
		return prev;
#ifdef __s390x__
	case 8:
		asm volatile(
			"	csg	%0,%2,0(%3)\n"
			: "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
			: "memory", "cc");
		return prev;
#endif /* __s390x__ */
        }
	__cmpxchg_called_with_bad_pointer();
	return old;
}

/*
 * Force strict CPU ordering.
 * And yes, this is required on UP too when we're talking
 * to devices.
 *
 * This is very similar to the ppc eieio/sync instruction in that is
 * does a checkpoint syncronisation & makes sure that 
 * all memory ops have completed wrt other CPU's ( see 7-15 POP  DJB ).
 */

#define eieio()	asm volatile("bcr 15,0" : : : "memory")
#define SYNC_OTHER_CORES(x)   eieio()
#define mb()    eieio()
#define rmb()   eieio()
#define wmb()   eieio()
#define read_barrier_depends() do { } while(0)
#define smp_mb()       mb()
#define smp_rmb()      rmb()
#define smp_wmb()      wmb()
#define smp_read_barrier_depends()    read_barrier_depends()
#define smp_mb__before_clear_bit()     smp_mb()
#define smp_mb__after_clear_bit()      smp_mb()


#define set_mb(var, value)      do { var = value; mb(); } while (0)

#ifdef __s390x__

#define __ctl_load(array, low, high) ({				\
	typedef struct { char _[sizeof(array)]; } addrtype;	\
	asm volatile(						\
		"	lctlg	%1,%2,0(%0)\n"			\
		: : "a" (&array), "i" (low), "i" (high),	\
		    "m" (*(addrtype *)(array)));		\
	})

#define __ctl_store(array, low, high) ({			\
	typedef struct { char _[sizeof(array)]; } addrtype;	\
	asm volatile(						\
		"	stctg	%2,%3,0(%1)\n"			\
		: "=m" (*(addrtype *)(array))			\
		: "a" (&array), "i" (low), "i" (high));		\
	})

#else /* __s390x__ */

#define __ctl_load(array, low, high) ({				\
	typedef struct { char _[sizeof(array)]; } addrtype;	\
	asm volatile(						\
		"	lctl	%1,%2,0(%0)\n"			\
		: : "a" (&array), "i" (low), "i" (high),	\
		    "m" (*(addrtype *)(array)));		\
})

#define __ctl_store(array, low, high) ({			\
	typedef struct { char _[sizeof(array)]; } addrtype;	\
	asm volatile(						\
		"	stctl	%2,%3,0(%1)\n"			\
		: "=m" (*(addrtype *)(array))			\
		: "a" (&array), "i" (low), "i" (high));		\
	})

#endif /* __s390x__ */

#define __ctl_set_bit(cr, bit) ({	\
	unsigned long __dummy;		\
	__ctl_store(__dummy, cr, cr);	\
	__dummy |= 1UL << (bit);	\
	__ctl_load(__dummy, cr, cr);	\
})

#define __ctl_clear_bit(cr, bit) ({	\
	unsigned long __dummy;		\
	__ctl_store(__dummy, cr, cr);	\
	__dummy &= ~(1UL << (bit));	\
	__ctl_load(__dummy, cr, cr);	\
})

#include <linux/irqflags.h>

#include <asm-generic/cmpxchg-local.h>

static inline unsigned long __cmpxchg_local(volatile void *ptr,
				      unsigned long old,
				      unsigned long new, int size)
{
	switch (size) {
	case 1:
	case 2:
	case 4:
#ifdef __s390x__
	case 8:
#endif
		return __cmpxchg(ptr, old, new, size);
	default:
		return __cmpxchg_local_generic(ptr, old, new, size);
	}

	return old;
}

/*
 * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
 * them available.
 */
#define cmpxchg_local(ptr, o, n)					\
	((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o),	\
			(unsigned long)(n), sizeof(*(ptr))))
#ifdef __s390x__
#define cmpxchg64_local(ptr, o, n)					\
  ({									\
	BUILD_BUG_ON(sizeof(*(ptr)) != 8);				\
	cmpxchg_local((ptr), (o), (n));					\
  })
#else
#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
#endif

/*
 * Use to set psw mask except for the first byte which
 * won't be changed by this function.
 */
static inline void
__set_psw_mask(unsigned long mask)
{
	__load_psw_mask(mask | (__raw_local_irq_stosm(0x00) & ~(-1UL >> 8)));
}

#define local_mcck_enable()  __set_psw_mask(psw_kernel_bits)
#define local_mcck_disable() __set_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK)

int stfle(unsigned long long *list, int doublewords);

#ifdef CONFIG_SMP

extern void smp_ctl_set_bit(int cr, int bit);
extern void smp_ctl_clear_bit(int cr, int bit);
#define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
#define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)

#else

#define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
#define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)

#endif /* CONFIG_SMP */

static inline unsigned int stfl(void)
{
	asm volatile(
		"	.insn	s,0xb2b10000,0(0)\n" /* stfl */
		"0:\n"
		EX_TABLE(0b,0b));
	return S390_lowcore.stfl_fac_list;
}

static inline unsigned short stap(void)
{
	unsigned short cpu_address;

	asm volatile("stap %0" : "=m" (cpu_address));
	return cpu_address;
}

extern void (*_machine_restart)(char *command);
extern void (*_machine_halt)(void);
extern void (*_machine_power_off)(void);

#define arch_align_stack(x) (x)

#ifdef CONFIG_TRACE_IRQFLAGS
extern psw_t sysc_restore_trace_psw;
extern psw_t io_restore_trace_psw;
#endif

#endif /* __KERNEL__ */

#endif
Commit	Line	Data
1da177e4 LT	1	/*
	2	* include/asm-s390/system.h
	3	*
	4	* S390 version
	5	* Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
	6	* Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
	7	*
	8	* Derived from "include/asm-i386/system.h"
	9	*/
	10
	11	#ifndef __ASM_SYSTEM_H
	12	#define __ASM_SYSTEM_H
	13
1da177e4 LT	14	#include <linux/kernel.h>
	15	#include <asm/types.h>
	16	#include <asm/ptrace.h>
	17	#include <asm/setup.h>
77fa2245	18	#include <asm/processor.h>
484875b1	19	#include <asm/lowcore.h>
1da177e4 LT	20
	21	#ifdef __KERNEL__
	22
	23	struct task_struct;
	24
	25	extern struct task_struct __switch_to(void , void *);
	26
1da177e4 LT	27	static inline void save_fp_regs(s390_fp_regs *fpregs)
1da177e4 LT	28	{
94c12cc7 MS	29	asm volatile(
	30	" std 0,8(%1)\n"
	31	" std 2,24(%1)\n"
	32	" std 4,40(%1)\n"
	33	" std 6,56(%1)"
	34	: "=m" (fpregs) : "a" (fpregs), "m" (fpregs) : "memory");
1da177e4 LT	35	if (!MACHINE_HAS_IEEE)
	36	return;
	37	asm volatile(
94c12cc7 MS	38	" stfpc 0(%1)\n"
	39	" std 1,16(%1)\n"
	40	" std 3,32(%1)\n"
	41	" std 5,48(%1)\n"
	42	" std 7,64(%1)\n"
	43	" std 8,72(%1)\n"
	44	" std 9,80(%1)\n"
	45	" std 10,88(%1)\n"
	46	" std 11,96(%1)\n"
	47	" std 12,104(%1)\n"
	48	" std 13,112(%1)\n"
	49	" std 14,120(%1)\n"
	50	" std 15,128(%1)\n"
	51	: "=m" (fpregs) : "a" (fpregs), "m" (fpregs) : "memory");
1da177e4 LT	52	}
	53
	54	static inline void restore_fp_regs(s390_fp_regs *fpregs)
	55	{
94c12cc7 MS	56	asm volatile(
	57	" ld 0,8(%0)\n"
	58	" ld 2,24(%0)\n"
	59	" ld 4,40(%0)\n"
	60	" ld 6,56(%0)"
	61	: : "a" (fpregs), "m" (*fpregs));
1da177e4 LT	62	if (!MACHINE_HAS_IEEE)
	63	return;
	64	asm volatile(
94c12cc7 MS	65	" lfpc 0(%0)\n"
	66	" ld 1,16(%0)\n"
	67	" ld 3,32(%0)\n"
	68	" ld 5,48(%0)\n"
	69	" ld 7,64(%0)\n"
	70	" ld 8,72(%0)\n"
	71	" ld 9,80(%0)\n"
	72	" ld 10,88(%0)\n"
	73	" ld 11,96(%0)\n"
	74	" ld 12,104(%0)\n"
	75	" ld 13,112(%0)\n"
	76	" ld 14,120(%0)\n"
	77	" ld 15,128(%0)\n"
	78	: : "a" (fpregs), "m" (*fpregs));
1da177e4 LT	79	}
	80
	81	static inline void save_access_regs(unsigned int *acrs)
	82	{
94c12cc7	83	asm volatile("stam 0,15,0(%0)" : : "a" (acrs) : "memory");
1da177e4 LT	84	}
	85
	86	static inline void restore_access_regs(unsigned int *acrs)
	87	{
94c12cc7	88	asm volatile("lam 0,15,0(%0)" : : "a" (acrs));
1da177e4 LT	89	}
	90
	91	#define switch_to(prev,next,last) do { \
	92	if (prev == next) \
	93	break; \
	94	save_fp_regs(&prev->thread.fp_regs); \
	95	restore_fp_regs(&next->thread.fp_regs); \
	96	save_access_regs(&prev->thread.acrs[0]); \
	97	restore_access_regs(&next->thread.acrs[0]); \
	98	prev = __switch_to(prev,next); \
	99	} while (0)
	100
1da177e4	101	#ifdef CONFIG_VIRT_CPU_ACCOUNTING
1f1c12af MS	102	extern void account_vtime(struct task_struct *);
1f1c12af MS	103	extern void account_tick_vtime(struct task_struct *);
1da177e4	104	extern void account_system_vtime(struct task_struct *);
5c833890 JB	105	#else
5c833890 JB	106	#define account_vtime(x) do { /* empty */ } while (0)
4866cde0	107	#endif
1da177e4	108
29b08d2b HC	109	#ifdef CONFIG_PFAULT
	110	extern void pfault_irq_init(void);
	111	extern int pfault_init(void);
	112	extern void pfault_fini(void);
	113	#else /* CONFIG_PFAULT */
	114	#define pfault_irq_init() do { } while (0)
	115	#define pfault_init() ({-1;})
	116	#define pfault_fini() do { } while (0)
	117	#endif /* CONFIG_PFAULT */
	118
5ee24d95	119	#define finish_arch_switch(prev) do { \
1da177e4	120	set_fs(current->thread.mm_segment); \
1f1c12af	121	account_vtime(prev); \
1da177e4 LT	122	} while (0)
1da177e4 LT	123
94c12cc7	124	#define nop() asm volatile("nop")
1da177e4	125
5a651c93 HC	126	#define xchg(ptr,x) \
	127	({ \
	128	__typeof__(*(ptr)) __ret; \
	129	__ret = (__typeof__(*(ptr))) \
	130	__xchg((unsigned long)(x), (void )(ptr),sizeof((ptr))); \
	131	__ret; \
	132	})
1da177e4	133
210d3a90 HC	134	extern void __xchg_called_with_bad_pointer(void);
210d3a90 HC	135
1da177e4 LT	136	static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
	137	{
	138	unsigned long addr, old;
	139	int shift;
	140
	141	switch (size) {
	142	case 1:
	143	addr = (unsigned long) ptr;
	144	shift = (3 ^ (addr & 3)) << 3;
	145	addr ^= addr & 3;
	146	asm volatile(
94c12cc7 MS	147	" l %0,0(%4)\n"
	148	"0: lr 0,%0\n"
	149	" nr 0,%3\n"
	150	" or 0,%2\n"
	151	" cs %0,0,0(%4)\n"
	152	" jl 0b\n"
1da177e4 LT	153	: "=&d" (old), "=m" ((int ) addr)
1da177e4 LT	154	: "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
94c12cc7	155	"m" ((int ) addr) : "memory", "cc", "0");
210d3a90	156	return old >> shift;
1da177e4 LT	157	case 2:
	158	addr = (unsigned long) ptr;
	159	shift = (2 ^ (addr & 2)) << 3;
	160	addr ^= addr & 2;
	161	asm volatile(
94c12cc7 MS	162	" l %0,0(%4)\n"
	163	"0: lr 0,%0\n"
	164	" nr 0,%3\n"
	165	" or 0,%2\n"
	166	" cs %0,0,0(%4)\n"
	167	" jl 0b\n"
1da177e4 LT	168	: "=&d" (old), "=m" ((int ) addr)
1da177e4 LT	169	: "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
94c12cc7	170	"m" ((int ) addr) : "memory", "cc", "0");
210d3a90	171	return old >> shift;
1da177e4	172	case 4:
94c12cc7 MS	173	asm volatile(
	174	" l %0,0(%3)\n"
	175	"0: cs %0,%2,0(%3)\n"
	176	" jl 0b\n"
1da177e4 LT	177	: "=&d" (old), "=m" ((int ) ptr)
1da177e4 LT	178	: "d" (x), "a" (ptr), "m" ((int ) ptr)
94c12cc7	179	: "memory", "cc");
210d3a90	180	return old;
1da177e4 LT	181	#ifdef __s390x__
1da177e4 LT	182	case 8:
94c12cc7 MS	183	asm volatile(
	184	" lg %0,0(%3)\n"
	185	"0: csg %0,%2,0(%3)\n"
	186	" jl 0b\n"
1da177e4 LT	187	: "=&d" (old), "=m" ((long ) ptr)
1da177e4 LT	188	: "d" (x), "a" (ptr), "m" ((long ) ptr)
94c12cc7	189	: "memory", "cc");
210d3a90	190	return old;
1da177e4	191	#endif /* __s390x__ */
210d3a90 HC	192	}
	193	__xchg_called_with_bad_pointer();
	194	return x;
1da177e4 LT	195	}
	196
	197	/*
	198	* Atomic compare and exchange. Compare OLD with MEM, if identical,
	199	* store NEW in MEM. Return the initial value in MEM. Success is
	200	* indicated by comparing RETURN with OLD.
	201	*/
	202
	203	#define __HAVE_ARCH_CMPXCHG 1
	204
fe413013 MD	205	#define cmpxchg(ptr, o, n) \
	206	((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(o), \
	207	(unsigned long)(n), sizeof(*(ptr))))
1da177e4	208
210d3a90 HC	209	extern void __cmpxchg_called_with_bad_pointer(void);
210d3a90 HC	210
1da177e4 LT	211	static inline unsigned long
	212	__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
	213	{
	214	unsigned long addr, prev, tmp;
	215	int shift;
	216
	217	switch (size) {
	218	case 1:
	219	addr = (unsigned long) ptr;
	220	shift = (3 ^ (addr & 3)) << 3;
	221	addr ^= addr & 3;
	222	asm volatile(
94c12cc7 MS	223	" l %0,0(%4)\n"
	224	"0: nr %0,%5\n"
	225	" lr %1,%0\n"
	226	" or %0,%2\n"
	227	" or %1,%3\n"
	228	" cs %0,%1,0(%4)\n"
	229	" jnl 1f\n"
	230	" xr %1,%0\n"
	231	" nr %1,%5\n"
	232	" jnz 0b\n"
1da177e4 LT	233	"1:"
	234	: "=&d" (prev), "=&d" (tmp)
	235	: "d" (old << shift), "d" (new << shift), "a" (ptr),
	236	"d" (~(255 << shift))
94c12cc7	237	: "memory", "cc");
1da177e4 LT	238	return prev >> shift;
	239	case 2:
	240	addr = (unsigned long) ptr;
	241	shift = (2 ^ (addr & 2)) << 3;
	242	addr ^= addr & 2;
	243	asm volatile(
94c12cc7 MS	244	" l %0,0(%4)\n"
	245	"0: nr %0,%5\n"
	246	" lr %1,%0\n"
	247	" or %0,%2\n"
	248	" or %1,%3\n"
	249	" cs %0,%1,0(%4)\n"
	250	" jnl 1f\n"
	251	" xr %1,%0\n"
	252	" nr %1,%5\n"
	253	" jnz 0b\n"
1da177e4 LT	254	"1:"
	255	: "=&d" (prev), "=&d" (tmp)
	256	: "d" (old << shift), "d" (new << shift), "a" (ptr),
	257	"d" (~(65535 << shift))
94c12cc7	258	: "memory", "cc");
1da177e4 LT	259	return prev >> shift;
1da177e4 LT	260	case 4:
94c12cc7 MS	261	asm volatile(
94c12cc7 MS	262	" cs %0,%2,0(%3)\n"
1da177e4	263	: "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
94c12cc7	264	: "memory", "cc");
1da177e4 LT	265	return prev;
	266	#ifdef __s390x__
	267	case 8:
94c12cc7 MS	268	asm volatile(
94c12cc7 MS	269	" csg %0,%2,0(%3)\n"
1da177e4	270	: "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
94c12cc7	271	: "memory", "cc");
1da177e4 LT	272	return prev;
	273	#endif /* __s390x__ */
	274	}
210d3a90 HC	275	__cmpxchg_called_with_bad_pointer();
210d3a90 HC	276	return old;
1da177e4 LT	277	}
	278
	279	/*
	280	* Force strict CPU ordering.
	281	* And yes, this is required on UP too when we're talking
	282	* to devices.
	283	*
	284	* This is very similar to the ppc eieio/sync instruction in that is
	285	* does a checkpoint syncronisation & makes sure that
	286	* all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ).
	287	*/
	288
94c12cc7 MS	289	#define eieio() asm volatile("bcr 15,0" : : : "memory")
94c12cc7 MS	290	#define SYNC_OTHER_CORES(x) eieio()
1da177e4 LT	291	#define mb() eieio()
	292	#define rmb() eieio()
	293	#define wmb() eieio()
	294	#define read_barrier_depends() do { } while(0)
	295	#define smp_mb() mb()
	296	#define smp_rmb() rmb()
	297	#define smp_wmb() wmb()
	298	#define smp_read_barrier_depends() read_barrier_depends()
	299	#define smp_mb__before_clear_bit() smp_mb()
	300	#define smp_mb__after_clear_bit() smp_mb()
	301
	302
	303	#define set_mb(var, value) do { var = value; mb(); } while (0)
1da177e4	304
1da177e4 LT	305	#ifdef __s390x__
1da177e4 LT	306
94c12cc7 MS	307	#define __ctl_load(array, low, high) ({ \
	308	typedef struct { char _[sizeof(array)]; } addrtype; \
	309	asm volatile( \
	310	" lctlg %1,%2,0(%0)\n" \
	311	: : "a" (&array), "i" (low), "i" (high), \
	312	"m" ((addrtype )(array))); \
1da177e4 LT	313	})
1da177e4 LT	314
94c12cc7 MS	315	#define __ctl_store(array, low, high) ({ \
	316	typedef struct { char _[sizeof(array)]; } addrtype; \
	317	asm volatile( \
	318	" stctg %2,%3,0(%1)\n" \
	319	: "=m" ((addrtype )(array)) \
	320	: "a" (&array), "i" (low), "i" (high)); \
1da177e4 LT	321	})
1da177e4 LT	322
1da177e4 LT	323	#else /* __s390x__ */
1da177e4 LT	324
94c12cc7 MS	325	#define __ctl_load(array, low, high) ({ \
	326	typedef struct { char _[sizeof(array)]; } addrtype; \
	327	asm volatile( \
	328	" lctl %1,%2,0(%0)\n" \
	329	: : "a" (&array), "i" (low), "i" (high), \
	330	"m" ((addrtype )(array))); \
	331	})
1da177e4	332
94c12cc7 MS	333	#define __ctl_store(array, low, high) ({ \
	334	typedef struct { char _[sizeof(array)]; } addrtype; \
	335	asm volatile( \
	336	" stctl %2,%3,0(%1)\n" \
	337	: "=m" ((addrtype )(array)) \
	338	: "a" (&array), "i" (low), "i" (high)); \
1da177e4 LT	339	})
1da177e4 LT	340
1da177e4 LT	341	#endif /* __s390x__ */
1da177e4 LT	342
94c12cc7 MS	343	#define __ctl_set_bit(cr, bit) ({ \
	344	unsigned long __dummy; \
	345	__ctl_store(__dummy, cr, cr); \
	346	__dummy \|= 1UL << (bit); \
	347	__ctl_load(__dummy, cr, cr); \
	348	})
	349
	350	#define __ctl_clear_bit(cr, bit) ({ \
	351	unsigned long __dummy; \
	352	__ctl_store(__dummy, cr, cr); \
	353	__dummy &= ~(1UL << (bit)); \
	354	__ctl_load(__dummy, cr, cr); \
	355	})
	356
1f194a4c	357	#include <linux/irqflags.h>
1da177e4	358
fe413013 MD	359	#include <asm-generic/cmpxchg-local.h>
	360
	361	static inline unsigned long __cmpxchg_local(volatile void *ptr,
	362	unsigned long old,
	363	unsigned long new, int size)
	364	{
	365	switch (size) {
	366	case 1:
	367	case 2:
	368	case 4:
	369	#ifdef __s390x__
	370	case 8:
	371	#endif
	372	return __cmpxchg(ptr, old, new, size);
	373	default:
	374	return __cmpxchg_local_generic(ptr, old, new, size);
	375	}
	376
	377	return old;
	378	}
	379
	380	/*
	381	* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
	382	* them available.
	383	*/
	384	#define cmpxchg_local(ptr, o, n) \
	385	((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
	386	(unsigned long)(n), sizeof(*(ptr))))
	387	#ifdef __s390x__
	388	#define cmpxchg64_local(ptr, o, n) \
	389	({ \
	390	BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
	391	cmpxchg_local((ptr), (o), (n)); \
	392	})
	393	#else
	394	#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
	395	#endif
	396
77fa2245 HC	397	/*
	398	* Use to set psw mask except for the first byte which
	399	* won't be changed by this function.
	400	*/
	401	static inline void
	402	__set_psw_mask(unsigned long mask)
	403	{
94c12cc7	404	__load_psw_mask(mask \| (__raw_local_irq_stosm(0x00) & ~(-1UL >> 8)));
77fa2245 HC	405	}
77fa2245 HC	406
c1821c2e GS	407	#define local_mcck_enable() __set_psw_mask(psw_kernel_bits)
c1821c2e GS	408	#define local_mcck_disable() __set_psw_mask(psw_kernel_bits & ~PSW_MASK_MCHECK)
77fa2245	409
7b758389 HC	410	int stfle(unsigned long long *list, int doublewords);
7b758389 HC	411
1da177e4 LT	412	#ifdef CONFIG_SMP
	413
	414	extern void smp_ctl_set_bit(int cr, int bit);
	415	extern void smp_ctl_clear_bit(int cr, int bit);
	416	#define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
	417	#define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
	418
	419	#else
	420
	421	#define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
	422	#define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
	423
	424	#endif /* CONFIG_SMP */
	425
484875b1 HC	426	static inline unsigned int stfl(void)
	427	{
	428	asm volatile(
	429	" .insn s,0xb2b10000,0(0)\n" /* stfl */
	430	"0:\n"
	431	EX_TABLE(0b,0b));
	432	return S390_lowcore.stfl_fac_list;
	433	}
	434
2e5061e4 HC	435	static inline unsigned short stap(void)
	436	{
	437	unsigned short cpu_address;
	438
	439	asm volatile("stap %0" : "=m" (cpu_address));
	440	return cpu_address;
	441	}
	442
1da177e4 LT	443	extern void (_machine_restart)(char command);
	444	extern void (*_machine_halt)(void);
	445	extern void (*_machine_power_off)(void);
	446
	447	#define arch_align_stack(x) (x)
	448
411788ea HC	449	#ifdef CONFIG_TRACE_IRQFLAGS
	450	extern psw_t sysc_restore_trace_psw;
	451	extern psw_t io_restore_trace_psw;
	452	#endif
	453
1da177e4 LT	454	#endif /* __KERNEL__ */
	455
	456	#endif