[linux-2.6-block.git] / include / asm-ppc64 / pci.h

#ifndef __PPC64_PCI_H
#define __PPC64_PCI_H
#ifdef __KERNEL__

/*
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <linux/types.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/dma-mapping.h>

#include <asm/machdep.h>
#include <asm/scatterlist.h>
#include <asm/io.h>
#include <asm/prom.h>

#include <asm-generic/pci-dma-compat.h>

#define PCIBIOS_MIN_IO		0x1000
#define PCIBIOS_MIN_MEM		0x10000000

struct pci_dev;

#ifdef CONFIG_PPC_ISERIES
#define pcibios_scan_all_fns(a, b)	0
#else
extern int pcibios_scan_all_fns(struct pci_bus *bus, int devfn);
#endif

static inline void pcibios_set_master(struct pci_dev *dev)
{
	/* No special bus mastering setup handling */
}

static inline void pcibios_penalize_isa_irq(int irq)
{
	/* We don't do dynamic PCI IRQ allocation */
}

#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
{
	if (ppc_md.pci_get_legacy_ide_irq)
		return ppc_md.pci_get_legacy_ide_irq(dev, channel);
	return channel ? 15 : 14;
}

#define HAVE_ARCH_PCI_MWI 1
static inline int pcibios_prep_mwi(struct pci_dev *dev)
{
	/*
	 * We would like to avoid touching the cacheline size or MWI bit
	 * but we cant do that with the current pcibios_prep_mwi 
	 * interface. pSeries firmware sets the cacheline size (which is not
	 * the cpu cacheline size in all cases) and hardware treats MWI 
	 * the same as memory write. So we dont touch the cacheline size
	 * here and allow the generic code to set the MWI bit.
	 */
	return 0;
}

extern unsigned int pcibios_assign_all_busses(void);

extern struct dma_mapping_ops pci_dma_ops;

/* For DAC DMA, we currently don't support it by default, but
 * we let the platform override this
 */
static inline int pci_dac_dma_supported(struct pci_dev *hwdev,u64 mask)
{
	if (pci_dma_ops.dac_dma_supported)
		return pci_dma_ops.dac_dma_supported(&hwdev->dev, mask);
	return 0;
}

static inline void pci_dma_burst_advice(struct pci_dev *pdev,
					enum pci_dma_burst_strategy *strat,
					unsigned long *strategy_parameter)
{
	unsigned long cacheline_size;
	u8 byte;

	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
	if (byte == 0)
		cacheline_size = 1024;
	else
		cacheline_size = (int) byte * 4;

	*strat = PCI_DMA_BURST_MULTIPLE;
	*strategy_parameter = cacheline_size;
}

extern int pci_domain_nr(struct pci_bus *bus);

/* Decide whether to display the domain number in /proc */
extern int pci_proc_domain(struct pci_bus *bus);

struct vm_area_struct;
/* Map a range of PCI memory or I/O space for a device into user space */
int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state, int write_combine);

/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
#define HAVE_PCI_MMAP	1

/* pci_unmap_{single,page} is not a nop, thus... */
#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)	\
	dma_addr_t ADDR_NAME;
#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)		\
	__u32 LEN_NAME;
#define pci_unmap_addr(PTR, ADDR_NAME)			\
	((PTR)->ADDR_NAME)
#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)		\
	(((PTR)->ADDR_NAME) = (VAL))
#define pci_unmap_len(PTR, LEN_NAME)			\
	((PTR)->LEN_NAME)
#define pci_unmap_len_set(PTR, LEN_NAME, VAL)		\
	(((PTR)->LEN_NAME) = (VAL))

/* The PCI address space does equal the physical memory
 * address space.  The networking and block device layers use
 * this boolean for bounce buffer decisions.
 */
#define PCI_DMA_BUS_IS_PHYS	(0)
	
extern void
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
			struct resource *res);

extern int
unmap_bus_range(struct pci_bus *bus);

extern int
remap_bus_range(struct pci_bus *bus);

extern void
pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus);

extern struct pci_controller *init_phb_dynamic(struct device_node *dn);

extern int pci_read_irq_line(struct pci_dev *dev);

extern void pcibios_add_platform_entries(struct pci_dev *dev);

struct file;
extern pgprot_t	pci_phys_mem_access_prot(struct file *file,
					 unsigned long offset,
					 unsigned long size,
					 pgprot_t prot);

#ifdef CONFIG_PPC_MULTIPLATFORM
#define HAVE_ARCH_PCI_RESOURCE_TO_USER
extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
				 const struct resource *rsrc,
				 u64 *start, u64 *end);
#endif /* CONFIG_PPC_MULTIPLATFORM */


#endif	/* __KERNEL__ */

#endif /* __PPC64_PCI_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef __PPC64_PCI_H
	2	#define __PPC64_PCI_H
	3	#ifdef __KERNEL__
	4
	5	/*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*/
	11
	12	#include <linux/types.h>
	13	#include <linux/slab.h>
	14	#include <linux/string.h>
	15	#include <linux/dma-mapping.h>
	16
	17	#include <asm/machdep.h>
	18	#include <asm/scatterlist.h>
	19	#include <asm/io.h>
	20	#include <asm/prom.h>
	21
	22	#include <asm-generic/pci-dma-compat.h>
	23
	24	#define PCIBIOS_MIN_IO 0x1000
	25	#define PCIBIOS_MIN_MEM 0x10000000
	26
	27	struct pci_dev;
	28
	29	#ifdef CONFIG_PPC_ISERIES
	30	#define pcibios_scan_all_fns(a, b) 0
	31	#else
	32	extern int pcibios_scan_all_fns(struct pci_bus *bus, int devfn);
	33	#endif
	34
	35	static inline void pcibios_set_master(struct pci_dev *dev)
	36	{
	37	/* No special bus mastering setup handling */
	38	}
	39
	40	static inline void pcibios_penalize_isa_irq(int irq)
	41	{
	42	/* We don't do dynamic PCI IRQ allocation */
	43	}
	44
	45	#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
	46	static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
	47	{
	48	if (ppc_md.pci_get_legacy_ide_irq)
	49	return ppc_md.pci_get_legacy_ide_irq(dev, channel);
	50	return channel ? 15 : 14;
	51	}
	52
	53	#define HAVE_ARCH_PCI_MWI 1
	54	static inline int pcibios_prep_mwi(struct pci_dev *dev)
	55	{
	56	/*
	57	* We would like to avoid touching the cacheline size or MWI bit
	58	* but we cant do that with the current pcibios_prep_mwi
	59	* interface. pSeries firmware sets the cacheline size (which is not
	60	* the cpu cacheline size in all cases) and hardware treats MWI
	61	* the same as memory write. So we dont touch the cacheline size
	62	* here and allow the generic code to set the MWI bit.
	63	*/
	64	return 0;
65	}
66
67	extern unsigned int pcibios_assign_all_busses(void);
68
69	extern struct dma_mapping_ops pci_dma_ops;
70
71	/* For DAC DMA, we currently don't support it by default, but
72	* we let the platform override this
73	*/
74	static inline int pci_dac_dma_supported(struct pci_dev *hwdev,u64 mask)
75	{
76	if (pci_dma_ops.dac_dma_supported)
77	return pci_dma_ops.dac_dma_supported(&hwdev->dev, mask);
78	return 0;
79	}
80
e24c2d96 DM	81	static inline void pci_dma_burst_advice(struct pci_dev *pdev,
	82	enum pci_dma_burst_strategy *strat,
	83	unsigned long *strategy_parameter)
	84	{
	85	unsigned long cacheline_size;
	86	u8 byte;
	87
	88	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
	89	if (byte == 0)
	90	cacheline_size = 1024;
	91	else
	92	cacheline_size = (int) byte * 4;
	93
	94	*strat = PCI_DMA_BURST_MULTIPLE;
	95	*strategy_parameter = cacheline_size;
	96	}
	97
1da177e4 LT	98	extern int pci_domain_nr(struct pci_bus *bus);
	99
	100	/* Decide whether to display the domain number in /proc */
	101	extern int pci_proc_domain(struct pci_bus *bus);
	102
	103	struct vm_area_struct;
	104	/* Map a range of PCI memory or I/O space for a device into user space */
	105	int pci_mmap_page_range(struct pci_dev pdev, struct vm_area_struct vma,
	106	enum pci_mmap_state mmap_state, int write_combine);
	107
	108	/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
	109	#define HAVE_PCI_MMAP 1
	110
	111	/* pci_unmap_{single,page} is not a nop, thus... */
	112	#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
	113	dma_addr_t ADDR_NAME;
	114	#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
	115	__u32 LEN_NAME;
	116	#define pci_unmap_addr(PTR, ADDR_NAME) \
	117	((PTR)->ADDR_NAME)
	118	#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
	119	(((PTR)->ADDR_NAME) = (VAL))
	120	#define pci_unmap_len(PTR, LEN_NAME) \
	121	((PTR)->LEN_NAME)
	122	#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
	123	(((PTR)->LEN_NAME) = (VAL))
	124
	125	/* The PCI address space does equal the physical memory
	126	* address space. The networking and block device layers use
	127	* this boolean for bounce buffer decisions.
	128	*/
	129	#define PCI_DMA_BUS_IS_PHYS (0)
	130
	131	extern void
	132	pcibios_resource_to_bus(struct pci_dev dev, struct pci_bus_region region,
	133	struct resource *res);
	134
	135	extern int
	136	unmap_bus_range(struct pci_bus *bus);
	137
	138	extern int
	139	remap_bus_range(struct pci_bus *bus);
	140
	141	extern void
	142	pcibios_fixup_device_resources(struct pci_dev dev, struct pci_bus bus);
	143
	144	extern struct pci_controller init_phb_dynamic(struct device_node dn);
	145
	146	extern int pci_read_irq_line(struct pci_dev *dev);
	147
	148	extern void pcibios_add_platform_entries(struct pci_dev *dev);
	149
	150	struct file;
	151	extern pgprot_t pci_phys_mem_access_prot(struct file *file,
	152	unsigned long offset,
	153	unsigned long size,
	154	pgprot_t prot);
	155
2311b1f2 ME	156	#ifdef CONFIG_PPC_MULTIPLATFORM
	157	#define HAVE_ARCH_PCI_RESOURCE_TO_USER
	158	extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
	159	const struct resource *rsrc,
	160	u64 start, u64 end);
	161	#endif /* CONFIG_PPC_MULTIPLATFORM */
	162
1da177e4 LT	163
	164	#endif /* __KERNEL__ */
	165
	166	#endif /* __PPC64_PCI_H */