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1da177e4 LT |
1 | #ifndef __PPC64_ELF_H |
2 | #define __PPC64_ELF_H | |
3 | ||
4 | #include <asm/types.h> | |
5 | #include <asm/ptrace.h> | |
6 | #include <asm/cputable.h> | |
7 | ||
8 | /* PowerPC relocations defined by the ABIs */ | |
9 | #define R_PPC_NONE 0 | |
10 | #define R_PPC_ADDR32 1 /* 32bit absolute address */ | |
11 | #define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ | |
12 | #define R_PPC_ADDR16 3 /* 16bit absolute address */ | |
13 | #define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ | |
14 | #define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ | |
15 | #define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ | |
16 | #define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ | |
17 | #define R_PPC_ADDR14_BRTAKEN 8 | |
18 | #define R_PPC_ADDR14_BRNTAKEN 9 | |
19 | #define R_PPC_REL24 10 /* PC relative 26 bit */ | |
20 | #define R_PPC_REL14 11 /* PC relative 16 bit */ | |
21 | #define R_PPC_REL14_BRTAKEN 12 | |
22 | #define R_PPC_REL14_BRNTAKEN 13 | |
23 | #define R_PPC_GOT16 14 | |
24 | #define R_PPC_GOT16_LO 15 | |
25 | #define R_PPC_GOT16_HI 16 | |
26 | #define R_PPC_GOT16_HA 17 | |
27 | #define R_PPC_PLTREL24 18 | |
28 | #define R_PPC_COPY 19 | |
29 | #define R_PPC_GLOB_DAT 20 | |
30 | #define R_PPC_JMP_SLOT 21 | |
31 | #define R_PPC_RELATIVE 22 | |
32 | #define R_PPC_LOCAL24PC 23 | |
33 | #define R_PPC_UADDR32 24 | |
34 | #define R_PPC_UADDR16 25 | |
35 | #define R_PPC_REL32 26 | |
36 | #define R_PPC_PLT32 27 | |
37 | #define R_PPC_PLTREL32 28 | |
38 | #define R_PPC_PLT16_LO 29 | |
39 | #define R_PPC_PLT16_HI 30 | |
40 | #define R_PPC_PLT16_HA 31 | |
41 | #define R_PPC_SDAREL16 32 | |
42 | #define R_PPC_SECTOFF 33 | |
43 | #define R_PPC_SECTOFF_LO 34 | |
44 | #define R_PPC_SECTOFF_HI 35 | |
45 | #define R_PPC_SECTOFF_HA 36 | |
46 | ||
47 | /* PowerPC relocations defined for the TLS access ABI. */ | |
48 | #define R_PPC_TLS 67 /* none (sym+add)@tls */ | |
49 | #define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ | |
50 | #define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ | |
51 | #define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ | |
52 | #define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ | |
53 | #define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ | |
54 | #define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ | |
55 | #define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ | |
56 | #define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ | |
57 | #define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ | |
58 | #define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ | |
59 | #define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ | |
60 | #define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ | |
61 | #define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ | |
62 | #define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ | |
63 | #define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ | |
64 | #define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ | |
65 | #define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ | |
66 | #define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ | |
67 | #define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ | |
68 | #define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ | |
69 | #define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ | |
70 | #define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ | |
71 | #define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ | |
72 | #define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ | |
73 | #define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ | |
74 | #define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ | |
75 | #define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ | |
76 | ||
77 | /* Keep this the last entry. */ | |
78 | #define R_PPC_NUM 95 | |
79 | ||
80 | /* | |
81 | * ELF register definitions.. | |
82 | * | |
83 | * This program is free software; you can redistribute it and/or | |
84 | * modify it under the terms of the GNU General Public License | |
85 | * as published by the Free Software Foundation; either version | |
86 | * 2 of the License, or (at your option) any later version. | |
87 | */ | |
88 | #include <asm/ptrace.h> | |
89 | ||
90 | #define ELF_NGREG 48 /* includes nip, msr, lr, etc. */ | |
91 | #define ELF_NFPREG 33 /* includes fpscr */ | |
92 | #define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */ | |
93 | #define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */ | |
94 | ||
95 | typedef unsigned long elf_greg_t64; | |
96 | typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG]; | |
97 | ||
98 | typedef unsigned int elf_greg_t32; | |
99 | typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG]; | |
100 | ||
101 | /* | |
102 | * These are used to set parameters in the core dumps. | |
103 | */ | |
104 | #ifndef ELF_ARCH | |
105 | # define ELF_ARCH EM_PPC64 | |
106 | # define ELF_CLASS ELFCLASS64 | |
107 | # define ELF_DATA ELFDATA2MSB | |
108 | typedef elf_greg_t64 elf_greg_t; | |
109 | typedef elf_gregset_t64 elf_gregset_t; | |
110 | # define elf_addr_t unsigned long | |
111 | #else | |
112 | /* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */ | |
113 | typedef elf_greg_t32 elf_greg_t; | |
114 | typedef elf_gregset_t32 elf_gregset_t; | |
115 | # define elf_addr_t u32 | |
116 | #endif | |
117 | ||
118 | typedef double elf_fpreg_t; | |
119 | typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; | |
120 | ||
121 | /* Altivec registers */ | |
122 | /* | |
123 | * The entries with indexes 0-31 contain the corresponding vector registers. | |
124 | * The entry with index 32 contains the vscr as the last word (offset 12) | |
125 | * within the quadword. This allows the vscr to be stored as either a | |
126 | * quadword (since it must be copied via a vector register to/from storage) | |
127 | * or as a word. The entry with index 33 contains the vrsave as the first | |
128 | * word (offset 0) within the quadword. | |
129 | * | |
130 | * This definition of the VMX state is compatible with the current PPC32 | |
131 | * ptrace interface. This allows signal handling and ptrace to use the same | |
132 | * structures. This also simplifies the implementation of a bi-arch | |
133 | * (combined (32- and 64-bit) gdb. | |
134 | * | |
135 | * Note that it's _not_ compatible with 32 bits ucontext which stuffs the | |
136 | * vrsave along with vscr and so only uses 33 vectors for the register set | |
137 | */ | |
138 | typedef __vector128 elf_vrreg_t; | |
139 | typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG]; | |
140 | typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32]; | |
141 | ||
142 | /* | |
143 | * This is used to ensure we don't load something for the wrong architecture. | |
144 | */ | |
145 | #define elf_check_arch(x) ((x)->e_machine == ELF_ARCH) | |
146 | ||
147 | #define USE_ELF_CORE_DUMP | |
148 | #define ELF_EXEC_PAGESIZE 4096 | |
149 | ||
150 | /* This is the location that an ET_DYN program is loaded if exec'ed. Typical | |
151 | use of this is to invoke "./ld.so someprog" to test out a new version of | |
152 | the loader. We need to make sure that it is out of the way of the program | |
153 | that it will "exec", and that there is sufficient room for the brk. */ | |
154 | ||
155 | #define ELF_ET_DYN_BASE (0x08000000) | |
156 | ||
157 | #ifdef __KERNEL__ | |
158 | ||
159 | /* Common routine for both 32-bit and 64-bit processes */ | |
160 | static inline void ppc64_elf_core_copy_regs(elf_gregset_t elf_regs, | |
161 | struct pt_regs *regs) | |
162 | { | |
163 | int i; | |
164 | int gprs = sizeof(struct pt_regs)/sizeof(elf_greg_t64); | |
165 | ||
166 | if (gprs > ELF_NGREG) | |
167 | gprs = ELF_NGREG; | |
168 | ||
169 | for (i=0; i < gprs; i++) | |
170 | elf_regs[i] = (elf_greg_t)((elf_greg_t64 *)regs)[i]; | |
171 | } | |
172 | #define ELF_CORE_COPY_REGS(gregs, regs) ppc64_elf_core_copy_regs(gregs, regs); | |
173 | ||
174 | static inline int dump_task_regs(struct task_struct *tsk, | |
175 | elf_gregset_t *elf_regs) | |
176 | { | |
177 | struct pt_regs *regs = tsk->thread.regs; | |
178 | if (regs) | |
179 | ppc64_elf_core_copy_regs(*elf_regs, regs); | |
180 | ||
181 | return 1; | |
182 | } | |
183 | #define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs) | |
184 | ||
185 | extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); | |
186 | #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs) | |
187 | ||
188 | /* XXX Should we define the XFPREGS using altivec ??? */ | |
189 | ||
190 | #endif | |
191 | ||
192 | /* This yields a mask that user programs can use to figure out what | |
193 | instruction set this cpu supports. This could be done in userspace, | |
194 | but it's not easy, and we've already done it here. */ | |
195 | ||
196 | #define ELF_HWCAP (cur_cpu_spec->cpu_user_features) | |
197 | ||
198 | /* This yields a string that ld.so will use to load implementation | |
199 | specific libraries for optimization. This is more specific in | |
200 | intent than poking at uname or /proc/cpuinfo. | |
201 | ||
202 | For the moment, we have only optimizations for the Intel generations, | |
203 | but that could change... */ | |
204 | ||
205 | #define ELF_PLATFORM (NULL) | |
206 | ||
207 | #define ELF_PLAT_INIT(_r, load_addr) do { \ | |
208 | memset(_r->gpr, 0, sizeof(_r->gpr)); \ | |
209 | _r->ctr = _r->link = _r->xer = _r->ccr = 0; \ | |
210 | _r->gpr[2] = load_addr; \ | |
211 | } while (0) | |
212 | ||
213 | #ifdef __KERNEL__ | |
214 | #define SET_PERSONALITY(ex, ibcs2) \ | |
215 | do { \ | |
216 | unsigned long new_flags = 0; \ | |
217 | if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ | |
218 | new_flags = _TIF_32BIT; \ | |
219 | if ((current_thread_info()->flags & _TIF_32BIT) \ | |
220 | != new_flags) \ | |
221 | set_thread_flag(TIF_ABI_PENDING); \ | |
222 | else \ | |
223 | clear_thread_flag(TIF_ABI_PENDING); \ | |
224 | if (ibcs2) \ | |
225 | set_personality(PER_SVR4); \ | |
226 | else if (current->personality != PER_LINUX32) \ | |
227 | set_personality(PER_LINUX); \ | |
228 | } while (0) | |
229 | ||
230 | /* | |
231 | * An executable for which elf_read_implies_exec() returns TRUE will | |
a2f95a5a AB |
232 | * have the READ_IMPLIES_EXEC personality flag set automatically. This |
233 | * is only required to work around bugs in old 32bit toolchains. Since | |
234 | * the 64bit ABI has never had these issues dont enable the workaround | |
235 | * even if we have an executable stack. | |
1da177e4 | 236 | */ |
a2f95a5a AB |
237 | #define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \ |
238 | (exec_stk != EXSTACK_DISABLE_X) : 0) | |
1da177e4 LT |
239 | |
240 | #endif | |
241 | ||
242 | /* | |
243 | * We need to put in some extra aux table entries to tell glibc what | |
244 | * the cache block size is, so it can use the dcbz instruction safely. | |
245 | */ | |
246 | #define AT_DCACHEBSIZE 19 | |
247 | #define AT_ICACHEBSIZE 20 | |
248 | #define AT_UCACHEBSIZE 21 | |
249 | /* A special ignored type value for PPC, for glibc compatibility. */ | |
250 | #define AT_IGNOREPPC 22 | |
251 | ||
252 | /* The vDSO location. We have to use the same value as x86 for glibc's | |
253 | * sake :-) | |
254 | */ | |
255 | #define AT_SYSINFO_EHDR 33 | |
256 | ||
257 | extern int dcache_bsize; | |
258 | extern int icache_bsize; | |
259 | extern int ucache_bsize; | |
260 | ||
261 | /* We do have an arch_setup_additional_pages for vDSO matters */ | |
262 | #define ARCH_HAS_SETUP_ADDITIONAL_PAGES | |
263 | struct linux_binprm; | |
264 | extern int arch_setup_additional_pages(struct linux_binprm *bprm, int executable_stack); | |
265 | ||
266 | /* | |
267 | * The requirements here are: | |
268 | * - keep the final alignment of sp (sp & 0xf) | |
269 | * - make sure the 32-bit value at the first 16 byte aligned position of | |
270 | * AUXV is greater than 16 for glibc compatibility. | |
271 | * AT_IGNOREPPC is used for that. | |
272 | * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC, | |
273 | * even if DLINFO_ARCH_ITEMS goes to zero or is undefined. | |
274 | */ | |
275 | #define ARCH_DLINFO \ | |
276 | do { \ | |
277 | /* Handle glibc compatibility. */ \ | |
278 | NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \ | |
279 | NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \ | |
280 | /* Cache size items */ \ | |
281 | NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \ | |
282 | NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \ | |
283 | NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \ | |
284 | /* vDSO base */ \ | |
285 | NEW_AUX_ENT(AT_SYSINFO_EHDR, current->thread.vdso_base); \ | |
286 | } while (0) | |
287 | ||
288 | /* PowerPC64 relocations defined by the ABIs */ | |
289 | #define R_PPC64_NONE R_PPC_NONE | |
290 | #define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address. */ | |
291 | #define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned. */ | |
292 | #define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address. */ | |
293 | #define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address. */ | |
294 | #define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */ | |
295 | #define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ | |
296 | #define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned. */ | |
297 | #define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN | |
298 | #define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN | |
299 | #define R_PPC64_REL24 R_PPC_REL24 /* PC relative 26 bit, word aligned. */ | |
300 | #define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit. */ | |
301 | #define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN | |
302 | #define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN | |
303 | #define R_PPC64_GOT16 R_PPC_GOT16 | |
304 | #define R_PPC64_GOT16_LO R_PPC_GOT16_LO | |
305 | #define R_PPC64_GOT16_HI R_PPC_GOT16_HI | |
306 | #define R_PPC64_GOT16_HA R_PPC_GOT16_HA | |
307 | ||
308 | #define R_PPC64_COPY R_PPC_COPY | |
309 | #define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT | |
310 | #define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT | |
311 | #define R_PPC64_RELATIVE R_PPC_RELATIVE | |
312 | ||
313 | #define R_PPC64_UADDR32 R_PPC_UADDR32 | |
314 | #define R_PPC64_UADDR16 R_PPC_UADDR16 | |
315 | #define R_PPC64_REL32 R_PPC_REL32 | |
316 | #define R_PPC64_PLT32 R_PPC_PLT32 | |
317 | #define R_PPC64_PLTREL32 R_PPC_PLTREL32 | |
318 | #define R_PPC64_PLT16_LO R_PPC_PLT16_LO | |
319 | #define R_PPC64_PLT16_HI R_PPC_PLT16_HI | |
320 | #define R_PPC64_PLT16_HA R_PPC_PLT16_HA | |
321 | ||
322 | #define R_PPC64_SECTOFF R_PPC_SECTOFF | |
323 | #define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO | |
324 | #define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI | |
325 | #define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA | |
326 | #define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2. */ | |
327 | #define R_PPC64_ADDR64 38 /* doubleword64 S + A. */ | |
328 | #define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A). */ | |
329 | #define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A). */ | |
330 | #define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A). */ | |
331 | #define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A). */ | |
332 | #define R_PPC64_UADDR64 43 /* doubleword64 S + A. */ | |
333 | #define R_PPC64_REL64 44 /* doubleword64 S + A - P. */ | |
334 | #define R_PPC64_PLT64 45 /* doubleword64 L + A. */ | |
335 | #define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P. */ | |
336 | #define R_PPC64_TOC16 47 /* half16* S + A - .TOC. */ | |
337 | #define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.). */ | |
338 | #define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.). */ | |
339 | #define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.). */ | |
340 | #define R_PPC64_TOC 51 /* doubleword64 .TOC. */ | |
341 | #define R_PPC64_PLTGOT16 52 /* half16* M + A. */ | |
342 | #define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A). */ | |
343 | #define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A). */ | |
344 | #define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A). */ | |
345 | ||
346 | #define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2. */ | |
347 | #define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2. */ | |
348 | #define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2. */ | |
349 | #define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2. */ | |
350 | #define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2. */ | |
351 | #define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2. */ | |
352 | #define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2. */ | |
353 | #define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2. */ | |
354 | #define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2. */ | |
355 | #define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2. */ | |
356 | #define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2. */ | |
357 | ||
358 | /* PowerPC64 relocations defined for the TLS access ABI. */ | |
359 | #define R_PPC64_TLS 67 /* none (sym+add)@tls */ | |
360 | #define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ | |
361 | #define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ | |
362 | #define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ | |
363 | #define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ | |
364 | #define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ | |
365 | #define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ | |
366 | #define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ | |
367 | #define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ | |
368 | #define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ | |
369 | #define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ | |
370 | #define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ | |
371 | #define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ | |
372 | #define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ | |
373 | #define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ | |
374 | #define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ | |
375 | #define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ | |
376 | #define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ | |
377 | #define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ | |
378 | #define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ | |
379 | #define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ | |
380 | #define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ | |
381 | #define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ | |
382 | #define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ | |
383 | #define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ | |
384 | #define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ | |
385 | #define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ | |
386 | #define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ | |
387 | #define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ | |
388 | #define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ | |
389 | #define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ | |
390 | #define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ | |
391 | #define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ | |
392 | #define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ | |
393 | #define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ | |
394 | #define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ | |
395 | #define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ | |
396 | #define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ | |
397 | #define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ | |
398 | #define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ | |
399 | ||
400 | /* Keep this the last entry. */ | |
401 | #define R_PPC64_NUM 107 | |
402 | ||
403 | #endif /* __PPC64_ELF_H */ |