[linux-2.6-block.git] / include / asm-ppc / pci.h

#ifndef __PPC_PCI_H
#define __PPC_PCI_H
#ifdef __KERNEL__

#include <linux/types.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <asm/scatterlist.h>
#include <asm/io.h>
#include <asm/pci-bridge.h>
#include <asm-generic/pci-dma-compat.h>

struct pci_dev;

/* Values for the `which' argument to sys_pciconfig_iobase syscall.  */
#define IOBASE_BRIDGE_NUMBER	0
#define IOBASE_MEMORY		1
#define IOBASE_IO		2
#define IOBASE_ISA_IO		3
#define IOBASE_ISA_MEM		4

/*
 * Set this to 1 if you want the kernel to re-assign all PCI
 * bus numbers
 */
extern int pci_assign_all_buses;

#define pcibios_assign_all_busses()	(pci_assign_all_buses)
#define pcibios_scan_all_fns(a, b)	0

#define PCIBIOS_MIN_IO		0x1000
#define PCIBIOS_MIN_MEM		0x10000000

extern inline void pcibios_set_master(struct pci_dev *dev)
{
	/* No special bus mastering setup handling */
}

extern inline void pcibios_penalize_isa_irq(int irq, int active)
{
	/* We don't do dynamic PCI IRQ allocation */
}

extern unsigned long pci_resource_to_bus(struct pci_dev *pdev, struct resource *res);

/*
 * The PCI bus bridge can translate addresses issued by the processor(s)
 * into a different address on the PCI bus.  On 32-bit cpus, we assume
 * this mapping is 1-1, but on 64-bit systems it often isn't.
 *
 * Obsolete ! Drivers should now use pci_resource_to_bus
 */
extern unsigned long phys_to_bus(unsigned long pa);
extern unsigned long pci_phys_to_bus(unsigned long pa, int busnr);
extern unsigned long pci_bus_to_phys(unsigned int ba, int busnr);

/* The PCI address space does equal the physical memory
 * address space.  The networking and block device layers use
 * this boolean for bounce buffer decisions.
 */
#define PCI_DMA_BUS_IS_PHYS     (1)

#ifdef CONFIG_NOT_COHERENT_CACHE
/*
 * pci_unmap_{page,single} are NOPs but pci_dma_sync_single_for_cpu()
 * and so on are not, so...
 */

#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)	\
	dma_addr_t ADDR_NAME;
#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)		\
	__u32 LEN_NAME;
#define pci_unmap_addr(PTR, ADDR_NAME)			\
	((PTR)->ADDR_NAME)
#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)		\
	(((PTR)->ADDR_NAME) = (VAL))
#define pci_unmap_len(PTR, LEN_NAME)			\
	((PTR)->LEN_NAME)
#define pci_unmap_len_set(PTR, LEN_NAME, VAL)		\
	(((PTR)->LEN_NAME) = (VAL))

#else /* coherent */

/* pci_unmap_{page,single} is a nop so... */
#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
#define pci_unmap_addr(PTR, ADDR_NAME)		(0)
#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)	do { } while (0)
#define pci_unmap_len(PTR, LEN_NAME)		(0)
#define pci_unmap_len_set(PTR, LEN_NAME, VAL)	do { } while (0)

#endif /* CONFIG_NOT_COHERENT_CACHE */

#ifdef CONFIG_PCI
static inline void pci_dma_burst_advice(struct pci_dev *pdev,
					enum pci_dma_burst_strategy *strat,
					unsigned long *strategy_parameter)
{
	*strat = PCI_DMA_BURST_INFINITY;
	*strategy_parameter = ~0UL;
}
#endif

/*
 * At present there are very few 32-bit PPC machines that can have
 * memory above the 4GB point, and we don't support that.
 */
#define pci_dac_dma_supported(pci_dev, mask)	(0)

/* Return the index of the PCI controller for device PDEV. */
#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index

/* Set the name of the bus as it appears in /proc/bus/pci */
static inline int pci_proc_domain(struct pci_bus *bus)
{
	return 0;
}

/* Map a range of PCI memory or I/O space for a device into user space */
int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
			enum pci_mmap_state mmap_state, int write_combine);

/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
#define HAVE_PCI_MMAP	1

extern void
pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
			struct resource *res);

extern void
pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
			struct pci_bus_region *region);

static inline struct resource *
pcibios_select_root(struct pci_dev *pdev, struct resource *res)
{
	struct resource *root = NULL;

	if (res->flags & IORESOURCE_IO)
		root = &ioport_resource;
	if (res->flags & IORESOURCE_MEM)
		root = &iomem_resource;

	return root;
}

extern void pcibios_add_platform_entries(struct pci_dev *dev);

struct file;
extern pgprot_t	pci_phys_mem_access_prot(struct file *file,
					 unsigned long pfn,
					 unsigned long size,
					 pgprot_t prot);

#define HAVE_ARCH_PCI_RESOURCE_TO_USER
extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
				 const struct resource *rsrc,
				 resource_size_t *start, resource_size_t *end);


#endif	/* __KERNEL__ */

#endif /* __PPC_PCI_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef __PPC_PCI_H
	2	#define __PPC_PCI_H
	3	#ifdef __KERNEL__
	4
	5	#include <linux/types.h>
	6	#include <linux/slab.h>
	7	#include <linux/string.h>
	8	#include <linux/mm.h>
	9	#include <asm/scatterlist.h>
	10	#include <asm/io.h>
	11	#include <asm/pci-bridge.h>
	12	#include <asm-generic/pci-dma-compat.h>
	13
	14	struct pci_dev;
	15
	16	/* Values for the `which' argument to sys_pciconfig_iobase syscall. */
	17	#define IOBASE_BRIDGE_NUMBER 0
	18	#define IOBASE_MEMORY 1
	19	#define IOBASE_IO 2
	20	#define IOBASE_ISA_IO 3
	21	#define IOBASE_ISA_MEM 4
	22
	23	/*
	24	* Set this to 1 if you want the kernel to re-assign all PCI
	25	* bus numbers
	26	*/
399fe2bd	27	extern int pci_assign_all_buses;
1da177e4	28
399fe2bd	29	#define pcibios_assign_all_busses() (pci_assign_all_buses)
1da177e4 LT	30	#define pcibios_scan_all_fns(a, b) 0
	31
	32	#define PCIBIOS_MIN_IO 0x1000
	33	#define PCIBIOS_MIN_MEM 0x10000000
	34
	35	extern inline void pcibios_set_master(struct pci_dev *dev)
	36	{
	37	/* No special bus mastering setup handling */
	38	}
	39
c9c3e457	40	extern inline void pcibios_penalize_isa_irq(int irq, int active)
1da177e4 LT	41	{
	42	/* We don't do dynamic PCI IRQ allocation */
	43	}
	44
	45	extern unsigned long pci_resource_to_bus(struct pci_dev pdev, struct resource res);
	46
	47	/*
	48	* The PCI bus bridge can translate addresses issued by the processor(s)
	49	* into a different address on the PCI bus. On 32-bit cpus, we assume
	50	* this mapping is 1-1, but on 64-bit systems it often isn't.
	51	*
	52	* Obsolete ! Drivers should now use pci_resource_to_bus
	53	*/
	54	extern unsigned long phys_to_bus(unsigned long pa);
	55	extern unsigned long pci_phys_to_bus(unsigned long pa, int busnr);
	56	extern unsigned long pci_bus_to_phys(unsigned int ba, int busnr);
	57
	58	/* The PCI address space does equal the physical memory
	59	* address space. The networking and block device layers use
	60	* this boolean for bounce buffer decisions.
	61	*/
	62	#define PCI_DMA_BUS_IS_PHYS (1)
	63
1d4454e7 RD	64	#ifdef CONFIG_NOT_COHERENT_CACHE
	65	/*
	66	* pci_unmap_{page,single} are NOPs but pci_dma_sync_single_for_cpu()
	67	* and so on are not, so...
	68	*/
	69
	70	#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
	71	dma_addr_t ADDR_NAME;
	72	#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
	73	__u32 LEN_NAME;
	74	#define pci_unmap_addr(PTR, ADDR_NAME) \
	75	((PTR)->ADDR_NAME)
	76	#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
	77	(((PTR)->ADDR_NAME) = (VAL))
	78	#define pci_unmap_len(PTR, LEN_NAME) \
	79	((PTR)->LEN_NAME)
	80	#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
	81	(((PTR)->LEN_NAME) = (VAL))
	82
	83	#else /* coherent */
	84
1da177e4 LT	85	/* pci_unmap_{page,single} is a nop so... */
	86	#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
	87	#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
	88	#define pci_unmap_addr(PTR, ADDR_NAME) (0)
	89	#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
	90	#define pci_unmap_len(PTR, LEN_NAME) (0)
	91	#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
	92
1d4454e7 RD	93	#endif /* CONFIG_NOT_COHERENT_CACHE */
1d4454e7 RD	94
bb4a61b6	95	#ifdef CONFIG_PCI
e24c2d96 DM	96	static inline void pci_dma_burst_advice(struct pci_dev *pdev,
	97	enum pci_dma_burst_strategy *strat,
	98	unsigned long *strategy_parameter)
	99	{
	100	*strat = PCI_DMA_BURST_INFINITY;
	101	*strategy_parameter = ~0UL;
	102	}
bb4a61b6	103	#endif
e24c2d96	104
1da177e4 LT	105	/*
	106	* At present there are very few 32-bit PPC machines that can have
	107	* memory above the 4GB point, and we don't support that.
	108	*/
	109	#define pci_dac_dma_supported(pci_dev, mask) (0)
	110
	111	/* Return the index of the PCI controller for device PDEV. */
	112	#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
	113
	114	/* Set the name of the bus as it appears in /proc/bus/pci */
	115	static inline int pci_proc_domain(struct pci_bus *bus)
	116	{
	117	return 0;
	118	}
	119
	120	/* Map a range of PCI memory or I/O space for a device into user space */
	121	int pci_mmap_page_range(struct pci_dev pdev, struct vm_area_struct vma,
	122	enum pci_mmap_state mmap_state, int write_combine);
	123
	124	/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
	125	#define HAVE_PCI_MMAP 1
	126
	127	extern void
	128	pcibios_resource_to_bus(struct pci_dev dev, struct pci_bus_region region,
	129	struct resource *res);
	130
43c34735 DB	131	extern void
	132	pcibios_bus_to_resource(struct pci_dev dev, struct resource res,
	133	struct pci_bus_region *region);
	134
085ae41f DM	135	static inline struct resource *
	136	pcibios_select_root(struct pci_dev pdev, struct resource res)
	137	{
	138	struct resource *root = NULL;
	139
	140	if (res->flags & IORESOURCE_IO)
	141	root = &ioport_resource;
	142	if (res->flags & IORESOURCE_MEM)
	143	root = &iomem_resource;
	144
	145	return root;
	146	}
	147
1da177e4 LT	148	extern void pcibios_add_platform_entries(struct pci_dev *dev);
	149
	150	struct file;
	151	extern pgprot_t pci_phys_mem_access_prot(struct file *file,
8b150478	152	unsigned long pfn,
1da177e4 LT	153	unsigned long size,
	154	pgprot_t prot);
	155
2311b1f2 ME	156	#define HAVE_ARCH_PCI_RESOURCE_TO_USER
	157	extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
	158	const struct resource *rsrc,
e31dd6e4	159	resource_size_t start, resource_size_t end);
2311b1f2 ME	160
2311b1f2 ME	161
1da177e4 LT	162	#endif /* __KERNEL__ */
	163
	164	#endif /* __PPC_PCI_H */