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1da177e4 LT |
1 | #ifdef __KERNEL__ |
2 | #ifndef __PPC_MMU_CONTEXT_H | |
3 | #define __PPC_MMU_CONTEXT_H | |
4 | ||
1da177e4 LT |
5 | #include <asm/atomic.h> |
6 | #include <asm/bitops.h> | |
7 | #include <asm/mmu.h> | |
8 | #include <asm/cputable.h> | |
9 | ||
10 | /* | |
11 | * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs | |
12 | * (virtual segment identifiers) for each context. Although the | |
13 | * hardware supports 24-bit VSIDs, and thus >1 million contexts, | |
14 | * we only use 32,768 of them. That is ample, since there can be | |
15 | * at most around 30,000 tasks in the system anyway, and it means | |
16 | * that we can use a bitmap to indicate which contexts are in use. | |
17 | * Using a bitmap means that we entirely avoid all of the problems | |
18 | * that we used to have when the context number overflowed, | |
19 | * particularly on SMP systems. | |
20 | * -- paulus. | |
21 | */ | |
22 | ||
23 | /* | |
24 | * This function defines the mapping from contexts to VSIDs (virtual | |
25 | * segment IDs). We use a skew on both the context and the high 4 bits | |
26 | * of the 32-bit virtual address (the "effective segment ID") in order | |
27 | * to spread out the entries in the MMU hash table. Note, if this | |
28 | * function is changed then arch/ppc/mm/hashtable.S will have to be | |
29 | * changed to correspond. | |
30 | */ | |
31 | #define CTX_TO_VSID(ctx, va) (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \ | |
32 | & 0xffffff) | |
33 | ||
34 | /* | |
35 | The MPC8xx has only 16 contexts. We rotate through them on each | |
36 | task switch. A better way would be to keep track of tasks that | |
37 | own contexts, and implement an LRU usage. That way very active | |
38 | tasks don't always have to pay the TLB reload overhead. The | |
39 | kernel pages are mapped shared, so the kernel can run on behalf | |
40 | of any task that makes a kernel entry. Shared does not mean they | |
41 | are not protected, just that the ASID comparison is not performed. | |
42 | -- Dan | |
43 | ||
44 | The IBM4xx has 256 contexts, so we can just rotate through these | |
45 | as a way of "switching" contexts. If the TID of the TLB is zero, | |
46 | the PID/TID comparison is disabled, so we can use a TID of zero | |
47 | to represent all kernel pages as shared among all contexts. | |
48 | -- Dan | |
49 | */ | |
50 | ||
51 | static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) | |
52 | { | |
53 | } | |
54 | ||
55 | #ifdef CONFIG_8xx | |
56 | #define NO_CONTEXT 16 | |
57 | #define LAST_CONTEXT 15 | |
58 | #define FIRST_CONTEXT 0 | |
59 | ||
60 | #elif defined(CONFIG_4xx) | |
61 | #define NO_CONTEXT 256 | |
62 | #define LAST_CONTEXT 255 | |
63 | #define FIRST_CONTEXT 1 | |
64 | ||
33d9e9b5 | 65 | #elif defined(CONFIG_E200) || defined(CONFIG_E500) |
1da177e4 LT |
66 | #define NO_CONTEXT 256 |
67 | #define LAST_CONTEXT 255 | |
68 | #define FIRST_CONTEXT 1 | |
69 | ||
70 | #else | |
71 | ||
72 | /* PPC 6xx, 7xx CPUs */ | |
6218a761 | 73 | #define NO_CONTEXT ((unsigned long) -1) |
1da177e4 LT |
74 | #define LAST_CONTEXT 32767 |
75 | #define FIRST_CONTEXT 1 | |
76 | #endif | |
77 | ||
78 | /* | |
79 | * Set the current MMU context. | |
80 | * On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by | |
81 | * loading up the segment registers for the user part of the address space. | |
82 | * | |
83 | * Since the PGD is immediately available, it is much faster to simply | |
84 | * pass this along as a second parameter, which is required for 8xx and | |
85 | * can be used for debugging on all processors (if you happen to have | |
86 | * an Abatron). | |
87 | */ | |
6218a761 | 88 | extern void set_context(unsigned long contextid, pgd_t *pgd); |
1da177e4 LT |
89 | |
90 | /* | |
91 | * Bitmap of contexts in use. | |
92 | * The size of this bitmap is LAST_CONTEXT + 1 bits. | |
93 | */ | |
94 | extern unsigned long context_map[]; | |
95 | ||
96 | /* | |
97 | * This caches the next context number that we expect to be free. | |
98 | * Its use is an optimization only, we can't rely on this context | |
99 | * number to be free, but it usually will be. | |
100 | */ | |
6218a761 | 101 | extern unsigned long next_mmu_context; |
1da177e4 LT |
102 | |
103 | /* | |
104 | * If we don't have sufficient contexts to give one to every task | |
105 | * that could be in the system, we need to be able to steal contexts. | |
106 | * These variables support that. | |
107 | */ | |
108 | #if LAST_CONTEXT < 30000 | |
109 | #define FEW_CONTEXTS 1 | |
110 | extern atomic_t nr_free_contexts; | |
111 | extern struct mm_struct *context_mm[LAST_CONTEXT+1]; | |
112 | extern void steal_context(void); | |
113 | #endif | |
114 | ||
115 | /* | |
116 | * Get a new mmu context for the address space described by `mm'. | |
117 | */ | |
118 | static inline void get_mmu_context(struct mm_struct *mm) | |
119 | { | |
6218a761 | 120 | unsigned long ctx; |
1da177e4 | 121 | |
6218a761 | 122 | if (mm->context.id != NO_CONTEXT) |
1da177e4 LT |
123 | return; |
124 | #ifdef FEW_CONTEXTS | |
125 | while (atomic_dec_if_positive(&nr_free_contexts) < 0) | |
126 | steal_context(); | |
127 | #endif | |
128 | ctx = next_mmu_context; | |
129 | while (test_and_set_bit(ctx, context_map)) { | |
130 | ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx); | |
131 | if (ctx > LAST_CONTEXT) | |
132 | ctx = 0; | |
133 | } | |
134 | next_mmu_context = (ctx + 1) & LAST_CONTEXT; | |
6218a761 | 135 | mm->context.id = ctx; |
1da177e4 LT |
136 | #ifdef FEW_CONTEXTS |
137 | context_mm[ctx] = mm; | |
138 | #endif | |
139 | } | |
140 | ||
141 | /* | |
142 | * Set up the context for a new address space. | |
143 | */ | |
6218a761 PM |
144 | static inline int init_new_context(struct task_struct *t, struct mm_struct *mm) |
145 | { | |
146 | mm->context.id = NO_CONTEXT; | |
147 | mm->context.vdso_base = 0; | |
148 | return 0; | |
149 | } | |
1da177e4 LT |
150 | |
151 | /* | |
152 | * We're finished using the context for an address space. | |
153 | */ | |
154 | static inline void destroy_context(struct mm_struct *mm) | |
155 | { | |
ddca3b80 | 156 | preempt_disable(); |
6218a761 PM |
157 | if (mm->context.id != NO_CONTEXT) { |
158 | clear_bit(mm->context.id, context_map); | |
159 | mm->context.id = NO_CONTEXT; | |
1da177e4 LT |
160 | #ifdef FEW_CONTEXTS |
161 | atomic_inc(&nr_free_contexts); | |
162 | #endif | |
163 | } | |
ddca3b80 | 164 | preempt_enable(); |
1da177e4 LT |
165 | } |
166 | ||
167 | static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, | |
168 | struct task_struct *tsk) | |
169 | { | |
170 | #ifdef CONFIG_ALTIVEC | |
10b35d99 KG |
171 | if (cpu_has_feature(CPU_FTR_ALTIVEC)) |
172 | asm volatile ("dssall;\n" | |
1da177e4 LT |
173 | #ifndef CONFIG_POWER4 |
174 | "sync;\n" /* G4 needs a sync here, G5 apparently not */ | |
175 | #endif | |
1da177e4 LT |
176 | : : ); |
177 | #endif /* CONFIG_ALTIVEC */ | |
178 | ||
179 | tsk->thread.pgdir = next->pgd; | |
180 | ||
181 | /* No need to flush userspace segments if the mm doesnt change */ | |
182 | if (prev == next) | |
183 | return; | |
184 | ||
185 | /* Setup new userspace context */ | |
186 | get_mmu_context(next); | |
6218a761 | 187 | set_context(next->context.id, next->pgd); |
1da177e4 LT |
188 | } |
189 | ||
190 | #define deactivate_mm(tsk,mm) do { } while (0) | |
191 | ||
192 | /* | |
193 | * After we have set current->mm to a new value, this activates | |
194 | * the context for the new mm so we see the new mappings. | |
195 | */ | |
196 | #define activate_mm(active_mm, mm) switch_mm(active_mm, mm, current) | |
197 | ||
198 | extern void mmu_context_init(void); | |
199 | ||
200 | #endif /* __PPC_MMU_CONTEXT_H */ | |
201 | #endif /* __KERNEL__ */ |