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1da177e4 LT |
1 | /* |
2 | * MPC8xx Communication Processor Module. | |
3 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) | |
4 | * | |
5 | * This file contains structures and information for the communication | |
6 | * processor channels. Some CPM control and status is available | |
7 | * throught the MPC8xx internal memory map. See immap.h for details. | |
8 | * This file only contains what I need for the moment, not the total | |
9 | * CPM capabilities. I (or someone else) will add definitions as they | |
10 | * are needed. -- Dan | |
11 | * | |
12 | * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 | |
13 | * bytes of the DP RAM and relocates the I2C parameter area to the | |
14 | * IDMA1 space. The remaining DP RAM is available for buffer descriptors | |
15 | * or other use. | |
16 | */ | |
17 | #ifndef __CPM_8XX__ | |
18 | #define __CPM_8XX__ | |
19 | ||
1da177e4 LT |
20 | #include <asm/8xx_immap.h> |
21 | #include <asm/ptrace.h> | |
22 | ||
23 | /* CPM Command register. | |
24 | */ | |
25 | #define CPM_CR_RST ((ushort)0x8000) | |
26 | #define CPM_CR_OPCODE ((ushort)0x0f00) | |
27 | #define CPM_CR_CHAN ((ushort)0x00f0) | |
28 | #define CPM_CR_FLG ((ushort)0x0001) | |
29 | ||
30 | /* Some commands (there are more...later) | |
31 | */ | |
32 | #define CPM_CR_INIT_TRX ((ushort)0x0000) | |
33 | #define CPM_CR_INIT_RX ((ushort)0x0001) | |
34 | #define CPM_CR_INIT_TX ((ushort)0x0002) | |
35 | #define CPM_CR_HUNT_MODE ((ushort)0x0003) | |
36 | #define CPM_CR_STOP_TX ((ushort)0x0004) | |
61f5657c | 37 | #define CPM_CR_GRA_STOP_TX ((ushort)0x0005) |
1da177e4 LT |
38 | #define CPM_CR_RESTART_TX ((ushort)0x0006) |
39 | #define CPM_CR_CLOSE_RX_BD ((ushort)0x0007) | |
40 | #define CPM_CR_SET_GADDR ((ushort)0x0008) | |
41 | #define CPM_CR_SET_TIMER CPM_CR_SET_GADDR | |
42 | ||
43 | /* Channel numbers. | |
44 | */ | |
45 | #define CPM_CR_CH_SCC1 ((ushort)0x0000) | |
46 | #define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ | |
47 | #define CPM_CR_CH_SCC2 ((ushort)0x0004) | |
48 | #define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */ | |
49 | #define CPM_CR_CH_TIMER CPM_CR_CH_SPI | |
50 | #define CPM_CR_CH_SCC3 ((ushort)0x0008) | |
51 | #define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ | |
52 | #define CPM_CR_CH_SCC4 ((ushort)0x000c) | |
53 | #define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ | |
54 | ||
55 | #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) | |
56 | ||
57 | /* The dual ported RAM is multi-functional. Some areas can be (and are | |
58 | * being) used for microcode. There is an area that can only be used | |
59 | * as data ram for buffer descriptors, which is all we use right now. | |
60 | * Currently the first 512 and last 256 bytes are used for microcode. | |
61 | */ | |
62 | #define CPM_DATAONLY_BASE ((uint)0x0800) | |
63 | #define CPM_DATAONLY_SIZE ((uint)0x0700) | |
64 | #define CPM_DP_NOSPACE ((uint)0x7fffffff) | |
65 | ||
66 | static inline long IS_DPERR(const uint offset) | |
67 | { | |
68 | return (uint)offset > (uint)-1000L; | |
69 | } | |
70 | ||
71 | /* Export the base address of the communication processor registers | |
72 | * and dual port ram. | |
73 | */ | |
74 | extern cpm8xx_t *cpmp; /* Pointer to comm processor */ | |
75 | extern uint cpm_dpalloc(uint size, uint align); | |
76 | extern int cpm_dpfree(uint offset); | |
77 | extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align); | |
78 | extern void cpm_dpdump(void); | |
79 | extern void *cpm_dpram_addr(uint offset); | |
80 | extern void cpm_setbrg(uint brg, uint rate); | |
81 | ||
82 | extern uint m8xx_cpm_hostalloc(uint size); | |
83 | extern int m8xx_cpm_hostfree(uint start); | |
84 | extern void m8xx_cpm_hostdump(void); | |
85 | ||
38dc1618 MT |
86 | extern void cpm_load_patch(volatile immap_t *immr); |
87 | ||
1da177e4 LT |
88 | /* Buffer descriptors used by many of the CPM protocols. |
89 | */ | |
90 | typedef struct cpm_buf_desc { | |
91 | ushort cbd_sc; /* Status and Control */ | |
92 | ushort cbd_datlen; /* Data length in buffer */ | |
93 | uint cbd_bufaddr; /* Buffer address in host memory */ | |
94 | } cbd_t; | |
95 | ||
96 | #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ | |
97 | #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ | |
98 | #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ | |
99 | #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ | |
100 | #define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ | |
101 | #define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ | |
102 | #define BD_SC_CM ((ushort)0x0200) /* Continous mode */ | |
103 | #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ | |
104 | #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ | |
105 | #define BD_SC_BR ((ushort)0x0020) /* Break received */ | |
106 | #define BD_SC_FR ((ushort)0x0010) /* Framing error */ | |
107 | #define BD_SC_PR ((ushort)0x0008) /* Parity error */ | |
108 | #define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */ | |
109 | #define BD_SC_OV ((ushort)0x0002) /* Overrun */ | |
110 | #define BD_SC_UN ((ushort)0x0002) /* Underrun */ | |
111 | #define BD_SC_CD ((ushort)0x0001) /* ?? */ | |
112 | #define BD_SC_CL ((ushort)0x0001) /* Collision */ | |
113 | ||
114 | /* Parameter RAM offsets. | |
115 | */ | |
116 | #define PROFF_SCC1 ((uint)0x0000) | |
117 | #define PROFF_IIC ((uint)0x0080) | |
118 | #define PROFF_SCC2 ((uint)0x0100) | |
119 | #define PROFF_SPI ((uint)0x0180) | |
120 | #define PROFF_SCC3 ((uint)0x0200) | |
121 | #define PROFF_SMC1 ((uint)0x0280) | |
122 | #define PROFF_SCC4 ((uint)0x0300) | |
123 | #define PROFF_SMC2 ((uint)0x0380) | |
124 | ||
125 | /* Define enough so I can at least use the serial port as a UART. | |
126 | * The MBX uses SMC1 as the host serial port. | |
127 | */ | |
128 | typedef struct smc_uart { | |
129 | ushort smc_rbase; /* Rx Buffer descriptor base address */ | |
130 | ushort smc_tbase; /* Tx Buffer descriptor base address */ | |
131 | u_char smc_rfcr; /* Rx function code */ | |
132 | u_char smc_tfcr; /* Tx function code */ | |
133 | ushort smc_mrblr; /* Max receive buffer length */ | |
134 | uint smc_rstate; /* Internal */ | |
135 | uint smc_idp; /* Internal */ | |
136 | ushort smc_rbptr; /* Internal */ | |
137 | ushort smc_ibc; /* Internal */ | |
138 | uint smc_rxtmp; /* Internal */ | |
139 | uint smc_tstate; /* Internal */ | |
140 | uint smc_tdp; /* Internal */ | |
141 | ushort smc_tbptr; /* Internal */ | |
142 | ushort smc_tbc; /* Internal */ | |
143 | uint smc_txtmp; /* Internal */ | |
144 | ushort smc_maxidl; /* Maximum idle characters */ | |
145 | ushort smc_tmpidl; /* Temporary idle counter */ | |
146 | ushort smc_brklen; /* Last received break length */ | |
147 | ushort smc_brkec; /* rcv'd break condition counter */ | |
148 | ushort smc_brkcr; /* xmt break count register */ | |
149 | ushort smc_rmask; /* Temporary bit mask */ | |
150 | char res1[8]; /* Reserved */ | |
151 | ushort smc_rpbase; /* Relocation pointer */ | |
152 | } smc_uart_t; | |
153 | ||
154 | /* Function code bits. | |
155 | */ | |
156 | #define SMC_EB ((u_char)0x10) /* Set big endian byte order */ | |
157 | ||
158 | /* SMC uart mode register. | |
159 | */ | |
160 | #define SMCMR_REN ((ushort)0x0001) | |
161 | #define SMCMR_TEN ((ushort)0x0002) | |
162 | #define SMCMR_DM ((ushort)0x000c) | |
163 | #define SMCMR_SM_GCI ((ushort)0x0000) | |
164 | #define SMCMR_SM_UART ((ushort)0x0020) | |
165 | #define SMCMR_SM_TRANS ((ushort)0x0030) | |
166 | #define SMCMR_SM_MASK ((ushort)0x0030) | |
167 | #define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ | |
168 | #define SMCMR_REVD SMCMR_PM_EVEN | |
169 | #define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ | |
170 | #define SMCMR_BS SMCMR_PEN | |
171 | #define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ | |
172 | #define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ | |
173 | #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) | |
174 | ||
175 | /* SMC2 as Centronics parallel printer. It is half duplex, in that | |
176 | * it can only receive or transmit. The parameter ram values for | |
177 | * each direction are either unique or properly overlap, so we can | |
178 | * include them in one structure. | |
179 | */ | |
180 | typedef struct smc_centronics { | |
181 | ushort scent_rbase; | |
182 | ushort scent_tbase; | |
183 | u_char scent_cfcr; | |
184 | u_char scent_smask; | |
185 | ushort scent_mrblr; | |
186 | uint scent_rstate; | |
187 | uint scent_r_ptr; | |
188 | ushort scent_rbptr; | |
189 | ushort scent_r_cnt; | |
190 | uint scent_rtemp; | |
191 | uint scent_tstate; | |
192 | uint scent_t_ptr; | |
193 | ushort scent_tbptr; | |
194 | ushort scent_t_cnt; | |
195 | uint scent_ttemp; | |
196 | ushort scent_max_sl; | |
197 | ushort scent_sl_cnt; | |
198 | ushort scent_character1; | |
199 | ushort scent_character2; | |
200 | ushort scent_character3; | |
201 | ushort scent_character4; | |
202 | ushort scent_character5; | |
203 | ushort scent_character6; | |
204 | ushort scent_character7; | |
205 | ushort scent_character8; | |
206 | ushort scent_rccm; | |
207 | ushort scent_rccr; | |
208 | } smc_cent_t; | |
209 | ||
210 | /* Centronics Status Mask Register. | |
211 | */ | |
212 | #define SMC_CENT_F ((u_char)0x08) | |
213 | #define SMC_CENT_PE ((u_char)0x04) | |
214 | #define SMC_CENT_S ((u_char)0x02) | |
215 | ||
216 | /* SMC Event and Mask register. | |
217 | */ | |
218 | #define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ | |
219 | #define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ | |
220 | #define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ | |
221 | #define SMCM_BSY ((unsigned char)0x04) | |
222 | #define SMCM_TX ((unsigned char)0x02) | |
223 | #define SMCM_RX ((unsigned char)0x01) | |
224 | ||
225 | /* Baud rate generators. | |
226 | */ | |
227 | #define CPM_BRG_RST ((uint)0x00020000) | |
228 | #define CPM_BRG_EN ((uint)0x00010000) | |
229 | #define CPM_BRG_EXTC_INT ((uint)0x00000000) | |
230 | #define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) | |
231 | #define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) | |
232 | #define CPM_BRG_ATB ((uint)0x00002000) | |
233 | #define CPM_BRG_CD_MASK ((uint)0x00001ffe) | |
234 | #define CPM_BRG_DIV16 ((uint)0x00000001) | |
235 | ||
236 | /* SI Clock Route Register | |
237 | */ | |
238 | #define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) | |
239 | #define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) | |
240 | #define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) | |
241 | #define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) | |
242 | #define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) | |
243 | #define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) | |
244 | #define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) | |
245 | #define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) | |
246 | ||
247 | /* SCCs. | |
248 | */ | |
249 | #define SCC_GSMRH_IRP ((uint)0x00040000) | |
250 | #define SCC_GSMRH_GDE ((uint)0x00010000) | |
251 | #define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) | |
252 | #define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) | |
253 | #define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) | |
254 | #define SCC_GSMRH_REVD ((uint)0x00002000) | |
255 | #define SCC_GSMRH_TRX ((uint)0x00001000) | |
256 | #define SCC_GSMRH_TTX ((uint)0x00000800) | |
257 | #define SCC_GSMRH_CDP ((uint)0x00000400) | |
258 | #define SCC_GSMRH_CTSP ((uint)0x00000200) | |
259 | #define SCC_GSMRH_CDS ((uint)0x00000100) | |
260 | #define SCC_GSMRH_CTSS ((uint)0x00000080) | |
261 | #define SCC_GSMRH_TFL ((uint)0x00000040) | |
262 | #define SCC_GSMRH_RFW ((uint)0x00000020) | |
263 | #define SCC_GSMRH_TXSY ((uint)0x00000010) | |
264 | #define SCC_GSMRH_SYNL16 ((uint)0x0000000c) | |
265 | #define SCC_GSMRH_SYNL8 ((uint)0x00000008) | |
266 | #define SCC_GSMRH_SYNL4 ((uint)0x00000004) | |
267 | #define SCC_GSMRH_RTSM ((uint)0x00000002) | |
268 | #define SCC_GSMRH_RSYN ((uint)0x00000001) | |
269 | ||
270 | #define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ | |
271 | #define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) | |
272 | #define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) | |
273 | #define SCC_GSMRL_EDGE_POS ((uint)0x20000000) | |
274 | #define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) | |
275 | #define SCC_GSMRL_TCI ((uint)0x10000000) | |
276 | #define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) | |
277 | #define SCC_GSMRL_TSNC_4 ((uint)0x08000000) | |
278 | #define SCC_GSMRL_TSNC_14 ((uint)0x04000000) | |
279 | #define SCC_GSMRL_TSNC_INF ((uint)0x00000000) | |
280 | #define SCC_GSMRL_RINV ((uint)0x02000000) | |
281 | #define SCC_GSMRL_TINV ((uint)0x01000000) | |
282 | #define SCC_GSMRL_TPL_128 ((uint)0x00c00000) | |
283 | #define SCC_GSMRL_TPL_64 ((uint)0x00a00000) | |
284 | #define SCC_GSMRL_TPL_48 ((uint)0x00800000) | |
285 | #define SCC_GSMRL_TPL_32 ((uint)0x00600000) | |
286 | #define SCC_GSMRL_TPL_16 ((uint)0x00400000) | |
287 | #define SCC_GSMRL_TPL_8 ((uint)0x00200000) | |
288 | #define SCC_GSMRL_TPL_NONE ((uint)0x00000000) | |
289 | #define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) | |
290 | #define SCC_GSMRL_TPP_01 ((uint)0x00100000) | |
291 | #define SCC_GSMRL_TPP_10 ((uint)0x00080000) | |
292 | #define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) | |
293 | #define SCC_GSMRL_TEND ((uint)0x00040000) | |
294 | #define SCC_GSMRL_TDCR_32 ((uint)0x00030000) | |
295 | #define SCC_GSMRL_TDCR_16 ((uint)0x00020000) | |
296 | #define SCC_GSMRL_TDCR_8 ((uint)0x00010000) | |
297 | #define SCC_GSMRL_TDCR_1 ((uint)0x00000000) | |
298 | #define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) | |
299 | #define SCC_GSMRL_RDCR_16 ((uint)0x00008000) | |
300 | #define SCC_GSMRL_RDCR_8 ((uint)0x00004000) | |
301 | #define SCC_GSMRL_RDCR_1 ((uint)0x00000000) | |
302 | #define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) | |
303 | #define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) | |
304 | #define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) | |
305 | #define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) | |
306 | #define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) | |
307 | #define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) | |
308 | #define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) | |
309 | #define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) | |
310 | #define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) | |
311 | #define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) | |
312 | #define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ | |
313 | #define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) | |
314 | #define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) | |
315 | #define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) | |
316 | #define SCC_GSMRL_ENR ((uint)0x00000020) | |
317 | #define SCC_GSMRL_ENT ((uint)0x00000010) | |
318 | #define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) | |
319 | #define SCC_GSMRL_MODE_QMC ((uint)0x0000000a) | |
320 | #define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) | |
321 | #define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) | |
322 | #define SCC_GSMRL_MODE_V14 ((uint)0x00000007) | |
323 | #define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) | |
324 | #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) | |
325 | #define SCC_GSMRL_MODE_UART ((uint)0x00000004) | |
326 | #define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) | |
327 | #define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) | |
328 | #define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) | |
329 | ||
330 | #define SCC_TODR_TOD ((ushort)0x8000) | |
331 | ||
332 | /* SCC Event and Mask register. | |
333 | */ | |
334 | #define SCCM_TXE ((unsigned char)0x10) | |
335 | #define SCCM_BSY ((unsigned char)0x04) | |
336 | #define SCCM_TX ((unsigned char)0x02) | |
337 | #define SCCM_RX ((unsigned char)0x01) | |
338 | ||
339 | typedef struct scc_param { | |
340 | ushort scc_rbase; /* Rx Buffer descriptor base address */ | |
341 | ushort scc_tbase; /* Tx Buffer descriptor base address */ | |
342 | u_char scc_rfcr; /* Rx function code */ | |
343 | u_char scc_tfcr; /* Tx function code */ | |
344 | ushort scc_mrblr; /* Max receive buffer length */ | |
345 | uint scc_rstate; /* Internal */ | |
346 | uint scc_idp; /* Internal */ | |
347 | ushort scc_rbptr; /* Internal */ | |
348 | ushort scc_ibc; /* Internal */ | |
349 | uint scc_rxtmp; /* Internal */ | |
350 | uint scc_tstate; /* Internal */ | |
351 | uint scc_tdp; /* Internal */ | |
352 | ushort scc_tbptr; /* Internal */ | |
353 | ushort scc_tbc; /* Internal */ | |
354 | uint scc_txtmp; /* Internal */ | |
355 | uint scc_rcrc; /* Internal */ | |
356 | uint scc_tcrc; /* Internal */ | |
357 | } sccp_t; | |
358 | ||
359 | /* Function code bits. | |
360 | */ | |
361 | #define SCC_EB ((u_char)0x10) /* Set big endian byte order */ | |
362 | ||
363 | /* CPM Ethernet through SCCx. | |
364 | */ | |
365 | typedef struct scc_enet { | |
366 | sccp_t sen_genscc; | |
367 | uint sen_cpres; /* Preset CRC */ | |
368 | uint sen_cmask; /* Constant mask for CRC */ | |
369 | uint sen_crcec; /* CRC Error counter */ | |
370 | uint sen_alec; /* alignment error counter */ | |
371 | uint sen_disfc; /* discard frame counter */ | |
372 | ushort sen_pads; /* Tx short frame pad character */ | |
373 | ushort sen_retlim; /* Retry limit threshold */ | |
374 | ushort sen_retcnt; /* Retry limit counter */ | |
375 | ushort sen_maxflr; /* maximum frame length register */ | |
376 | ushort sen_minflr; /* minimum frame length register */ | |
377 | ushort sen_maxd1; /* maximum DMA1 length */ | |
378 | ushort sen_maxd2; /* maximum DMA2 length */ | |
379 | ushort sen_maxd; /* Rx max DMA */ | |
380 | ushort sen_dmacnt; /* Rx DMA counter */ | |
381 | ushort sen_maxb; /* Max BD byte count */ | |
382 | ushort sen_gaddr1; /* Group address filter */ | |
383 | ushort sen_gaddr2; | |
384 | ushort sen_gaddr3; | |
385 | ushort sen_gaddr4; | |
386 | uint sen_tbuf0data0; /* Save area 0 - current frame */ | |
387 | uint sen_tbuf0data1; /* Save area 1 - current frame */ | |
388 | uint sen_tbuf0rba; /* Internal */ | |
389 | uint sen_tbuf0crc; /* Internal */ | |
390 | ushort sen_tbuf0bcnt; /* Internal */ | |
391 | ushort sen_paddrh; /* physical address (MSB) */ | |
392 | ushort sen_paddrm; | |
393 | ushort sen_paddrl; /* physical address (LSB) */ | |
394 | ushort sen_pper; /* persistence */ | |
395 | ushort sen_rfbdptr; /* Rx first BD pointer */ | |
396 | ushort sen_tfbdptr; /* Tx first BD pointer */ | |
397 | ushort sen_tlbdptr; /* Tx last BD pointer */ | |
398 | uint sen_tbuf1data0; /* Save area 0 - current frame */ | |
399 | uint sen_tbuf1data1; /* Save area 1 - current frame */ | |
400 | uint sen_tbuf1rba; /* Internal */ | |
401 | uint sen_tbuf1crc; /* Internal */ | |
402 | ushort sen_tbuf1bcnt; /* Internal */ | |
403 | ushort sen_txlen; /* Tx Frame length counter */ | |
404 | ushort sen_iaddr1; /* Individual address filter */ | |
405 | ushort sen_iaddr2; | |
406 | ushort sen_iaddr3; | |
407 | ushort sen_iaddr4; | |
408 | ushort sen_boffcnt; /* Backoff counter */ | |
409 | ||
410 | /* NOTE: Some versions of the manual have the following items | |
411 | * incorrectly documented. Below is the proper order. | |
412 | */ | |
413 | ushort sen_taddrh; /* temp address (MSB) */ | |
414 | ushort sen_taddrm; | |
415 | ushort sen_taddrl; /* temp address (LSB) */ | |
416 | } scc_enet_t; | |
417 | ||
418 | /* SCC Event register as used by Ethernet. | |
419 | */ | |
420 | #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ | |
421 | #define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ | |
422 | #define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ | |
423 | #define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ | |
424 | #define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ | |
425 | #define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ | |
426 | ||
427 | /* SCC Mode Register (PMSR) as used by Ethernet. | |
428 | */ | |
429 | #define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ | |
430 | #define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ | |
431 | #define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ | |
432 | #define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ | |
433 | #define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ | |
434 | #define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ | |
435 | #define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ | |
436 | #define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ | |
437 | #define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ | |
438 | #define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ | |
439 | #define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ | |
440 | #define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ | |
441 | #define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ | |
442 | ||
443 | /* Buffer descriptor control/status used by Ethernet receive. | |
444 | */ | |
445 | #define BD_ENET_RX_EMPTY ((ushort)0x8000) | |
446 | #define BD_ENET_RX_WRAP ((ushort)0x2000) | |
447 | #define BD_ENET_RX_INTR ((ushort)0x1000) | |
448 | #define BD_ENET_RX_LAST ((ushort)0x0800) | |
449 | #define BD_ENET_RX_FIRST ((ushort)0x0400) | |
450 | #define BD_ENET_RX_MISS ((ushort)0x0100) | |
451 | #define BD_ENET_RX_LG ((ushort)0x0020) | |
452 | #define BD_ENET_RX_NO ((ushort)0x0010) | |
453 | #define BD_ENET_RX_SH ((ushort)0x0008) | |
454 | #define BD_ENET_RX_CR ((ushort)0x0004) | |
455 | #define BD_ENET_RX_OV ((ushort)0x0002) | |
456 | #define BD_ENET_RX_CL ((ushort)0x0001) | |
457 | #define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */ | |
458 | #define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */ | |
459 | #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ | |
460 | ||
461 | /* Buffer descriptor control/status used by Ethernet transmit. | |
462 | */ | |
463 | #define BD_ENET_TX_READY ((ushort)0x8000) | |
464 | #define BD_ENET_TX_PAD ((ushort)0x4000) | |
465 | #define BD_ENET_TX_WRAP ((ushort)0x2000) | |
466 | #define BD_ENET_TX_INTR ((ushort)0x1000) | |
467 | #define BD_ENET_TX_LAST ((ushort)0x0800) | |
468 | #define BD_ENET_TX_TC ((ushort)0x0400) | |
469 | #define BD_ENET_TX_DEF ((ushort)0x0200) | |
470 | #define BD_ENET_TX_HB ((ushort)0x0100) | |
471 | #define BD_ENET_TX_LC ((ushort)0x0080) | |
472 | #define BD_ENET_TX_RL ((ushort)0x0040) | |
473 | #define BD_ENET_TX_RCMASK ((ushort)0x003c) | |
474 | #define BD_ENET_TX_UN ((ushort)0x0002) | |
475 | #define BD_ENET_TX_CSL ((ushort)0x0001) | |
476 | #define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ | |
477 | ||
478 | /* SCC as UART | |
479 | */ | |
480 | typedef struct scc_uart { | |
481 | sccp_t scc_genscc; | |
482 | char res1[8]; /* Reserved */ | |
483 | ushort scc_maxidl; /* Maximum idle chars */ | |
484 | ushort scc_idlc; /* temp idle counter */ | |
485 | ushort scc_brkcr; /* Break count register */ | |
486 | ushort scc_parec; /* receive parity error counter */ | |
487 | ushort scc_frmec; /* receive framing error counter */ | |
488 | ushort scc_nosec; /* receive noise counter */ | |
489 | ushort scc_brkec; /* receive break condition counter */ | |
490 | ushort scc_brkln; /* last received break length */ | |
491 | ushort scc_uaddr1; /* UART address character 1 */ | |
492 | ushort scc_uaddr2; /* UART address character 2 */ | |
493 | ushort scc_rtemp; /* Temp storage */ | |
494 | ushort scc_toseq; /* Transmit out of sequence char */ | |
495 | ushort scc_char1; /* control character 1 */ | |
496 | ushort scc_char2; /* control character 2 */ | |
497 | ushort scc_char3; /* control character 3 */ | |
498 | ushort scc_char4; /* control character 4 */ | |
499 | ushort scc_char5; /* control character 5 */ | |
500 | ushort scc_char6; /* control character 6 */ | |
501 | ushort scc_char7; /* control character 7 */ | |
502 | ushort scc_char8; /* control character 8 */ | |
503 | ushort scc_rccm; /* receive control character mask */ | |
504 | ushort scc_rccr; /* receive control character register */ | |
505 | ushort scc_rlbc; /* receive last break character */ | |
506 | } scc_uart_t; | |
507 | ||
508 | /* SCC Event and Mask registers when it is used as a UART. | |
509 | */ | |
510 | #define UART_SCCM_GLR ((ushort)0x1000) | |
511 | #define UART_SCCM_GLT ((ushort)0x0800) | |
512 | #define UART_SCCM_AB ((ushort)0x0200) | |
513 | #define UART_SCCM_IDL ((ushort)0x0100) | |
514 | #define UART_SCCM_GRA ((ushort)0x0080) | |
515 | #define UART_SCCM_BRKE ((ushort)0x0040) | |
516 | #define UART_SCCM_BRKS ((ushort)0x0020) | |
517 | #define UART_SCCM_CCR ((ushort)0x0008) | |
518 | #define UART_SCCM_BSY ((ushort)0x0004) | |
519 | #define UART_SCCM_TX ((ushort)0x0002) | |
520 | #define UART_SCCM_RX ((ushort)0x0001) | |
521 | ||
522 | /* The SCC PMSR when used as a UART. | |
523 | */ | |
524 | #define SCU_PSMR_FLC ((ushort)0x8000) | |
525 | #define SCU_PSMR_SL ((ushort)0x4000) | |
526 | #define SCU_PSMR_CL ((ushort)0x3000) | |
527 | #define SCU_PSMR_UM ((ushort)0x0c00) | |
528 | #define SCU_PSMR_FRZ ((ushort)0x0200) | |
529 | #define SCU_PSMR_RZS ((ushort)0x0100) | |
530 | #define SCU_PSMR_SYN ((ushort)0x0080) | |
531 | #define SCU_PSMR_DRT ((ushort)0x0040) | |
532 | #define SCU_PSMR_PEN ((ushort)0x0010) | |
533 | #define SCU_PSMR_RPM ((ushort)0x000c) | |
534 | #define SCU_PSMR_REVP ((ushort)0x0008) | |
535 | #define SCU_PSMR_TPM ((ushort)0x0003) | |
536 | #define SCU_PSMR_TEVP ((ushort)0x0002) | |
537 | ||
538 | /* CPM Transparent mode SCC. | |
539 | */ | |
540 | typedef struct scc_trans { | |
541 | sccp_t st_genscc; | |
542 | uint st_cpres; /* Preset CRC */ | |
543 | uint st_cmask; /* Constant mask for CRC */ | |
544 | } scc_trans_t; | |
545 | ||
546 | #define BD_SCC_TX_LAST ((ushort)0x0800) | |
547 | ||
548 | /* IIC parameter RAM. | |
549 | */ | |
550 | typedef struct iic { | |
551 | ushort iic_rbase; /* Rx Buffer descriptor base address */ | |
552 | ushort iic_tbase; /* Tx Buffer descriptor base address */ | |
553 | u_char iic_rfcr; /* Rx function code */ | |
554 | u_char iic_tfcr; /* Tx function code */ | |
555 | ushort iic_mrblr; /* Max receive buffer length */ | |
556 | uint iic_rstate; /* Internal */ | |
557 | uint iic_rdp; /* Internal */ | |
558 | ushort iic_rbptr; /* Internal */ | |
559 | ushort iic_rbc; /* Internal */ | |
560 | uint iic_rxtmp; /* Internal */ | |
561 | uint iic_tstate; /* Internal */ | |
562 | uint iic_tdp; /* Internal */ | |
563 | ushort iic_tbptr; /* Internal */ | |
564 | ushort iic_tbc; /* Internal */ | |
565 | uint iic_txtmp; /* Internal */ | |
566 | char res1[4]; /* Reserved */ | |
567 | ushort iic_rpbase; /* Relocation pointer */ | |
568 | char res2[2]; /* Reserved */ | |
569 | } iic_t; | |
570 | ||
571 | #define BD_IIC_START ((ushort)0x0400) | |
572 | ||
573 | /* SPI parameter RAM. | |
574 | */ | |
575 | typedef struct spi { | |
576 | ushort spi_rbase; /* Rx Buffer descriptor base address */ | |
577 | ushort spi_tbase; /* Tx Buffer descriptor base address */ | |
578 | u_char spi_rfcr; /* Rx function code */ | |
579 | u_char spi_tfcr; /* Tx function code */ | |
580 | ushort spi_mrblr; /* Max receive buffer length */ | |
581 | uint spi_rstate; /* Internal */ | |
582 | uint spi_rdp; /* Internal */ | |
583 | ushort spi_rbptr; /* Internal */ | |
584 | ushort spi_rbc; /* Internal */ | |
585 | uint spi_rxtmp; /* Internal */ | |
586 | uint spi_tstate; /* Internal */ | |
587 | uint spi_tdp; /* Internal */ | |
588 | ushort spi_tbptr; /* Internal */ | |
589 | ushort spi_tbc; /* Internal */ | |
590 | uint spi_txtmp; /* Internal */ | |
591 | uint spi_res; | |
592 | ushort spi_rpbase; /* Relocation pointer */ | |
593 | ushort spi_res2; | |
594 | } spi_t; | |
595 | ||
596 | /* SPI Mode register. | |
597 | */ | |
598 | #define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ | |
599 | #define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ | |
600 | #define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ | |
601 | #define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ | |
602 | #define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ | |
603 | #define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ | |
604 | #define SPMODE_EN ((ushort)0x0100) /* Enable */ | |
605 | #define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ | |
606 | #define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */ | |
607 | #define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */ | |
608 | #define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */ | |
609 | #define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ | |
610 | ||
611 | /* SPIE fields */ | |
612 | #define SPIE_MME 0x20 | |
613 | #define SPIE_TXE 0x10 | |
614 | #define SPIE_BSY 0x04 | |
615 | #define SPIE_TXB 0x02 | |
616 | #define SPIE_RXB 0x01 | |
617 | ||
618 | /* | |
619 | * RISC Controller Configuration Register definitons | |
620 | */ | |
621 | #define RCCR_TIME 0x8000 /* RISC Timer Enable */ | |
622 | #define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */ | |
623 | #define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */ | |
624 | ||
625 | /* RISC Timer Parameter RAM offset */ | |
626 | #define PROFF_RTMR ((uint)0x01B0) | |
627 | ||
628 | typedef struct risc_timer_pram { | |
629 | unsigned short tm_base; /* RISC Timer Table Base Address */ | |
630 | unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */ | |
631 | unsigned short r_tmr; /* RISC Timer Mode Register */ | |
632 | unsigned short r_tmv; /* RISC Timer Valid Register */ | |
633 | unsigned long tm_cmd; /* RISC Timer Command Register */ | |
634 | unsigned long tm_cnt; /* RISC Timer Internal Count */ | |
635 | } rt_pram_t; | |
636 | ||
637 | /* Bits in RISC Timer Command Register */ | |
638 | #define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */ | |
639 | #define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */ | |
640 | #define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */ | |
641 | #define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */ | |
642 | #define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */ | |
643 | ||
644 | /* CPM interrupts. There are nearly 32 interrupts generated by CPM | |
645 | * channels or devices. All of these are presented to the PPC core | |
646 | * as a single interrupt. The CPM interrupt handler dispatches its | |
647 | * own handlers, in a similar fashion to the PPC core handler. We | |
648 | * use the table as defined in the manuals (i.e. no special high | |
649 | * priority and SCC1 == SCCa, etc...). | |
650 | */ | |
651 | #define CPMVEC_NR 32 | |
652 | #define CPMVEC_PIO_PC15 ((ushort)0x1f) | |
653 | #define CPMVEC_SCC1 ((ushort)0x1e) | |
654 | #define CPMVEC_SCC2 ((ushort)0x1d) | |
655 | #define CPMVEC_SCC3 ((ushort)0x1c) | |
656 | #define CPMVEC_SCC4 ((ushort)0x1b) | |
657 | #define CPMVEC_PIO_PC14 ((ushort)0x1a) | |
658 | #define CPMVEC_TIMER1 ((ushort)0x19) | |
659 | #define CPMVEC_PIO_PC13 ((ushort)0x18) | |
660 | #define CPMVEC_PIO_PC12 ((ushort)0x17) | |
661 | #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) | |
662 | #define CPMVEC_IDMA1 ((ushort)0x15) | |
663 | #define CPMVEC_IDMA2 ((ushort)0x14) | |
664 | #define CPMVEC_TIMER2 ((ushort)0x12) | |
665 | #define CPMVEC_RISCTIMER ((ushort)0x11) | |
666 | #define CPMVEC_I2C ((ushort)0x10) | |
667 | #define CPMVEC_PIO_PC11 ((ushort)0x0f) | |
668 | #define CPMVEC_PIO_PC10 ((ushort)0x0e) | |
669 | #define CPMVEC_TIMER3 ((ushort)0x0c) | |
670 | #define CPMVEC_PIO_PC9 ((ushort)0x0b) | |
671 | #define CPMVEC_PIO_PC8 ((ushort)0x0a) | |
672 | #define CPMVEC_PIO_PC7 ((ushort)0x09) | |
673 | #define CPMVEC_TIMER4 ((ushort)0x07) | |
674 | #define CPMVEC_PIO_PC6 ((ushort)0x06) | |
675 | #define CPMVEC_SPI ((ushort)0x05) | |
676 | #define CPMVEC_SMC1 ((ushort)0x04) | |
677 | #define CPMVEC_SMC2 ((ushort)0x03) | |
678 | #define CPMVEC_PIO_PC5 ((ushort)0x02) | |
679 | #define CPMVEC_PIO_PC4 ((ushort)0x01) | |
680 | #define CPMVEC_ERROR ((ushort)0x00) | |
681 | ||
682 | /* CPM interrupt configuration vector. | |
683 | */ | |
684 | #define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ | |
685 | #define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ | |
686 | #define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ | |
687 | #define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ | |
688 | #define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ | |
689 | #define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ | |
690 | #define CICR_IEN ((uint)0x00000080) /* Int. enable */ | |
691 | #define CICR_SPS ((uint)0x00000001) /* SCC Spread */ | |
692 | ||
39e3eb72 | 693 | extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); |
1da177e4 LT |
694 | extern void cpm_free_handler(int vec); |
695 | ||
696 | #endif /* __CPM_8XX__ */ |