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1da177e4 LT |
1 | /* |
2 | * include/asm-ppc/cache.h | |
3 | */ | |
4 | #ifdef __KERNEL__ | |
5 | #ifndef __ARCH_PPC_CACHE_H | |
6 | #define __ARCH_PPC_CACHE_H | |
7 | ||
8 | #include <linux/config.h> | |
9 | ||
10 | /* bytes per L1 cache line */ | |
11 | #if defined(CONFIG_8xx) || defined(CONFIG_403GCX) | |
12 | #define L1_CACHE_LINE_SIZE 16 | |
13 | #define LG_L1_CACHE_LINE_SIZE 4 | |
14 | #define MAX_COPY_PREFETCH 1 | |
15 | #elif defined(CONFIG_PPC64BRIDGE) | |
16 | #define L1_CACHE_LINE_SIZE 128 | |
17 | #define LG_L1_CACHE_LINE_SIZE 7 | |
18 | #define MAX_COPY_PREFETCH 1 | |
19 | #else | |
20 | #define L1_CACHE_LINE_SIZE 32 | |
21 | #define LG_L1_CACHE_LINE_SIZE 5 | |
22 | #define MAX_COPY_PREFETCH 4 | |
23 | #endif | |
24 | ||
25 | #define L1_CACHE_BYTES L1_CACHE_LINE_SIZE | |
26 | #define L1_CACHE_SHIFT LG_L1_CACHE_LINE_SIZE | |
27 | #define SMP_CACHE_BYTES L1_CACHE_BYTES | |
28 | #define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */ | |
29 | ||
30 | #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) | |
31 | #define L1_CACHE_PAGES 8 | |
32 | ||
33 | #ifndef __ASSEMBLY__ | |
34 | extern void clean_dcache_range(unsigned long start, unsigned long stop); | |
35 | extern void flush_dcache_range(unsigned long start, unsigned long stop); | |
36 | extern void invalidate_dcache_range(unsigned long start, unsigned long stop); | |
37 | extern void flush_dcache_all(void); | |
38 | #endif /* __ASSEMBLY__ */ | |
39 | ||
40 | /* prep registers for L2 */ | |
41 | #define CACHECRBA 0x80000823 /* Cache configuration register address */ | |
42 | #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */ | |
43 | #define L2CACHE_512KB 0x00 /* 512KB */ | |
44 | #define L2CACHE_256KB 0x01 /* 256KB */ | |
45 | #define L2CACHE_1MB 0x02 /* 1MB */ | |
46 | #define L2CACHE_NONE 0x03 /* NONE */ | |
47 | #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */ | |
48 | ||
49 | #ifdef CONFIG_8xx | |
50 | /* Cache control on the MPC8xx is provided through some additional | |
51 | * special purpose registers. | |
52 | */ | |
53 | #define SPRN_IC_CST 560 /* Instruction cache control/status */ | |
54 | #define SPRN_IC_ADR 561 /* Address needed for some commands */ | |
55 | #define SPRN_IC_DAT 562 /* Read-only data register */ | |
56 | #define SPRN_DC_CST 568 /* Data cache control/status */ | |
57 | #define SPRN_DC_ADR 569 /* Address needed for some commands */ | |
58 | #define SPRN_DC_DAT 570 /* Read-only data register */ | |
59 | ||
60 | /* Commands. Only the first few are available to the instruction cache. | |
61 | */ | |
62 | #define IDC_ENABLE 0x02000000 /* Cache enable */ | |
63 | #define IDC_DISABLE 0x04000000 /* Cache disable */ | |
64 | #define IDC_LDLCK 0x06000000 /* Load and lock */ | |
65 | #define IDC_UNLINE 0x08000000 /* Unlock line */ | |
66 | #define IDC_UNALL 0x0a000000 /* Unlock all */ | |
67 | #define IDC_INVALL 0x0c000000 /* Invalidate all */ | |
68 | ||
69 | #define DC_FLINE 0x0e000000 /* Flush data cache line */ | |
70 | #define DC_SFWT 0x01000000 /* Set forced writethrough mode */ | |
71 | #define DC_CFWT 0x03000000 /* Clear forced writethrough mode */ | |
72 | #define DC_SLES 0x05000000 /* Set little endian swap mode */ | |
73 | #define DC_CLES 0x07000000 /* Clear little endian swap mode */ | |
74 | ||
75 | /* Status. | |
76 | */ | |
77 | #define IDC_ENABLED 0x80000000 /* Cache is enabled */ | |
78 | #define IDC_CERR1 0x00200000 /* Cache error 1 */ | |
79 | #define IDC_CERR2 0x00100000 /* Cache error 2 */ | |
80 | #define IDC_CERR3 0x00080000 /* Cache error 3 */ | |
81 | ||
82 | #define DC_DFWT 0x40000000 /* Data cache is forced write through */ | |
83 | #define DC_LES 0x20000000 /* Caches are little endian mode */ | |
84 | #endif /* CONFIG_8xx */ | |
85 | ||
86 | #endif | |
87 | #endif /* __KERNEL__ */ |