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14cf11af PM |
1 | /* |
2 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> | |
3 | */ | |
bbeb3f4c SR |
4 | #ifndef _ASM_POWERPC_SYSTEM_H |
5 | #define _ASM_POWERPC_SYSTEM_H | |
14cf11af | 6 | |
14cf11af PM |
7 | #include <linux/kernel.h> |
8 | ||
9 | #include <asm/hw_irq.h> | |
40ef8cbc | 10 | #include <asm/atomic.h> |
14cf11af PM |
11 | |
12 | /* | |
13 | * Memory barrier. | |
14 | * The sync instruction guarantees that all memory accesses initiated | |
15 | * by this processor have been performed (with respect to all other | |
16 | * mechanisms that access memory). The eieio instruction is a barrier | |
17 | * providing an ordering (separately) for (a) cacheable stores and (b) | |
18 | * loads and stores to non-cacheable memory (e.g. I/O devices). | |
19 | * | |
20 | * mb() prevents loads and stores being reordered across this point. | |
21 | * rmb() prevents loads being reordered across this point. | |
22 | * wmb() prevents stores being reordered across this point. | |
23 | * read_barrier_depends() prevents data-dependent loads being reordered | |
24 | * across this point (nop on PPC). | |
25 | * | |
26 | * We have to use the sync instructions for mb(), since lwsync doesn't | |
27 | * order loads with respect to previous stores. Lwsync is fine for | |
28 | * rmb(), though. Note that lwsync is interpreted as sync by | |
29 | * 32-bit and older 64-bit CPUs. | |
30 | * | |
31 | * For wmb(), we use sync since wmb is used in drivers to order | |
32 | * stores to system memory with respect to writes to the device. | |
33 | * However, smp_wmb() can be a lighter-weight eieio barrier on | |
34 | * SMP since it is only used to order updates to system memory. | |
35 | */ | |
36 | #define mb() __asm__ __volatile__ ("sync" : : : "memory") | |
37 | #define rmb() __asm__ __volatile__ ("lwsync" : : : "memory") | |
38 | #define wmb() __asm__ __volatile__ ("sync" : : : "memory") | |
39 | #define read_barrier_depends() do { } while(0) | |
40 | ||
41 | #define set_mb(var, value) do { var = value; mb(); } while (0) | |
42 | #define set_wmb(var, value) do { var = value; wmb(); } while (0) | |
43 | ||
88ced031 | 44 | #ifdef __KERNEL__ |
14cf11af PM |
45 | #ifdef CONFIG_SMP |
46 | #define smp_mb() mb() | |
47 | #define smp_rmb() rmb() | |
48 | #define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory") | |
49 | #define smp_read_barrier_depends() read_barrier_depends() | |
50 | #else | |
51 | #define smp_mb() barrier() | |
52 | #define smp_rmb() barrier() | |
53 | #define smp_wmb() barrier() | |
54 | #define smp_read_barrier_depends() do { } while(0) | |
55 | #endif /* CONFIG_SMP */ | |
56 | ||
14cf11af PM |
57 | struct task_struct; |
58 | struct pt_regs; | |
59 | ||
60 | #ifdef CONFIG_DEBUGGER | |
61 | ||
62 | extern int (*__debugger)(struct pt_regs *regs); | |
63 | extern int (*__debugger_ipi)(struct pt_regs *regs); | |
64 | extern int (*__debugger_bpt)(struct pt_regs *regs); | |
65 | extern int (*__debugger_sstep)(struct pt_regs *regs); | |
66 | extern int (*__debugger_iabr_match)(struct pt_regs *regs); | |
67 | extern int (*__debugger_dabr_match)(struct pt_regs *regs); | |
68 | extern int (*__debugger_fault_handler)(struct pt_regs *regs); | |
69 | ||
70 | #define DEBUGGER_BOILERPLATE(__NAME) \ | |
71 | static inline int __NAME(struct pt_regs *regs) \ | |
72 | { \ | |
73 | if (unlikely(__ ## __NAME)) \ | |
74 | return __ ## __NAME(regs); \ | |
75 | return 0; \ | |
76 | } | |
77 | ||
78 | DEBUGGER_BOILERPLATE(debugger) | |
79 | DEBUGGER_BOILERPLATE(debugger_ipi) | |
80 | DEBUGGER_BOILERPLATE(debugger_bpt) | |
81 | DEBUGGER_BOILERPLATE(debugger_sstep) | |
82 | DEBUGGER_BOILERPLATE(debugger_iabr_match) | |
83 | DEBUGGER_BOILERPLATE(debugger_dabr_match) | |
84 | DEBUGGER_BOILERPLATE(debugger_fault_handler) | |
85 | ||
86 | #ifdef CONFIG_XMON | |
87 | extern void xmon_init(int enable); | |
88 | #endif | |
89 | ||
90 | #else | |
91 | static inline int debugger(struct pt_regs *regs) { return 0; } | |
92 | static inline int debugger_ipi(struct pt_regs *regs) { return 0; } | |
93 | static inline int debugger_bpt(struct pt_regs *regs) { return 0; } | |
94 | static inline int debugger_sstep(struct pt_regs *regs) { return 0; } | |
95 | static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; } | |
96 | static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; } | |
97 | static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; } | |
98 | #endif | |
99 | ||
100 | extern int set_dabr(unsigned long dabr); | |
101 | extern void print_backtrace(unsigned long *); | |
102 | extern void show_regs(struct pt_regs * regs); | |
103 | extern void flush_instruction_cache(void); | |
104 | extern void hard_reset_now(void); | |
105 | extern void poweroff_now(void); | |
106 | ||
107 | #ifdef CONFIG_6xx | |
108 | extern long _get_L2CR(void); | |
109 | extern long _get_L3CR(void); | |
110 | extern void _set_L2CR(unsigned long); | |
111 | extern void _set_L3CR(unsigned long); | |
112 | #else | |
113 | #define _get_L2CR() 0L | |
114 | #define _get_L3CR() 0L | |
115 | #define _set_L2CR(val) do { } while(0) | |
116 | #define _set_L3CR(val) do { } while(0) | |
117 | #endif | |
118 | ||
119 | extern void via_cuda_init(void); | |
14cf11af PM |
120 | extern void read_rtc_time(void); |
121 | extern void pmac_find_display(void); | |
122 | extern void giveup_fpu(struct task_struct *); | |
cabb5587 | 123 | extern void disable_kernel_fp(void); |
14cf11af PM |
124 | extern void enable_kernel_fp(void); |
125 | extern void flush_fp_to_thread(struct task_struct *); | |
126 | extern void enable_kernel_altivec(void); | |
127 | extern void giveup_altivec(struct task_struct *); | |
128 | extern void load_up_altivec(struct task_struct *); | |
40ef8cbc | 129 | extern int emulate_altivec(struct pt_regs *); |
14cf11af PM |
130 | extern void giveup_spe(struct task_struct *); |
131 | extern void load_up_spe(struct task_struct *); | |
132 | extern int fix_alignment(struct pt_regs *); | |
25c8a78b DG |
133 | extern void cvt_fd(float *from, double *to, struct thread_struct *thread); |
134 | extern void cvt_df(double *from, float *to, struct thread_struct *thread); | |
14cf11af | 135 | |
5388fb10 PM |
136 | #ifndef CONFIG_SMP |
137 | extern void discard_lazy_cpu_state(void); | |
138 | #else | |
139 | static inline void discard_lazy_cpu_state(void) | |
140 | { | |
141 | } | |
142 | #endif | |
143 | ||
14cf11af PM |
144 | #ifdef CONFIG_ALTIVEC |
145 | extern void flush_altivec_to_thread(struct task_struct *); | |
146 | #else | |
147 | static inline void flush_altivec_to_thread(struct task_struct *t) | |
148 | { | |
149 | } | |
150 | #endif | |
151 | ||
152 | #ifdef CONFIG_SPE | |
153 | extern void flush_spe_to_thread(struct task_struct *); | |
154 | #else | |
155 | static inline void flush_spe_to_thread(struct task_struct *t) | |
156 | { | |
157 | } | |
158 | #endif | |
159 | ||
160 | extern int call_rtas(const char *, int, int, unsigned long *, ...); | |
161 | extern void cacheable_memzero(void *p, unsigned int nb); | |
162 | extern void *cacheable_memcpy(void *, const void *, unsigned int); | |
163 | extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long); | |
164 | extern void bad_page_fault(struct pt_regs *, unsigned long, int); | |
165 | extern int die(const char *, struct pt_regs *, long); | |
166 | extern void _exception(int, struct pt_regs *, int, unsigned long); | |
167 | #ifdef CONFIG_BOOKE_WDT | |
168 | extern u32 booke_wdt_enabled; | |
169 | extern u32 booke_wdt_period; | |
170 | #endif /* CONFIG_BOOKE_WDT */ | |
171 | ||
172 | /* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */ | |
173 | extern unsigned char e2a(unsigned char); | |
174 | ||
175 | struct device_node; | |
176 | extern void note_scsi_host(struct device_node *, void *); | |
177 | ||
178 | extern struct task_struct *__switch_to(struct task_struct *, | |
179 | struct task_struct *); | |
180 | #define switch_to(prev, next, last) ((last) = __switch_to((prev), (next))) | |
181 | ||
182 | struct thread_struct; | |
183 | extern struct task_struct *_switch(struct thread_struct *prev, | |
184 | struct thread_struct *next); | |
185 | ||
4dc7a0bb IM |
186 | /* |
187 | * On SMP systems, when the scheduler does migration-cost autodetection, | |
188 | * it needs a way to flush as much of the CPU's caches as possible. | |
189 | * | |
190 | * TODO: fill this in! | |
191 | */ | |
192 | static inline void sched_cacheflush(void) | |
193 | { | |
194 | } | |
195 | ||
14cf11af | 196 | extern unsigned int rtas_data; |
40ef8cbc | 197 | extern int mem_init_done; /* set on boot once kmalloc can be called */ |
cf00a8d1 | 198 | extern unsigned long memory_limit; |
49b09853 | 199 | extern unsigned long klimit; |
14cf11af | 200 | |
17a6392d PM |
201 | extern int powersave_nap; /* set if nap mode can be used in idle loop */ |
202 | ||
14cf11af PM |
203 | /* |
204 | * Atomic exchange | |
205 | * | |
206 | * Changes the memory location '*ptr' to be val and returns | |
207 | * the previous value stored there. | |
208 | */ | |
209 | static __inline__ unsigned long | |
210 | __xchg_u32(volatile void *p, unsigned long val) | |
211 | { | |
212 | unsigned long prev; | |
213 | ||
214 | __asm__ __volatile__( | |
144b9c13 | 215 | LWSYNC_ON_SMP |
14cf11af PM |
216 | "1: lwarx %0,0,%2 \n" |
217 | PPC405_ERR77(0,%2) | |
218 | " stwcx. %3,0,%2 \n\ | |
219 | bne- 1b" | |
220 | ISYNC_ON_SMP | |
221 | : "=&r" (prev), "=m" (*(volatile unsigned int *)p) | |
222 | : "r" (p), "r" (val), "m" (*(volatile unsigned int *)p) | |
223 | : "cc", "memory"); | |
224 | ||
225 | return prev; | |
226 | } | |
227 | ||
228 | #ifdef CONFIG_PPC64 | |
229 | static __inline__ unsigned long | |
230 | __xchg_u64(volatile void *p, unsigned long val) | |
231 | { | |
232 | unsigned long prev; | |
233 | ||
234 | __asm__ __volatile__( | |
144b9c13 | 235 | LWSYNC_ON_SMP |
14cf11af PM |
236 | "1: ldarx %0,0,%2 \n" |
237 | PPC405_ERR77(0,%2) | |
238 | " stdcx. %3,0,%2 \n\ | |
239 | bne- 1b" | |
240 | ISYNC_ON_SMP | |
241 | : "=&r" (prev), "=m" (*(volatile unsigned long *)p) | |
242 | : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p) | |
243 | : "cc", "memory"); | |
244 | ||
245 | return prev; | |
246 | } | |
247 | #endif | |
248 | ||
249 | /* | |
250 | * This function doesn't exist, so you'll get a linker error | |
251 | * if something tries to do an invalid xchg(). | |
252 | */ | |
253 | extern void __xchg_called_with_bad_pointer(void); | |
254 | ||
255 | static __inline__ unsigned long | |
256 | __xchg(volatile void *ptr, unsigned long x, unsigned int size) | |
257 | { | |
258 | switch (size) { | |
259 | case 4: | |
260 | return __xchg_u32(ptr, x); | |
261 | #ifdef CONFIG_PPC64 | |
262 | case 8: | |
263 | return __xchg_u64(ptr, x); | |
264 | #endif | |
265 | } | |
266 | __xchg_called_with_bad_pointer(); | |
267 | return x; | |
268 | } | |
269 | ||
270 | #define xchg(ptr,x) \ | |
271 | ({ \ | |
272 | __typeof__(*(ptr)) _x_ = (x); \ | |
273 | (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \ | |
274 | }) | |
275 | ||
276 | #define tas(ptr) (xchg((ptr),1)) | |
277 | ||
278 | /* | |
279 | * Compare and exchange - if *p == old, set it to new, | |
280 | * and return the old value of *p. | |
281 | */ | |
282 | #define __HAVE_ARCH_CMPXCHG 1 | |
283 | ||
284 | static __inline__ unsigned long | |
285 | __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new) | |
286 | { | |
287 | unsigned int prev; | |
288 | ||
289 | __asm__ __volatile__ ( | |
144b9c13 | 290 | LWSYNC_ON_SMP |
14cf11af PM |
291 | "1: lwarx %0,0,%2 # __cmpxchg_u32\n\ |
292 | cmpw 0,%0,%3\n\ | |
293 | bne- 2f\n" | |
294 | PPC405_ERR77(0,%2) | |
295 | " stwcx. %4,0,%2\n\ | |
296 | bne- 1b" | |
297 | ISYNC_ON_SMP | |
298 | "\n\ | |
299 | 2:" | |
300 | : "=&r" (prev), "=m" (*p) | |
301 | : "r" (p), "r" (old), "r" (new), "m" (*p) | |
302 | : "cc", "memory"); | |
303 | ||
304 | return prev; | |
305 | } | |
306 | ||
307 | #ifdef CONFIG_PPC64 | |
308 | static __inline__ unsigned long | |
3c726f8d | 309 | __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new) |
14cf11af PM |
310 | { |
311 | unsigned long prev; | |
312 | ||
313 | __asm__ __volatile__ ( | |
144b9c13 | 314 | LWSYNC_ON_SMP |
14cf11af PM |
315 | "1: ldarx %0,0,%2 # __cmpxchg_u64\n\ |
316 | cmpd 0,%0,%3\n\ | |
317 | bne- 2f\n\ | |
318 | stdcx. %4,0,%2\n\ | |
319 | bne- 1b" | |
320 | ISYNC_ON_SMP | |
321 | "\n\ | |
322 | 2:" | |
323 | : "=&r" (prev), "=m" (*p) | |
324 | : "r" (p), "r" (old), "r" (new), "m" (*p) | |
325 | : "cc", "memory"); | |
326 | ||
327 | return prev; | |
328 | } | |
329 | #endif | |
330 | ||
331 | /* This function doesn't exist, so you'll get a linker error | |
332 | if something tries to do an invalid cmpxchg(). */ | |
333 | extern void __cmpxchg_called_with_bad_pointer(void); | |
334 | ||
335 | static __inline__ unsigned long | |
336 | __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, | |
337 | unsigned int size) | |
338 | { | |
339 | switch (size) { | |
340 | case 4: | |
341 | return __cmpxchg_u32(ptr, old, new); | |
342 | #ifdef CONFIG_PPC64 | |
343 | case 8: | |
344 | return __cmpxchg_u64(ptr, old, new); | |
345 | #endif | |
346 | } | |
347 | __cmpxchg_called_with_bad_pointer(); | |
348 | return old; | |
349 | } | |
350 | ||
351 | #define cmpxchg(ptr,o,n) \ | |
352 | ({ \ | |
353 | __typeof__(*(ptr)) _o_ = (o); \ | |
354 | __typeof__(*(ptr)) _n_ = (n); \ | |
355 | (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ | |
356 | (unsigned long)_n_, sizeof(*(ptr))); \ | |
357 | }) | |
358 | ||
359 | #ifdef CONFIG_PPC64 | |
360 | /* | |
361 | * We handle most unaligned accesses in hardware. On the other hand | |
362 | * unaligned DMA can be very expensive on some ppc64 IO chips (it does | |
363 | * powers of 2 writes until it reaches sufficient alignment). | |
364 | * | |
365 | * Based on this we disable the IP header alignment in network drivers. | |
366 | */ | |
367 | #define NET_IP_ALIGN 0 | |
368 | #endif | |
369 | ||
370 | #define arch_align_stack(x) (x) | |
371 | ||
9b6b563c | 372 | /* Used in very early kernel initialization. */ |
cabb5587 | 373 | extern unsigned long reloc_offset(void); |
9b6b563c PM |
374 | extern unsigned long add_reloc_offset(unsigned long); |
375 | extern void reloc_got2(unsigned long); | |
376 | ||
377 | #define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x))) | |
cabb5587 | 378 | |
c87ef117 ME |
379 | static inline void create_instruction(unsigned long addr, unsigned int instr) |
380 | { | |
381 | unsigned int *p; | |
382 | p = (unsigned int *)addr; | |
383 | *p = instr; | |
384 | asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p)); | |
385 | } | |
386 | ||
387 | /* Flags for create_branch: | |
388 | * "b" == create_branch(addr, target, 0); | |
389 | * "ba" == create_branch(addr, target, BRANCH_ABSOLUTE); | |
390 | * "bl" == create_branch(addr, target, BRANCH_SET_LINK); | |
391 | * "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK); | |
392 | */ | |
393 | #define BRANCH_SET_LINK 0x1 | |
394 | #define BRANCH_ABSOLUTE 0x2 | |
395 | ||
396 | static inline void create_branch(unsigned long addr, | |
397 | unsigned long target, int flags) | |
398 | { | |
399 | unsigned int instruction; | |
400 | ||
401 | if (! (flags & BRANCH_ABSOLUTE)) | |
402 | target = target - addr; | |
403 | ||
404 | /* Mask out the flags and target, so they don't step on each other. */ | |
405 | instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC); | |
406 | ||
407 | create_instruction(addr, instruction); | |
408 | } | |
409 | ||
410 | static inline void create_function_call(unsigned long addr, void * func) | |
411 | { | |
412 | unsigned long func_addr; | |
413 | ||
414 | #ifdef CONFIG_PPC64 | |
415 | /* | |
416 | * On PPC64 the function pointer actually points to the function's | |
417 | * descriptor. The first entry in the descriptor is the address | |
418 | * of the function text. | |
419 | */ | |
420 | func_addr = *(unsigned long *)func; | |
421 | #else | |
422 | func_addr = (unsigned long)func; | |
423 | #endif | |
424 | create_branch(addr, func_addr, BRANCH_SET_LINK); | |
425 | } | |
426 | ||
c6622f63 PM |
427 | #ifdef CONFIG_VIRT_CPU_ACCOUNTING |
428 | extern void account_system_vtime(struct task_struct *); | |
429 | #endif | |
430 | ||
14cf11af | 431 | #endif /* __KERNEL__ */ |
bbeb3f4c | 432 | #endif /* _ASM_POWERPC_SYSTEM_H */ |