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14cf11af PM |
1 | /* |
2 | * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> | |
3 | */ | |
bbeb3f4c SR |
4 | #ifndef _ASM_POWERPC_SYSTEM_H |
5 | #define _ASM_POWERPC_SYSTEM_H | |
14cf11af PM |
6 | |
7 | #include <linux/config.h> | |
8 | #include <linux/kernel.h> | |
9 | ||
10 | #include <asm/hw_irq.h> | |
11 | #include <asm/ppc_asm.h> | |
40ef8cbc | 12 | #include <asm/atomic.h> |
14cf11af PM |
13 | |
14 | /* | |
15 | * Memory barrier. | |
16 | * The sync instruction guarantees that all memory accesses initiated | |
17 | * by this processor have been performed (with respect to all other | |
18 | * mechanisms that access memory). The eieio instruction is a barrier | |
19 | * providing an ordering (separately) for (a) cacheable stores and (b) | |
20 | * loads and stores to non-cacheable memory (e.g. I/O devices). | |
21 | * | |
22 | * mb() prevents loads and stores being reordered across this point. | |
23 | * rmb() prevents loads being reordered across this point. | |
24 | * wmb() prevents stores being reordered across this point. | |
25 | * read_barrier_depends() prevents data-dependent loads being reordered | |
26 | * across this point (nop on PPC). | |
27 | * | |
28 | * We have to use the sync instructions for mb(), since lwsync doesn't | |
29 | * order loads with respect to previous stores. Lwsync is fine for | |
30 | * rmb(), though. Note that lwsync is interpreted as sync by | |
31 | * 32-bit and older 64-bit CPUs. | |
32 | * | |
33 | * For wmb(), we use sync since wmb is used in drivers to order | |
34 | * stores to system memory with respect to writes to the device. | |
35 | * However, smp_wmb() can be a lighter-weight eieio barrier on | |
36 | * SMP since it is only used to order updates to system memory. | |
37 | */ | |
38 | #define mb() __asm__ __volatile__ ("sync" : : : "memory") | |
39 | #define rmb() __asm__ __volatile__ ("lwsync" : : : "memory") | |
40 | #define wmb() __asm__ __volatile__ ("sync" : : : "memory") | |
41 | #define read_barrier_depends() do { } while(0) | |
42 | ||
43 | #define set_mb(var, value) do { var = value; mb(); } while (0) | |
44 | #define set_wmb(var, value) do { var = value; wmb(); } while (0) | |
45 | ||
46 | #ifdef CONFIG_SMP | |
47 | #define smp_mb() mb() | |
48 | #define smp_rmb() rmb() | |
49 | #define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory") | |
50 | #define smp_read_barrier_depends() read_barrier_depends() | |
51 | #else | |
52 | #define smp_mb() barrier() | |
53 | #define smp_rmb() barrier() | |
54 | #define smp_wmb() barrier() | |
55 | #define smp_read_barrier_depends() do { } while(0) | |
56 | #endif /* CONFIG_SMP */ | |
57 | ||
58 | #ifdef __KERNEL__ | |
59 | struct task_struct; | |
60 | struct pt_regs; | |
61 | ||
62 | #ifdef CONFIG_DEBUGGER | |
63 | ||
64 | extern int (*__debugger)(struct pt_regs *regs); | |
65 | extern int (*__debugger_ipi)(struct pt_regs *regs); | |
66 | extern int (*__debugger_bpt)(struct pt_regs *regs); | |
67 | extern int (*__debugger_sstep)(struct pt_regs *regs); | |
68 | extern int (*__debugger_iabr_match)(struct pt_regs *regs); | |
69 | extern int (*__debugger_dabr_match)(struct pt_regs *regs); | |
70 | extern int (*__debugger_fault_handler)(struct pt_regs *regs); | |
71 | ||
72 | #define DEBUGGER_BOILERPLATE(__NAME) \ | |
73 | static inline int __NAME(struct pt_regs *regs) \ | |
74 | { \ | |
75 | if (unlikely(__ ## __NAME)) \ | |
76 | return __ ## __NAME(regs); \ | |
77 | return 0; \ | |
78 | } | |
79 | ||
80 | DEBUGGER_BOILERPLATE(debugger) | |
81 | DEBUGGER_BOILERPLATE(debugger_ipi) | |
82 | DEBUGGER_BOILERPLATE(debugger_bpt) | |
83 | DEBUGGER_BOILERPLATE(debugger_sstep) | |
84 | DEBUGGER_BOILERPLATE(debugger_iabr_match) | |
85 | DEBUGGER_BOILERPLATE(debugger_dabr_match) | |
86 | DEBUGGER_BOILERPLATE(debugger_fault_handler) | |
87 | ||
88 | #ifdef CONFIG_XMON | |
89 | extern void xmon_init(int enable); | |
90 | #endif | |
91 | ||
92 | #else | |
93 | static inline int debugger(struct pt_regs *regs) { return 0; } | |
94 | static inline int debugger_ipi(struct pt_regs *regs) { return 0; } | |
95 | static inline int debugger_bpt(struct pt_regs *regs) { return 0; } | |
96 | static inline int debugger_sstep(struct pt_regs *regs) { return 0; } | |
97 | static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; } | |
98 | static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; } | |
99 | static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; } | |
100 | #endif | |
101 | ||
102 | extern int set_dabr(unsigned long dabr); | |
103 | extern void print_backtrace(unsigned long *); | |
104 | extern void show_regs(struct pt_regs * regs); | |
105 | extern void flush_instruction_cache(void); | |
106 | extern void hard_reset_now(void); | |
107 | extern void poweroff_now(void); | |
108 | ||
109 | #ifdef CONFIG_6xx | |
110 | extern long _get_L2CR(void); | |
111 | extern long _get_L3CR(void); | |
112 | extern void _set_L2CR(unsigned long); | |
113 | extern void _set_L3CR(unsigned long); | |
114 | #else | |
115 | #define _get_L2CR() 0L | |
116 | #define _get_L3CR() 0L | |
117 | #define _set_L2CR(val) do { } while(0) | |
118 | #define _set_L3CR(val) do { } while(0) | |
119 | #endif | |
120 | ||
121 | extern void via_cuda_init(void); | |
14cf11af PM |
122 | extern void read_rtc_time(void); |
123 | extern void pmac_find_display(void); | |
124 | extern void giveup_fpu(struct task_struct *); | |
cabb5587 | 125 | extern void disable_kernel_fp(void); |
14cf11af PM |
126 | extern void enable_kernel_fp(void); |
127 | extern void flush_fp_to_thread(struct task_struct *); | |
128 | extern void enable_kernel_altivec(void); | |
129 | extern void giveup_altivec(struct task_struct *); | |
130 | extern void load_up_altivec(struct task_struct *); | |
40ef8cbc | 131 | extern int emulate_altivec(struct pt_regs *); |
14cf11af PM |
132 | extern void giveup_spe(struct task_struct *); |
133 | extern void load_up_spe(struct task_struct *); | |
134 | extern int fix_alignment(struct pt_regs *); | |
25c8a78b DG |
135 | extern void cvt_fd(float *from, double *to, struct thread_struct *thread); |
136 | extern void cvt_df(double *from, float *to, struct thread_struct *thread); | |
14cf11af PM |
137 | |
138 | #ifdef CONFIG_ALTIVEC | |
139 | extern void flush_altivec_to_thread(struct task_struct *); | |
140 | #else | |
141 | static inline void flush_altivec_to_thread(struct task_struct *t) | |
142 | { | |
143 | } | |
144 | #endif | |
145 | ||
146 | #ifdef CONFIG_SPE | |
147 | extern void flush_spe_to_thread(struct task_struct *); | |
148 | #else | |
149 | static inline void flush_spe_to_thread(struct task_struct *t) | |
150 | { | |
151 | } | |
152 | #endif | |
153 | ||
154 | extern int call_rtas(const char *, int, int, unsigned long *, ...); | |
155 | extern void cacheable_memzero(void *p, unsigned int nb); | |
156 | extern void *cacheable_memcpy(void *, const void *, unsigned int); | |
157 | extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long); | |
158 | extern void bad_page_fault(struct pt_regs *, unsigned long, int); | |
159 | extern int die(const char *, struct pt_regs *, long); | |
160 | extern void _exception(int, struct pt_regs *, int, unsigned long); | |
161 | #ifdef CONFIG_BOOKE_WDT | |
162 | extern u32 booke_wdt_enabled; | |
163 | extern u32 booke_wdt_period; | |
164 | #endif /* CONFIG_BOOKE_WDT */ | |
165 | ||
166 | /* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */ | |
167 | extern unsigned char e2a(unsigned char); | |
168 | ||
169 | struct device_node; | |
170 | extern void note_scsi_host(struct device_node *, void *); | |
171 | ||
172 | extern struct task_struct *__switch_to(struct task_struct *, | |
173 | struct task_struct *); | |
174 | #define switch_to(prev, next, last) ((last) = __switch_to((prev), (next))) | |
175 | ||
176 | struct thread_struct; | |
177 | extern struct task_struct *_switch(struct thread_struct *prev, | |
178 | struct thread_struct *next); | |
179 | ||
180 | extern unsigned int rtas_data; | |
40ef8cbc | 181 | extern int mem_init_done; /* set on boot once kmalloc can be called */ |
14cf11af | 182 | |
17a6392d PM |
183 | extern int powersave_nap; /* set if nap mode can be used in idle loop */ |
184 | ||
14cf11af PM |
185 | /* |
186 | * Atomic exchange | |
187 | * | |
188 | * Changes the memory location '*ptr' to be val and returns | |
189 | * the previous value stored there. | |
190 | */ | |
191 | static __inline__ unsigned long | |
192 | __xchg_u32(volatile void *p, unsigned long val) | |
193 | { | |
194 | unsigned long prev; | |
195 | ||
196 | __asm__ __volatile__( | |
197 | EIEIO_ON_SMP | |
198 | "1: lwarx %0,0,%2 \n" | |
199 | PPC405_ERR77(0,%2) | |
200 | " stwcx. %3,0,%2 \n\ | |
201 | bne- 1b" | |
202 | ISYNC_ON_SMP | |
203 | : "=&r" (prev), "=m" (*(volatile unsigned int *)p) | |
204 | : "r" (p), "r" (val), "m" (*(volatile unsigned int *)p) | |
205 | : "cc", "memory"); | |
206 | ||
207 | return prev; | |
208 | } | |
209 | ||
210 | #ifdef CONFIG_PPC64 | |
211 | static __inline__ unsigned long | |
212 | __xchg_u64(volatile void *p, unsigned long val) | |
213 | { | |
214 | unsigned long prev; | |
215 | ||
216 | __asm__ __volatile__( | |
217 | EIEIO_ON_SMP | |
218 | "1: ldarx %0,0,%2 \n" | |
219 | PPC405_ERR77(0,%2) | |
220 | " stdcx. %3,0,%2 \n\ | |
221 | bne- 1b" | |
222 | ISYNC_ON_SMP | |
223 | : "=&r" (prev), "=m" (*(volatile unsigned long *)p) | |
224 | : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p) | |
225 | : "cc", "memory"); | |
226 | ||
227 | return prev; | |
228 | } | |
229 | #endif | |
230 | ||
231 | /* | |
232 | * This function doesn't exist, so you'll get a linker error | |
233 | * if something tries to do an invalid xchg(). | |
234 | */ | |
235 | extern void __xchg_called_with_bad_pointer(void); | |
236 | ||
237 | static __inline__ unsigned long | |
238 | __xchg(volatile void *ptr, unsigned long x, unsigned int size) | |
239 | { | |
240 | switch (size) { | |
241 | case 4: | |
242 | return __xchg_u32(ptr, x); | |
243 | #ifdef CONFIG_PPC64 | |
244 | case 8: | |
245 | return __xchg_u64(ptr, x); | |
246 | #endif | |
247 | } | |
248 | __xchg_called_with_bad_pointer(); | |
249 | return x; | |
250 | } | |
251 | ||
252 | #define xchg(ptr,x) \ | |
253 | ({ \ | |
254 | __typeof__(*(ptr)) _x_ = (x); \ | |
255 | (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \ | |
256 | }) | |
257 | ||
258 | #define tas(ptr) (xchg((ptr),1)) | |
259 | ||
260 | /* | |
261 | * Compare and exchange - if *p == old, set it to new, | |
262 | * and return the old value of *p. | |
263 | */ | |
264 | #define __HAVE_ARCH_CMPXCHG 1 | |
265 | ||
266 | static __inline__ unsigned long | |
267 | __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new) | |
268 | { | |
269 | unsigned int prev; | |
270 | ||
271 | __asm__ __volatile__ ( | |
272 | EIEIO_ON_SMP | |
273 | "1: lwarx %0,0,%2 # __cmpxchg_u32\n\ | |
274 | cmpw 0,%0,%3\n\ | |
275 | bne- 2f\n" | |
276 | PPC405_ERR77(0,%2) | |
277 | " stwcx. %4,0,%2\n\ | |
278 | bne- 1b" | |
279 | ISYNC_ON_SMP | |
280 | "\n\ | |
281 | 2:" | |
282 | : "=&r" (prev), "=m" (*p) | |
283 | : "r" (p), "r" (old), "r" (new), "m" (*p) | |
284 | : "cc", "memory"); | |
285 | ||
286 | return prev; | |
287 | } | |
288 | ||
289 | #ifdef CONFIG_PPC64 | |
290 | static __inline__ unsigned long | |
291 | __cmpxchg_u64(volatile long *p, unsigned long old, unsigned long new) | |
292 | { | |
293 | unsigned long prev; | |
294 | ||
295 | __asm__ __volatile__ ( | |
296 | EIEIO_ON_SMP | |
297 | "1: ldarx %0,0,%2 # __cmpxchg_u64\n\ | |
298 | cmpd 0,%0,%3\n\ | |
299 | bne- 2f\n\ | |
300 | stdcx. %4,0,%2\n\ | |
301 | bne- 1b" | |
302 | ISYNC_ON_SMP | |
303 | "\n\ | |
304 | 2:" | |
305 | : "=&r" (prev), "=m" (*p) | |
306 | : "r" (p), "r" (old), "r" (new), "m" (*p) | |
307 | : "cc", "memory"); | |
308 | ||
309 | return prev; | |
310 | } | |
311 | #endif | |
312 | ||
313 | /* This function doesn't exist, so you'll get a linker error | |
314 | if something tries to do an invalid cmpxchg(). */ | |
315 | extern void __cmpxchg_called_with_bad_pointer(void); | |
316 | ||
317 | static __inline__ unsigned long | |
318 | __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, | |
319 | unsigned int size) | |
320 | { | |
321 | switch (size) { | |
322 | case 4: | |
323 | return __cmpxchg_u32(ptr, old, new); | |
324 | #ifdef CONFIG_PPC64 | |
325 | case 8: | |
326 | return __cmpxchg_u64(ptr, old, new); | |
327 | #endif | |
328 | } | |
329 | __cmpxchg_called_with_bad_pointer(); | |
330 | return old; | |
331 | } | |
332 | ||
333 | #define cmpxchg(ptr,o,n) \ | |
334 | ({ \ | |
335 | __typeof__(*(ptr)) _o_ = (o); \ | |
336 | __typeof__(*(ptr)) _n_ = (n); \ | |
337 | (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ | |
338 | (unsigned long)_n_, sizeof(*(ptr))); \ | |
339 | }) | |
340 | ||
341 | #ifdef CONFIG_PPC64 | |
342 | /* | |
343 | * We handle most unaligned accesses in hardware. On the other hand | |
344 | * unaligned DMA can be very expensive on some ppc64 IO chips (it does | |
345 | * powers of 2 writes until it reaches sufficient alignment). | |
346 | * | |
347 | * Based on this we disable the IP header alignment in network drivers. | |
348 | */ | |
349 | #define NET_IP_ALIGN 0 | |
350 | #endif | |
351 | ||
352 | #define arch_align_stack(x) (x) | |
353 | ||
9b6b563c | 354 | /* Used in very early kernel initialization. */ |
cabb5587 | 355 | extern unsigned long reloc_offset(void); |
9b6b563c PM |
356 | extern unsigned long add_reloc_offset(unsigned long); |
357 | extern void reloc_got2(unsigned long); | |
358 | ||
359 | #define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x))) | |
cabb5587 | 360 | |
14cf11af | 361 | #endif /* __KERNEL__ */ |
bbeb3f4c | 362 | #endif /* _ASM_POWERPC_SYSTEM_H */ |