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[CELL] oprofile: add support to OProfile for profiling CELL BE SPUs
[linux-2.6-block.git] / include / asm-powerpc / spu.h
CommitLineData
67207b96
AB		 1/*
2 * SPU core / file system interface and HW structures
3 *
4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
5 *
6 * Author: Arnd Bergmann <arndb@de.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _SPU_H
24#define _SPU_H
88ced031
AB		 25#ifdef __KERNEL__
26
67207b96 27#include <linux/workqueue.h>
1d64093f 28#include <linux/sysdev.h>
67207b96 29
aeb01377 30#define LS_SIZE (256 * 1024)
5473af04
MN		 31#define LS_ADDR_MASK (LS_SIZE - 1)
32
33#define MFC_PUT_CMD 0x20
34#define MFC_PUTS_CMD 0x28
35#define MFC_PUTR_CMD 0x30
36#define MFC_PUTF_CMD 0x22
37#define MFC_PUTB_CMD 0x21
38#define MFC_PUTFS_CMD 0x2A
39#define MFC_PUTBS_CMD 0x29
40#define MFC_PUTRF_CMD 0x32
41#define MFC_PUTRB_CMD 0x31
42#define MFC_PUTL_CMD 0x24
43#define MFC_PUTRL_CMD 0x34
44#define MFC_PUTLF_CMD 0x26
45#define MFC_PUTLB_CMD 0x25
46#define MFC_PUTRLF_CMD 0x36
47#define MFC_PUTRLB_CMD 0x35
48
49#define MFC_GET_CMD 0x40
50#define MFC_GETS_CMD 0x48
51#define MFC_GETF_CMD 0x42
52#define MFC_GETB_CMD 0x41
53#define MFC_GETFS_CMD 0x4A
54#define MFC_GETBS_CMD 0x49
55#define MFC_GETL_CMD 0x44
56#define MFC_GETLF_CMD 0x46
57#define MFC_GETLB_CMD 0x45
58
59#define MFC_SDCRT_CMD 0x80
60#define MFC_SDCRTST_CMD 0x81
61#define MFC_SDCRZ_CMD 0x89
62#define MFC_SDCRS_CMD 0x8D
63#define MFC_SDCRF_CMD 0x8F
64
65#define MFC_GETLLAR_CMD 0xD0
66#define MFC_PUTLLC_CMD 0xB4
67#define MFC_PUTLLUC_CMD 0xB0
68#define MFC_PUTQLLUC_CMD 0xB8
69#define MFC_SNDSIG_CMD 0xA0
70#define MFC_SNDSIGB_CMD 0xA1
71#define MFC_SNDSIGF_CMD 0xA2
72#define MFC_BARRIER_CMD 0xC0
73#define MFC_EIEIO_CMD 0xC8
74#define MFC_SYNC_CMD 0xCC
75
76#define MFC_MIN_DMA_SIZE_SHIFT 4 /* 16 bytes */
77#define MFC_MAX_DMA_SIZE_SHIFT 14 /* 16384 bytes */
78#define MFC_MIN_DMA_SIZE (1 << MFC_MIN_DMA_SIZE_SHIFT)
79#define MFC_MAX_DMA_SIZE (1 << MFC_MAX_DMA_SIZE_SHIFT)
80#define MFC_MIN_DMA_SIZE_MASK (MFC_MIN_DMA_SIZE - 1)
81#define MFC_MAX_DMA_SIZE_MASK (MFC_MAX_DMA_SIZE - 1)
82#define MFC_MIN_DMA_LIST_SIZE 0x0008 /* 8 bytes */
83#define MFC_MAX_DMA_LIST_SIZE 0x4000 /* 16K bytes */
84
85#define MFC_TAGID_TO_TAGMASK(tag_id) (1 << (tag_id & 0x1F))
86
87/* Events for Channels 0-2 */
88#define MFC_DMA_TAG_STATUS_UPDATE_EVENT 0x00000001
89#define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT 0x00000002
90#define MFC_DMA_QUEUE_AVAILABLE_EVENT 0x00000008
91#define MFC_SPU_MAILBOX_WRITTEN_EVENT 0x00000010
92#define MFC_DECREMENTER_EVENT 0x00000020
93#define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT 0x00000040
94#define MFC_PU_MAILBOX_AVAILABLE_EVENT 0x00000080
95#define MFC_SIGNAL_2_EVENT 0x00000100
96#define MFC_SIGNAL_1_EVENT 0x00000200
97#define MFC_LLR_LOST_EVENT 0x00000400
98#define MFC_PRIV_ATTN_EVENT 0x00000800
99#define MFC_MULTI_SRC_EVENT 0x00001000
100
101/* Flags indicating progress during context switch. */
8837d921
AB		 102#define SPU_CONTEXT_SWITCH_PENDING 0UL
103#define SPU_CONTEXT_SWITCH_ACTIVE 1UL
67207b96 104
8b3d6663
AB		 105struct spu_context;
106struct spu_runqueue;
c9868fe0 107struct device_node;
8b3d6663 108
fe2f896d 109enum spu_utilization_state {
fe2f896d 110 SPU_UTIL_USER,
27ec41d3 111 SPU_UTIL_SYSTEM,
fe2f896d 112 SPU_UTIL_IOWAIT,
27ec41d3 113 SPU_UTIL_IDLE_LOADED,
fe2f896d
CH		 114 SPU_UTIL_MAX
115};
116
67207b96 117struct spu {
c61c27d5 118 const char *name;
67207b96
AB		 119 unsigned long local_store_phys;
120 u8 *local_store;
6df10a82 121 unsigned long problem_phys;
67207b96 122 struct spu_problem __iomem *problem;
67207b96
AB		 123 struct spu_priv2 __iomem *priv2;
124 struct list_head list;
aa6d5b20 125 struct list_head cbe_list;
8b3d6663 126 struct list_head sched_list;
e570beb6 127 struct list_head full_list;
67207b96 128 int number;
0ebfff14 129 unsigned int irqs[3];
67207b96 130 u32 node;
5473af04 131 u64 flags;
8b3d6663
AB		 132 u64 dar;
133 u64 dsisr;
67207b96
AB		 134 size_t ls_size;
135 unsigned int slb_replace;
136 struct mm_struct *mm;
8b3d6663
AB		 137 struct spu_context *ctx;
138 struct spu_runqueue *rq;
2a911f0b 139 unsigned long long timestamp;
8b3d6663 140 pid_t pid;
1474855d 141 pid_t tgid;
67207b96
AB		 142 int class_0_pending;
143 spinlock_t register_lock;
144
8b3d6663
AB		 145 void (* wbox_callback)(struct spu *spu);
146 void (* ibox_callback)(struct spu *spu);
5110459f 147 void (* stop_callback)(struct spu *spu);
a33a7d73 148 void (* mfc_callback)(struct spu *spu);
9add11da 149 void (* dma_callback)(struct spu *spu, int type);
67207b96
AB		 150
151 char irq_c0[8];
152 char irq_c1[8];
153 char irq_c2[8];
1d64093f 154
c9868fe0
IK		 155 u64 spe_id;
156
e28b0031 157 void* pdata; /* platform private data */
c9868fe0
IK		 158
159 /* of based platforms only */
160 struct device_node *devnode;
161
162 /* native only */
163 struct spu_priv1 __iomem *priv1;
164
165 /* beat only */
166 u64 shadow_int_mask_RW[3];
167
1d64093f 168 struct sys_device sysdev;
e9f8a0b6 169
9d92af62
AB		 170 int has_mem_affinity;
171 struct list_head aff_list;
172
e9f8a0b6
CH		 173 struct {
174 /* protected by interrupt reentrancy */
27ec41d3
AD		 175 enum spu_utilization_state util_state;
176 unsigned long long tstamp;
177 unsigned long long times[SPU_UTIL_MAX];
fe2f896d
CH		 178 unsigned long long vol_ctx_switch;
179 unsigned long long invol_ctx_switch;
180 unsigned long long min_flt;
181 unsigned long long maj_flt;
182 unsigned long long hash_flt;
e9f8a0b6
CH		 183 unsigned long long slb_flt;
184 unsigned long long class2_intr;
fe2f896d 185 unsigned long long libassist;
e9f8a0b6 186 } stats;
67207b96
AB		 187};
188
aa6d5b20
AB		 189struct cbe_spu_info {
190 struct list_head spus;
191 struct list_head free_spus;
192 int n_spus;
193 atomic_t reserved_spus;
194};
195
196extern struct cbe_spu_info cbe_spu_info[];
197
67207b96 198struct spu *spu_alloc(void);
a68cf983 199struct spu *spu_alloc_node(int node);
8e68e2f2 200struct spu *spu_alloc_spu(struct spu *spu);
67207b96 201void spu_free(struct spu *spu);
5110459f
AB		 202int spu_irq_class_0_bottom(struct spu *spu);
203int spu_irq_class_1_bottom(struct spu *spu);
2fb9d206 204void spu_irq_setaffinity(struct spu *spu, int cpu);
67207b96 205
8d2655e6
AD		 206#ifdef CONFIG_KEXEC
207void crash_register_spus(struct list_head *list);
208#else
209static inline void crash_register_spus(struct list_head *list)
210{
211}
212#endif
213
94b2a439
BH		 214extern void spu_invalidate_slbs(struct spu *spu);
215extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
216
217/* Calls from the memory management to the SPU */
218struct mm_struct;
219extern void spu_flush_all_slbs(struct mm_struct *mm);
220
1474855d
BN		 221/* This interface allows a profiler (e.g., OProfile) to store a ref
222 * to spu context information that it creates. This caching technique
223 * avoids the need to recreate this information after a save/restore operation.
224 *
225 * Assumes the caller has already incremented the ref count to
226 * profile_info; then spu_context_destroy must call kref_put
227 * on prof_info_kref.
228 */
229void spu_set_profile_private_kref(struct spu_context *ctx,
230 struct kref *prof_info_kref,
231 void ( * prof_info_release) (struct kref *kref));
232
233void *spu_get_profile_private_kref(struct spu_context *ctx);
234
2dd14934
AB		 235/* system callbacks from the SPU */
236struct spu_syscall_block {
237 u64 nr_ret;
238 u64 parm[6];
239};
240extern long spu_sys_callback(struct spu_syscall_block *s);
241
242/* syscalls implemented in spufs */
f1fa16e8 243struct file;
67207b96
AB		 244extern struct spufs_calls {
245 asmlinkage long (*create_thread)(const char __user *name,
8e68e2f2
AB		 246 unsigned int flags, mode_t mode,
247 struct file *neighbor);
67207b96
AB		 248 asmlinkage long (*spu_run)(struct file *filp, __u32 __user *unpc,
249 __u32 __user *ustatus);
250 struct module *owner;
251} spufs_calls;
252
bf1ab978
DGM		 253/* coredump calls implemented in spufs */
254struct spu_coredump_calls {
255 asmlinkage int (*arch_notes_size)(void);
256 asmlinkage void (*arch_write_notes)(struct file *file);
257 struct module *owner;
258};
259
9add11da
AB		 260/* return status from spu_run, same as in libspe */
261#define SPE_EVENT_DMA_ALIGNMENT 0x0008 /*A DMA alignment error */
262#define SPE_EVENT_SPE_ERROR 0x0010 /*An illegal instruction error*/
263#define SPE_EVENT_SPE_DATA_SEGMENT 0x0020 /*A DMA segmentation error */
264#define SPE_EVENT_SPE_DATA_STORAGE 0x0040 /*A DMA storage error */
265#define SPE_EVENT_INVALID_DMA 0x0800 /* Invalid MFC DMA */
266
267/*
268 * Flags for sys_spu_create.
269 */
270#define SPU_CREATE_EVENTS_ENABLED 0x0001
6263203e 271#define SPU_CREATE_GANG 0x0002
5737edd1
MN		 272#define SPU_CREATE_NOSCHED 0x0004
273#define SPU_CREATE_ISOLATE 0x0008
8e68e2f2
AB		 274#define SPU_CREATE_AFFINITY_SPU 0x0010
275#define SPU_CREATE_AFFINITY_MEM 0x0020
6263203e 276
8e68e2f2 277#define SPU_CREATE_FLAG_ALL 0x003f /* mask of all valid flags */
6263203e 278
9add11da 279
67207b96
AB		 280#ifdef CONFIG_SPU_FS_MODULE
281int register_spu_syscalls(struct spufs_calls *calls);
282void unregister_spu_syscalls(struct spufs_calls *calls);
283#else
284static inline int register_spu_syscalls(struct spufs_calls *calls)
285{
286 return 0;
287}
288static inline void unregister_spu_syscalls(struct spufs_calls *calls)
289{
290}
291#endif /* MODULE */
292
bf1ab978
DGM		 293int register_arch_coredump_calls(struct spu_coredump_calls *calls);
294void unregister_arch_coredump_calls(struct spu_coredump_calls *calls);
295
e570beb6
CK		 296int spu_add_sysdev_attr(struct sysdev_attribute *attr);
297void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
298
299int spu_add_sysdev_attr_group(struct attribute_group *attrs);
300void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
301
67207b96 302
86767277
AB		 303/*
304 * Notifier blocks:
305 *
306 * oprofile can get notified when a context switch is performed
307 * on an spe. The notifer function that gets called is passed
308 * a pointer to the SPU structure as well as the object-id that
309 * identifies the binary running on that SPU now.
310 *
311 * For a context save, the object-id that is passed is zero,
312 * identifying that the kernel will run from that moment on.
313 *
314 * For a context restore, the object-id is the value written
315 * to object-id spufs file from user space and the notifer
316 * function can assume that spu->ctx is valid.
317 */
f1fa16e8 318struct notifier_block;
86767277
AB		 319int spu_switch_event_register(struct notifier_block * n);
320int spu_switch_event_unregister(struct notifier_block * n);
321
67207b96
AB		 322/*
323 * This defines the Local Store, Problem Area and Privlege Area of an SPU.
324 */
325
326union mfc_tag_size_class_cmd {
327 struct {
328 u16 mfc_size;
329 u16 mfc_tag;
330 u8 pad;
331 u8 mfc_rclassid;
332 u16 mfc_cmd;
333 } u;
334 struct {
335 u32 mfc_size_tag32;
336 u32 mfc_class_cmd32;
337 } by32;
338 u64 all64;
339};
340
341struct mfc_cq_sr {
342 u64 mfc_cq_data0_RW;
343 u64 mfc_cq_data1_RW;
344 u64 mfc_cq_data2_RW;
345 u64 mfc_cq_data3_RW;
346};
347
348struct spu_problem {
349#define MS_SYNC_PENDING 1L
350 u64 spc_mssync_RW; /* 0x0000 */
351 u8 pad_0x0008_0x3000[0x3000 - 0x0008];
352
353 /* DMA Area */
354 u8 pad_0x3000_0x3004[0x4]; /* 0x3000 */
355 u32 mfc_lsa_W; /* 0x3004 */
356 u64 mfc_ea_W; /* 0x3008 */
357 union mfc_tag_size_class_cmd mfc_union_W; /* 0x3010 */
358 u8 pad_0x3018_0x3104[0xec]; /* 0x3018 */
359 u32 dma_qstatus_R; /* 0x3104 */
360 u8 pad_0x3108_0x3204[0xfc]; /* 0x3108 */
361 u32 dma_querytype_RW; /* 0x3204 */
362 u8 pad_0x3208_0x321c[0x14]; /* 0x3208 */
363 u32 dma_querymask_RW; /* 0x321c */
364 u8 pad_0x3220_0x322c[0xc]; /* 0x3220 */
365 u32 dma_tagstatus_R; /* 0x322c */
366#define DMA_TAGSTATUS_INTR_ANY 1u
367#define DMA_TAGSTATUS_INTR_ALL 2u
368 u8 pad_0x3230_0x4000[0x4000 - 0x3230]; /* 0x3230 */
369
370 /* SPU Control Area */
371 u8 pad_0x4000_0x4004[0x4]; /* 0x4000 */
372 u32 pu_mb_R; /* 0x4004 */
373 u8 pad_0x4008_0x400c[0x4]; /* 0x4008 */
374 u32 spu_mb_W; /* 0x400c */
375 u8 pad_0x4010_0x4014[0x4]; /* 0x4010 */
376 u32 mb_stat_R; /* 0x4014 */
377 u8 pad_0x4018_0x401c[0x4]; /* 0x4018 */
378 u32 spu_runcntl_RW; /* 0x401c */
379#define SPU_RUNCNTL_STOP 0L
380#define SPU_RUNCNTL_RUNNABLE 1L
5737edd1 381#define SPU_RUNCNTL_ISOLATE 2L
67207b96
AB		 382 u8 pad_0x4020_0x4024[0x4]; /* 0x4020 */
383 u32 spu_status_R; /* 0x4024 */
384#define SPU_STOP_STATUS_SHIFT 16
385#define SPU_STATUS_STOPPED 0x0
386#define SPU_STATUS_RUNNING 0x1
387#define SPU_STATUS_STOPPED_BY_STOP 0x2
388#define SPU_STATUS_STOPPED_BY_HALT 0x4
389#define SPU_STATUS_WAITING_FOR_CHANNEL 0x8
390#define SPU_STATUS_SINGLE_STEP 0x10
391#define SPU_STATUS_INVALID_INSTR 0x20
392#define SPU_STATUS_INVALID_CH 0x40
393#define SPU_STATUS_ISOLATED_STATE 0x80
eb758ce5 394#define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
395#define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
67207b96
AB		 396 u8 pad_0x4028_0x402c[0x4]; /* 0x4028 */
397 u32 spu_spe_R; /* 0x402c */
398 u8 pad_0x4030_0x4034[0x4]; /* 0x4030 */
399 u32 spu_npc_RW; /* 0x4034 */
400 u8 pad_0x4038_0x14000[0x14000 - 0x4038]; /* 0x4038 */
401
402 /* Signal Notification Area */
403 u8 pad_0x14000_0x1400c[0xc]; /* 0x14000 */
404 u32 signal_notify1; /* 0x1400c */
405 u8 pad_0x14010_0x1c00c[0x7ffc]; /* 0x14010 */
406 u32 signal_notify2; /* 0x1c00c */
407} __attribute__ ((aligned(0x20000)));
408
409/* SPU Privilege 2 State Area */
410struct spu_priv2 {
411 /* MFC Registers */
412 u8 pad_0x0000_0x1100[0x1100 - 0x0000]; /* 0x0000 */
413
414 /* SLB Management Registers */
415 u8 pad_0x1100_0x1108[0x8]; /* 0x1100 */
416 u64 slb_index_W; /* 0x1108 */
417#define SLB_INDEX_MASK 0x7L
418 u64 slb_esid_RW; /* 0x1110 */
419 u64 slb_vsid_RW; /* 0x1118 */
420#define SLB_VSID_SUPERVISOR_STATE (0x1ull << 11)
421#define SLB_VSID_SUPERVISOR_STATE_MASK (0x1ull << 11)
422#define SLB_VSID_PROBLEM_STATE (0x1ull << 10)
423#define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10)
424#define SLB_VSID_EXECUTE_SEGMENT (0x1ull << 9)
425#define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9)
426#define SLB_VSID_EXECUTE_SEGMENT_MASK (0x1ull << 9)
427#define SLB_VSID_4K_PAGE (0x0 << 8)
428#define SLB_VSID_LARGE_PAGE (0x1ull << 8)
429#define SLB_VSID_PAGE_SIZE_MASK (0x1ull << 8)
430#define SLB_VSID_CLASS_MASK (0x1ull << 7)
431#define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
432 u64 slb_invalidate_entry_W; /* 0x1120 */
433 u64 slb_invalidate_all_W; /* 0x1128 */
434 u8 pad_0x1130_0x2000[0x2000 - 0x1130]; /* 0x1130 */
435
436 /* Context Save / Restore Area */
437 struct mfc_cq_sr spuq[16]; /* 0x2000 */
438 struct mfc_cq_sr puq[8]; /* 0x2200 */
439 u8 pad_0x2300_0x3000[0x3000 - 0x2300]; /* 0x2300 */
440
441 /* MFC Control */
442 u64 mfc_control_RW; /* 0x3000 */
443#define MFC_CNTL_RESUME_DMA_QUEUE (0ull << 0)
444#define MFC_CNTL_SUSPEND_DMA_QUEUE (1ull << 0)
445#define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK (1ull << 0)
49776d30 446#define MFC_CNTL_SUSPEND_MASK (1ull << 4)
67207b96
AB		 447#define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
448#define MFC_CNTL_SUSPEND_IN_PROGRESS (1ull << 8)
449#define MFC_CNTL_SUSPEND_COMPLETE (3ull << 8)
450#define MFC_CNTL_SUSPEND_DMA_STATUS_MASK (3ull << 8)
451#define MFC_CNTL_DMA_QUEUES_EMPTY (1ull << 14)
452#define MFC_CNTL_DMA_QUEUES_EMPTY_MASK (1ull << 14)
453#define MFC_CNTL_PURGE_DMA_REQUEST (1ull << 15)
454#define MFC_CNTL_PURGE_DMA_IN_PROGRESS (1ull << 24)
455#define MFC_CNTL_PURGE_DMA_COMPLETE (3ull << 24)
456#define MFC_CNTL_PURGE_DMA_STATUS_MASK (3ull << 24)
457#define MFC_CNTL_RESTART_DMA_COMMAND (1ull << 32)
458#define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING (1ull << 32)
459#define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
460#define MFC_CNTL_MFC_PRIVILEGE_STATE (2ull << 33)
461#define MFC_CNTL_MFC_PROBLEM_STATE (3ull << 33)
462#define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK (3ull << 33)
463#define MFC_CNTL_DECREMENTER_HALTED (1ull << 35)
464#define MFC_CNTL_DECREMENTER_RUNNING (1ull << 40)
465#define MFC_CNTL_DECREMENTER_STATUS_MASK (1ull << 40)
466 u8 pad_0x3008_0x4000[0x4000 - 0x3008]; /* 0x3008 */
467
468 /* Interrupt Mailbox */
469 u64 puint_mb_R; /* 0x4000 */
470 u8 pad_0x4008_0x4040[0x4040 - 0x4008]; /* 0x4008 */
471
472 /* SPU Control */
473 u64 spu_privcntl_RW; /* 0x4040 */
474#define SPU_PRIVCNTL_MODE_NORMAL (0x0ull << 0)
475#define SPU_PRIVCNTL_MODE_SINGLE_STEP (0x1ull << 0)
476#define SPU_PRIVCNTL_MODE_MASK (0x1ull << 0)
477#define SPU_PRIVCNTL_NO_ATTENTION_EVENT (0x0ull << 1)
478#define SPU_PRIVCNTL_ATTENTION_EVENT (0x1ull << 1)
479#define SPU_PRIVCNTL_ATTENTION_EVENT_MASK (0x1ull << 1)
480#define SPU_PRIVCNT_LOAD_REQUEST_NORMAL (0x0ull << 2)
481#define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK (0x1ull << 2)
482 u8 pad_0x4048_0x4058[0x10]; /* 0x4048 */
483 u64 spu_lslr_RW; /* 0x4058 */
484 u64 spu_chnlcntptr_RW; /* 0x4060 */
485 u64 spu_chnlcnt_RW; /* 0x4068 */
486 u64 spu_chnldata_RW; /* 0x4070 */
487 u64 spu_cfg_RW; /* 0x4078 */
488 u8 pad_0x4080_0x5000[0x5000 - 0x4080]; /* 0x4080 */
489
490 /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
491 u64 spu_pm_trace_tag_status_RW; /* 0x5000 */
492 u64 spu_tag_status_query_RW; /* 0x5008 */
493#define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
494#define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
495 u64 spu_cmd_buf1_RW; /* 0x5010 */
496#define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
497#define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
498 u64 spu_cmd_buf2_RW; /* 0x5018 */
499#define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
500#define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
501#define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
502 u64 spu_atomic_status_RW; /* 0x5020 */
503} __attribute__ ((aligned(0x20000)));
504
505/* SPU Privilege 1 State Area */
506struct spu_priv1 {
507 /* Control and Configuration Area */
508 u64 mfc_sr1_RW; /* 0x000 */
509#define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK 0x01ull
510#define MFC_STATE1_BUS_TLBIE_MASK 0x02ull
511#define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
512#define MFC_STATE1_PROBLEM_STATE_MASK 0x08ull
513#define MFC_STATE1_RELOCATE_MASK 0x10ull
514#define MFC_STATE1_MASTER_RUN_CONTROL_MASK 0x20ull
be703177 515#define MFC_STATE1_TABLE_SEARCH_MASK 0x40ull
67207b96
AB		 516 u64 mfc_lpid_RW; /* 0x008 */
517 u64 spu_idr_RW; /* 0x010 */
518 u64 mfc_vr_RO; /* 0x018 */
519#define MFC_VERSION_BITS (0xffff << 16)
520#define MFC_REVISION_BITS (0xffff)
521#define MFC_GET_VERSION_BITS(vr) (((vr) & MFC_VERSION_BITS) >> 16)
522#define MFC_GET_REVISION_BITS(vr) ((vr) & MFC_REVISION_BITS)
523 u64 spu_vr_RO; /* 0x020 */
524#define SPU_VERSION_BITS (0xffff << 16)
525#define SPU_REVISION_BITS (0xffff)
526#define SPU_GET_VERSION_BITS(vr) (vr & SPU_VERSION_BITS) >> 16
527#define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
528 u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */
529
67207b96 530 /* Interrupt Area */
f0831acc 531 u64 int_mask_RW[3]; /* 0x100 */
67207b96
AB		 532#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L
533#define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR 0x2L
534#define CLASS0_ENABLE_SPU_ERROR_INTR 0x4L
535#define CLASS0_ENABLE_MFC_FIR_INTR 0x8L
67207b96
AB		 536#define CLASS1_ENABLE_SEGMENT_FAULT_INTR 0x1L
537#define CLASS1_ENABLE_STORAGE_FAULT_INTR 0x2L
538#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
539#define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
67207b96
AB		 540#define CLASS2_ENABLE_MAILBOX_INTR 0x1L
541#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
542#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
543#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
544 u8 pad_0x118_0x140[0x28]; /* 0x118 */
f0831acc 545 u64 int_stat_RW[3]; /* 0x140 */
67207b96
AB		 546 u8 pad_0x158_0x180[0x28]; /* 0x158 */
547 u64 int_route_RW; /* 0x180 */
548
549 /* Interrupt Routing */
550 u8 pad_0x188_0x200[0x200 - 0x188]; /* 0x188 */
551
552 /* Atomic Unit Control Area */
553 u64 mfc_atomic_flush_RW; /* 0x200 */
554#define mfc_atomic_flush_enable 0x1L
555 u8 pad_0x208_0x280[0x78]; /* 0x208 */
556 u64 resource_allocation_groupID_RW; /* 0x280 */
557 u64 resource_allocation_enable_RW; /* 0x288 */
558 u8 pad_0x290_0x3c8[0x3c8 - 0x290]; /* 0x290 */
559
560 /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
561
562 u64 smf_sbi_signal_sel; /* 0x3c8 */
563#define smf_sbi_mask_lsb 56
564#define smf_sbi_shift (63 - smf_sbi_mask_lsb)
565#define smf_sbi_mask (0x301LL << smf_sbi_shift)
566#define smf_sbi_bus0_bits (0x001LL << smf_sbi_shift)
567#define smf_sbi_bus2_bits (0x100LL << smf_sbi_shift)
568#define smf_sbi2_bus0_bits (0x201LL << smf_sbi_shift)
569#define smf_sbi2_bus2_bits (0x300LL << smf_sbi_shift)
570 u64 smf_ato_signal_sel; /* 0x3d0 */
571#define smf_ato_mask_lsb 35
572#define smf_ato_shift (63 - smf_ato_mask_lsb)
573#define smf_ato_mask (0x3LL << smf_ato_shift)
574#define smf_ato_bus0_bits (0x2LL << smf_ato_shift)
575#define smf_ato_bus2_bits (0x1LL << smf_ato_shift)
576 u8 pad_0x3d8_0x400[0x400 - 0x3d8]; /* 0x3d8 */
577
578 /* TLB Management Registers */
579 u64 mfc_sdr_RW; /* 0x400 */
580 u8 pad_0x408_0x500[0xf8]; /* 0x408 */
581 u64 tlb_index_hint_RO; /* 0x500 */
582 u64 tlb_index_W; /* 0x508 */
583 u64 tlb_vpn_RW; /* 0x510 */
584 u64 tlb_rpn_RW; /* 0x518 */
585 u8 pad_0x520_0x540[0x20]; /* 0x520 */
586 u64 tlb_invalidate_entry_W; /* 0x540 */
587 u64 tlb_invalidate_all_W; /* 0x548 */
588 u8 pad_0x550_0x580[0x580 - 0x550]; /* 0x550 */
589
590 /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
591 u64 smm_hid; /* 0x580 */
592#define PAGE_SIZE_MASK 0xf000000000000000ull
593#define PAGE_SIZE_16MB_64KB 0x2000000000000000ull
594 u8 pad_0x588_0x600[0x600 - 0x588]; /* 0x588 */
595
596 /* MFC Status/Control Area */
597 u64 mfc_accr_RW; /* 0x600 */
598#define MFC_ACCR_EA_ACCESS_GET (1 << 0)
599#define MFC_ACCR_EA_ACCESS_PUT (1 << 1)
600#define MFC_ACCR_LS_ACCESS_GET (1 << 3)
601#define MFC_ACCR_LS_ACCESS_PUT (1 << 4)
602 u8 pad_0x608_0x610[0x8]; /* 0x608 */
603 u64 mfc_dsisr_RW; /* 0x610 */
604#define MFC_DSISR_PTE_NOT_FOUND (1 << 30)
605#define MFC_DSISR_ACCESS_DENIED (1 << 27)
606#define MFC_DSISR_ATOMIC (1 << 26)
607#define MFC_DSISR_ACCESS_PUT (1 << 25)
608#define MFC_DSISR_ADDR_MATCH (1 << 22)
609#define MFC_DSISR_LS (1 << 17)
610#define MFC_DSISR_L (1 << 16)
611#define MFC_DSISR_ADDRESS_OVERFLOW (1 << 0)
612 u8 pad_0x618_0x620[0x8]; /* 0x618 */
613 u64 mfc_dar_RW; /* 0x620 */
614 u8 pad_0x628_0x700[0x700 - 0x628]; /* 0x628 */
615
616 /* Replacement Management Table (RMT) Area */
617 u64 rmt_index_RW; /* 0x700 */
618 u8 pad_0x708_0x710[0x8]; /* 0x708 */
619 u64 rmt_data1_RW; /* 0x710 */
620 u8 pad_0x718_0x800[0x800 - 0x718]; /* 0x718 */
621
622 /* Control/Configuration Registers */
623 u64 mfc_dsir_R; /* 0x800 */
624#define MFC_DSIR_Q (1 << 31)
625#define MFC_DSIR_SPU_QUEUE MFC_DSIR_Q
626 u64 mfc_lsacr_RW; /* 0x808 */
627#define MFC_LSACR_COMPARE_MASK ((~0ull) << 32)
628#define MFC_LSACR_COMPARE_ADDR ((~0ull) >> 32)
629 u64 mfc_lscrr_R; /* 0x810 */
630#define MFC_LSCRR_Q (1 << 31)
631#define MFC_LSCRR_SPU_QUEUE MFC_LSCRR_Q
632#define MFC_LSCRR_QI_SHIFT 32
633#define MFC_LSCRR_QI_MASK ((~0ull) << MFC_LSCRR_QI_SHIFT)
634 u8 pad_0x818_0x820[0x8]; /* 0x818 */
635 u64 mfc_tclass_id_RW; /* 0x820 */
636#define MFC_TCLASS_ID_ENABLE (1L << 0L)
637#define MFC_TCLASS_SLOT2_ENABLE (1L << 5L)
638#define MFC_TCLASS_SLOT1_ENABLE (1L << 6L)
639#define MFC_TCLASS_SLOT0_ENABLE (1L << 7L)
640#define MFC_TCLASS_QUOTA_2_SHIFT 8L
641#define MFC_TCLASS_QUOTA_1_SHIFT 16L
642#define MFC_TCLASS_QUOTA_0_SHIFT 24L
643#define MFC_TCLASS_QUOTA_2_MASK (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
644#define MFC_TCLASS_QUOTA_1_MASK (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
645#define MFC_TCLASS_QUOTA_0_MASK (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
646 u8 pad_0x828_0x900[0x900 - 0x828]; /* 0x828 */
647
648 /* Real Mode Support Registers */
649 u64 mfc_rm_boundary; /* 0x900 */
650 u8 pad_0x908_0x938[0x30]; /* 0x908 */
651 u64 smf_dma_signal_sel; /* 0x938 */
652#define mfc_dma1_mask_lsb 41
653#define mfc_dma1_shift (63 - mfc_dma1_mask_lsb)
654#define mfc_dma1_mask (0x3LL << mfc_dma1_shift)
655#define mfc_dma1_bits (0x1LL << mfc_dma1_shift)
656#define mfc_dma2_mask_lsb 43
657#define mfc_dma2_shift (63 - mfc_dma2_mask_lsb)
658#define mfc_dma2_mask (0x3LL << mfc_dma2_shift)
659#define mfc_dma2_bits (0x1LL << mfc_dma2_shift)
660 u8 pad_0x940_0xa38[0xf8]; /* 0x940 */
661 u64 smm_signal_sel; /* 0xa38 */
662#define smm_sig_mask_lsb 12
663#define smm_sig_shift (63 - smm_sig_mask_lsb)
664#define smm_sig_mask (0x3LL << smm_sig_shift)
665#define smm_sig_bus0_bits (0x2LL << smm_sig_shift)
666#define smm_sig_bus2_bits (0x1LL << smm_sig_shift)
667 u8 pad_0xa40_0xc00[0xc00 - 0xa40]; /* 0xa40 */
668
669 /* DMA Command Error Area */
670 u64 mfc_cer_R; /* 0xc00 */
671#define MFC_CER_Q (1 << 31)
672#define MFC_CER_SPU_QUEUE MFC_CER_Q
673 u8 pad_0xc08_0x1000[0x1000 - 0xc08]; /* 0xc08 */
674
675 /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
676 /* DMA Command Error Area */
677 u64 spu_ecc_cntl_RW; /* 0x1000 */
678#define SPU_ECC_CNTL_E (1ull << 0ull)
679#define SPU_ECC_CNTL_ENABLE SPU_ECC_CNTL_E
680#define SPU_ECC_CNTL_DISABLE (~SPU_ECC_CNTL_E & 1L)
681#define SPU_ECC_CNTL_S (1ull << 1ull)
682#define SPU_ECC_STOP_AFTER_ERROR SPU_ECC_CNTL_S
683#define SPU_ECC_CONTINUE_AFTER_ERROR (~SPU_ECC_CNTL_S & 2L)
684#define SPU_ECC_CNTL_B (1ull << 2ull)
685#define SPU_ECC_BACKGROUND_ENABLE SPU_ECC_CNTL_B
686#define SPU_ECC_BACKGROUND_DISABLE (~SPU_ECC_CNTL_B & 4L)
687#define SPU_ECC_CNTL_I_SHIFT 3ull
688#define SPU_ECC_CNTL_I_MASK (3ull << SPU_ECC_CNTL_I_SHIFT)
689#define SPU_ECC_WRITE_ALWAYS (~SPU_ECC_CNTL_I & 12L)
690#define SPU_ECC_WRITE_CORRECTABLE (1ull << SPU_ECC_CNTL_I_SHIFT)
691#define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
692#define SPU_ECC_CNTL_D (1ull << 5ull)
693#define SPU_ECC_DETECTION_ENABLE SPU_ECC_CNTL_D
694#define SPU_ECC_DETECTION_DISABLE (~SPU_ECC_CNTL_D & 32L)
695 u64 spu_ecc_stat_RW; /* 0x1008 */
696#define SPU_ECC_CORRECTED_ERROR (1ull << 0ul)
697#define SPU_ECC_UNCORRECTED_ERROR (1ull << 1ul)
698#define SPU_ECC_SCRUB_COMPLETE (1ull << 2ul)
699#define SPU_ECC_SCRUB_IN_PROGRESS (1ull << 3ul)
700#define SPU_ECC_INSTRUCTION_ERROR (1ull << 4ul)
701#define SPU_ECC_DATA_ERROR (1ull << 5ul)
702#define SPU_ECC_DMA_ERROR (1ull << 6ul)
703#define SPU_ECC_STATUS_CNT_MASK (256ull << 8)
704 u64 spu_ecc_addr_RW; /* 0x1010 */
705 u64 spu_err_mask_RW; /* 0x1018 */
706#define SPU_ERR_ILLEGAL_INSTR (1ull << 0ul)
707#define SPU_ERR_ILLEGAL_CHANNEL (1ull << 1ul)
708 u8 pad_0x1020_0x1028[0x1028 - 0x1020]; /* 0x1020 */
709
710 /* SPU Debug-Trace Bus (DTB) Selection Registers */
711 u64 spu_trig0_sel; /* 0x1028 */
712 u64 spu_trig1_sel; /* 0x1030 */
713 u64 spu_trig2_sel; /* 0x1038 */
714 u64 spu_trig3_sel; /* 0x1040 */
715 u64 spu_trace_sel; /* 0x1048 */
716#define spu_trace_sel_mask 0x1f1fLL
717#define spu_trace_sel_bus0_bits 0x1000LL
718#define spu_trace_sel_bus2_bits 0x0010LL
719 u64 spu_event0_sel; /* 0x1050 */
720 u64 spu_event1_sel; /* 0x1058 */
721 u64 spu_event2_sel; /* 0x1060 */
722 u64 spu_event3_sel; /* 0x1068 */
723 u64 spu_trace_cntl; /* 0x1070 */
724} __attribute__ ((aligned(0x2000)));
725
88ced031 726#endif /* __KERNEL__ */
67207b96 727#endif
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