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9f04b9e3 PM |
1 | #ifndef _ASM_POWERPC_PROCESSOR_H |
2 | #define _ASM_POWERPC_PROCESSOR_H | |
1da177e4 LT |
3 | |
4 | /* | |
9f04b9e3 PM |
5 | * Copyright (C) 2001 PPC 64 Team, IBM Corp |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
1da177e4 | 11 | */ |
1da177e4 LT |
12 | |
13 | #include <linux/config.h> | |
9f04b9e3 | 14 | #include <asm/reg.h> |
1da177e4 | 15 | |
9f04b9e3 PM |
16 | #ifndef __ASSEMBLY__ |
17 | #include <linux/compiler.h> | |
1da177e4 LT |
18 | #include <asm/ptrace.h> |
19 | #include <asm/types.h> | |
1da177e4 | 20 | |
799d6046 PM |
21 | /* We do _not_ want to define new machine types at all, those must die |
22 | * in favor of using the device-tree | |
23 | * -- BenH. | |
1da177e4 | 24 | */ |
1da177e4 | 25 | |
799d6046 PM |
26 | /* Platforms codes (to be obsoleted) */ |
27 | #define PLATFORM_PSERIES 0x0100 | |
28 | #define PLATFORM_PSERIES_LPAR 0x0101 | |
29 | #define PLATFORM_ISERIES_LPAR 0x0201 | |
30 | #define PLATFORM_LPAR 0x0001 | |
31 | #define PLATFORM_POWERMAC 0x0400 | |
32 | #define PLATFORM_MAPLE 0x0500 | |
33 | #define PLATFORM_PREP 0x0600 | |
34 | #define PLATFORM_CHRP 0x0700 | |
35 | #define PLATFORM_CELL 0x1000 | |
36 | ||
37 | /* Compat platform codes for 32 bits */ | |
38 | #define _MACH_prep PLATFORM_PREP | |
39 | #define _MACH_Pmac PLATFORM_POWERMAC | |
40 | #define _MACH_chrp PLATFORM_CHRP | |
41 | ||
42 | /* PREP sub-platform types see residual.h for these */ | |
1da177e4 LT |
43 | #define _PREP_Motorola 0x01 /* motorola prep */ |
44 | #define _PREP_Firm 0x02 /* firmworks prep */ | |
45 | #define _PREP_IBM 0x00 /* ibm prep */ | |
46 | #define _PREP_Bull 0x03 /* bull prep */ | |
47 | ||
799d6046 | 48 | /* CHRP sub-platform types. These are arbitrary */ |
1da177e4 LT |
49 | #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ |
50 | #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ | |
51 | #define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */ | |
52 | ||
799d6046 PM |
53 | #define platform_is_pseries() (_machine == PLATFORM_PSERIES || \ |
54 | _machine == PLATFORM_PSERIES_LPAR) | |
55 | #define platform_is_lpar() (!!(_machine & PLATFORM_LPAR)) | |
56 | ||
57 | #if defined(CONFIG_PPC_MULTIPLATFORM) | |
1da177e4 LT |
58 | extern int _machine; |
59 | ||
799d6046 PM |
60 | #ifdef CONFIG_PPC32 |
61 | ||
1da177e4 LT |
62 | /* what kind of prep workstation we are */ |
63 | extern int _prep_type; | |
64 | extern int _chrp_type; | |
65 | ||
66 | /* | |
67 | * This is used to identify the board type from a given PReP board | |
799d6046 PM |
68 | * vendor. Board revision is also made available. This will be moved |
69 | * elsewhere soon | |
1da177e4 LT |
70 | */ |
71 | extern unsigned char ucSystemType; | |
72 | extern unsigned char ucBoardRev; | |
73 | extern unsigned char ucBoardRevMaj, ucBoardRevMin; | |
799d6046 PM |
74 | |
75 | #endif /* CONFIG_PPC32 */ | |
76 | ||
77 | #elif defined(CONFIG_PPC_ISERIES) | |
78 | /* | |
79 | * iSeries is soon to become MULTIPLATFORM hopefully ... | |
80 | */ | |
3db9aaaf | 81 | #define _machine PLATFORM_ISERIES_LPAR |
1da177e4 LT |
82 | #else |
83 | #define _machine 0 | |
84 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | |
9f04b9e3 | 85 | |
9f04b9e3 PM |
86 | /* |
87 | * Default implementation of macro that returns current | |
88 | * instruction pointer ("program counter"). | |
89 | */ | |
90 | #define current_text_addr() ({ __label__ _l; _l: &&_l;}) | |
91 | ||
92 | /* Macros for adjusting thread priority (hardware multi-threading) */ | |
93 | #define HMT_very_low() asm volatile("or 31,31,31 # very low priority") | |
94 | #define HMT_low() asm volatile("or 1,1,1 # low priority") | |
95 | #define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority") | |
96 | #define HMT_medium() asm volatile("or 2,2,2 # medium priority") | |
97 | #define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority") | |
98 | #define HMT_high() asm volatile("or 3,3,3 # high priority") | |
99 | ||
100 | #ifdef __KERNEL__ | |
101 | ||
102 | extern int have_of; | |
1da177e4 LT |
103 | |
104 | struct task_struct; | |
9f04b9e3 | 105 | void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp); |
1da177e4 LT |
106 | void release_thread(struct task_struct *); |
107 | ||
108 | /* Prepare to copy thread state - unlazy all lazy status */ | |
109 | extern void prepare_to_copy(struct task_struct *tsk); | |
110 | ||
9f04b9e3 | 111 | /* Create a new kernel thread. */ |
1da177e4 LT |
112 | extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags); |
113 | ||
114 | /* Lazy FPU handling on uni-processor */ | |
115 | extern struct task_struct *last_task_used_math; | |
116 | extern struct task_struct *last_task_used_altivec; | |
117 | extern struct task_struct *last_task_used_spe; | |
118 | ||
9f04b9e3 PM |
119 | #ifdef CONFIG_PPC32 |
120 | #define TASK_SIZE (CONFIG_TASK_SIZE) | |
121 | ||
1da177e4 LT |
122 | /* This decides where the kernel will search for a free chunk of vm |
123 | * space during mmap's. | |
124 | */ | |
125 | #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) | |
9f04b9e3 PM |
126 | #endif |
127 | ||
128 | #ifdef CONFIG_PPC64 | |
129 | /* 64-bit user address space is 44-bits (16TB user VM) */ | |
130 | #define TASK_SIZE_USER64 (0x0000100000000000UL) | |
131 | ||
132 | /* | |
133 | * 32-bit user address space is 4GB - 1 page | |
134 | * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT | |
135 | */ | |
136 | #define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE)) | |
137 | ||
138 | #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \ | |
139 | TASK_SIZE_USER32 : TASK_SIZE_USER64) | |
140 | ||
141 | /* This decides where the kernel will search for a free chunk of vm | |
142 | * space during mmap's. | |
143 | */ | |
144 | #define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4)) | |
145 | #define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4)) | |
146 | ||
147 | #define TASK_UNMAPPED_BASE ((test_thread_flag(TIF_32BIT)) ? \ | |
148 | TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 ) | |
149 | #endif | |
1da177e4 LT |
150 | |
151 | typedef struct { | |
152 | unsigned long seg; | |
153 | } mm_segment_t; | |
154 | ||
155 | struct thread_struct { | |
156 | unsigned long ksp; /* Kernel stack pointer */ | |
9f04b9e3 PM |
157 | #ifdef CONFIG_PPC64 |
158 | unsigned long ksp_vsid; | |
159 | #endif | |
1da177e4 LT |
160 | struct pt_regs *regs; /* Pointer to saved register state */ |
161 | mm_segment_t fs; /* for get_fs() validation */ | |
9f04b9e3 | 162 | #ifdef CONFIG_PPC32 |
1da177e4 | 163 | void *pgdir; /* root of page-table tree */ |
1da177e4 | 164 | signed long last_syscall; |
9f04b9e3 | 165 | #endif |
1da177e4 LT |
166 | #if defined(CONFIG_4xx) || defined (CONFIG_BOOKE) |
167 | unsigned long dbcr0; /* debug control register values */ | |
168 | unsigned long dbcr1; | |
169 | #endif | |
170 | double fpr[32]; /* Complete floating point set */ | |
25c8a78b DG |
171 | struct { /* fpr ... fpscr must be contiguous */ |
172 | ||
173 | unsigned int pad; | |
174 | unsigned int val; /* Floating point status */ | |
175 | } fpscr; | |
9f04b9e3 PM |
176 | int fpexc_mode; /* floating-point exception mode */ |
177 | #ifdef CONFIG_PPC64 | |
178 | unsigned long start_tb; /* Start purr when proc switched in */ | |
179 | unsigned long accum_tb; /* Total accumilated purr for process */ | |
9f04b9e3 | 180 | #endif |
a7f290da | 181 | unsigned long vdso_base; /* base of the vDSO library */ |
9f04b9e3 | 182 | unsigned long dabr; /* Data address breakpoint register */ |
1da177e4 LT |
183 | #ifdef CONFIG_ALTIVEC |
184 | /* Complete AltiVec register set */ | |
185 | vector128 vr[32] __attribute((aligned(16))); | |
186 | /* AltiVec status */ | |
187 | vector128 vscr __attribute((aligned(16))); | |
188 | unsigned long vrsave; | |
189 | int used_vr; /* set if process has used altivec */ | |
190 | #endif /* CONFIG_ALTIVEC */ | |
191 | #ifdef CONFIG_SPE | |
192 | unsigned long evr[32]; /* upper 32-bits of SPE regs */ | |
193 | u64 acc; /* Accumulator */ | |
194 | unsigned long spefscr; /* SPE & eFP status */ | |
195 | int used_spe; /* set if process has used spe */ | |
196 | #endif /* CONFIG_SPE */ | |
197 | }; | |
198 | ||
199 | #define ARCH_MIN_TASKALIGN 16 | |
200 | ||
201 | #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) | |
202 | ||
9f04b9e3 PM |
203 | |
204 | #ifdef CONFIG_PPC32 | |
1da177e4 LT |
205 | #define INIT_THREAD { \ |
206 | .ksp = INIT_SP, \ | |
207 | .fs = KERNEL_DS, \ | |
208 | .pgdir = swapper_pg_dir, \ | |
209 | .fpexc_mode = MSR_FE0 | MSR_FE1, \ | |
210 | } | |
9f04b9e3 PM |
211 | #else |
212 | #define INIT_THREAD { \ | |
213 | .ksp = INIT_SP, \ | |
214 | .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \ | |
215 | .fs = KERNEL_DS, \ | |
216 | .fpr = {0}, \ | |
25c8a78b | 217 | .fpscr = { .val = 0, }, \ |
9f04b9e3 PM |
218 | .fpexc_mode = MSR_FE0|MSR_FE1, \ |
219 | } | |
220 | #endif | |
1da177e4 LT |
221 | |
222 | /* | |
223 | * Return saved PC of a blocked thread. For now, this is the "user" PC | |
224 | */ | |
9f04b9e3 PM |
225 | #define thread_saved_pc(tsk) \ |
226 | ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) | |
1da177e4 LT |
227 | |
228 | unsigned long get_wchan(struct task_struct *p); | |
229 | ||
9f04b9e3 PM |
230 | #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) |
231 | #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0) | |
1da177e4 LT |
232 | |
233 | /* Get/set floating-point exception mode */ | |
9f04b9e3 PM |
234 | #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr)) |
235 | #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val)) | |
1da177e4 LT |
236 | |
237 | extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr); | |
238 | extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val); | |
239 | ||
9f04b9e3 | 240 | static inline unsigned int __unpack_fe01(unsigned long msr_bits) |
1da177e4 LT |
241 | { |
242 | return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8); | |
243 | } | |
244 | ||
9f04b9e3 | 245 | static inline unsigned long __pack_fe01(unsigned int fpmode) |
1da177e4 LT |
246 | { |
247 | return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1); | |
248 | } | |
249 | ||
9f04b9e3 PM |
250 | #ifdef CONFIG_PPC64 |
251 | #define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0) | |
252 | #else | |
1da177e4 | 253 | #define cpu_relax() barrier() |
9f04b9e3 | 254 | #endif |
1da177e4 LT |
255 | |
256 | /* | |
257 | * Prefetch macros. | |
258 | */ | |
259 | #define ARCH_HAS_PREFETCH | |
260 | #define ARCH_HAS_PREFETCHW | |
261 | #define ARCH_HAS_SPINLOCK_PREFETCH | |
262 | ||
9f04b9e3 | 263 | static inline void prefetch(const void *x) |
1da177e4 | 264 | { |
9f04b9e3 PM |
265 | if (unlikely(!x)) |
266 | return; | |
267 | ||
268 | __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x)); | |
1da177e4 LT |
269 | } |
270 | ||
9f04b9e3 | 271 | static inline void prefetchw(const void *x) |
1da177e4 | 272 | { |
9f04b9e3 PM |
273 | if (unlikely(!x)) |
274 | return; | |
275 | ||
276 | __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x)); | |
1da177e4 LT |
277 | } |
278 | ||
279 | #define spin_lock_prefetch(x) prefetchw(x) | |
280 | ||
9f04b9e3 PM |
281 | #ifdef CONFIG_PPC64 |
282 | #define HAVE_ARCH_PICK_MMAP_LAYOUT | |
283 | #endif | |
1da177e4 | 284 | |
1da177e4 | 285 | #endif /* __KERNEL__ */ |
9f04b9e3 PM |
286 | #endif /* __ASSEMBLY__ */ |
287 | #endif /* _ASM_POWERPC_PROCESSOR_H */ |