Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. |
1da177e4 | 3 | */ |
5f7c6907 KG |
4 | #ifndef _ASM_POWERPC_PPC_ASM_H |
5 | #define _ASM_POWERPC_PPC_ASM_H | |
6 | ||
40ef8cbc PM |
7 | #include <linux/stringify.h> |
8 | #include <linux/config.h> | |
9 | ||
5f7c6907 | 10 | #ifdef __ASSEMBLY__ |
1da177e4 LT |
11 | |
12 | /* | |
13 | * Macros for storing registers into and loading registers from | |
14 | * exception frames. | |
15 | */ | |
5f7c6907 KG |
16 | #ifdef __powerpc64__ |
17 | #define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) | |
18 | #define REST_GPR(n, base) ld n,GPR0+8*(n)(base) | |
19 | #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) | |
20 | #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) | |
21 | #else | |
1da177e4 | 22 | #define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) |
5f7c6907 KG |
23 | #define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) |
24 | #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ | |
25 | SAVE_10GPRS(22, base) | |
26 | #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ | |
27 | REST_10GPRS(22, base) | |
28 | #endif | |
29 | ||
30 | ||
1da177e4 LT |
31 | #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) |
32 | #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) | |
33 | #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) | |
34 | #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) | |
1da177e4 LT |
35 | #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) |
36 | #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) | |
37 | #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) | |
38 | #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) | |
39 | ||
1da177e4 LT |
40 | #define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base) |
41 | #define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) | |
42 | #define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) | |
43 | #define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) | |
44 | #define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) | |
45 | #define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) | |
46 | #define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base) | |
47 | #define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) | |
48 | #define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) | |
49 | #define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) | |
50 | #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) | |
51 | #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) | |
52 | ||
53 | #define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base | |
5f7c6907 KG |
54 | #define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) |
55 | #define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) | |
56 | #define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) | |
57 | #define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) | |
58 | #define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) | |
1da177e4 | 59 | #define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base |
5f7c6907 KG |
60 | #define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) |
61 | #define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) | |
62 | #define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) | |
63 | #define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) | |
64 | #define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) | |
1da177e4 LT |
65 | |
66 | #define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base) | |
5f7c6907 KG |
67 | #define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base) |
68 | #define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base) | |
69 | #define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base) | |
70 | #define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base) | |
71 | #define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base) | |
1da177e4 | 72 | #define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n |
5f7c6907 KG |
73 | #define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base) |
74 | #define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base) | |
75 | #define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base) | |
76 | #define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base) | |
77 | #define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base) | |
78 | ||
8c71632f ME |
79 | /* Macros to adjust thread priority for hardware multithreading */ |
80 | #define HMT_VERY_LOW or 31,31,31 # very low priority | |
81 | #define HMT_LOW or 1,1,1 | |
82 | #define HMT_MEDIUM_LOW or 6,6,6 # medium low priority | |
83 | #define HMT_MEDIUM or 2,2,2 | |
84 | #define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority | |
85 | #define HMT_HIGH or 3,3,3 | |
5f7c6907 KG |
86 | |
87 | /* handle instructions that older assemblers may not know */ | |
88 | #define RFCI .long 0x4c000066 /* rfci instruction */ | |
89 | #define RFDI .long 0x4c00004e /* rfdi instruction */ | |
90 | #define RFMCI .long 0x4c00004c /* rfmci instruction */ | |
91 | ||
40ef8cbc PM |
92 | #ifdef CONFIG_PPC64 |
93 | ||
94 | #define XGLUE(a,b) a##b | |
95 | #define GLUE(a,b) XGLUE(a,b) | |
96 | ||
97 | #define _GLOBAL(name) \ | |
98 | .section ".text"; \ | |
99 | .align 2 ; \ | |
100 | .globl name; \ | |
101 | .globl GLUE(.,name); \ | |
102 | .section ".opd","aw"; \ | |
103 | name: \ | |
104 | .quad GLUE(.,name); \ | |
105 | .quad .TOC.@tocbase; \ | |
106 | .quad 0; \ | |
107 | .previous; \ | |
108 | .type GLUE(.,name),@function; \ | |
109 | GLUE(.,name): | |
110 | ||
111 | #define _KPROBE(name) \ | |
112 | .section ".kprobes.text","a"; \ | |
113 | .align 2 ; \ | |
114 | .globl name; \ | |
115 | .globl GLUE(.,name); \ | |
116 | .section ".opd","aw"; \ | |
117 | name: \ | |
118 | .quad GLUE(.,name); \ | |
119 | .quad .TOC.@tocbase; \ | |
120 | .quad 0; \ | |
121 | .previous; \ | |
122 | .type GLUE(.,name),@function; \ | |
123 | GLUE(.,name): | |
124 | ||
125 | #define _STATIC(name) \ | |
126 | .section ".text"; \ | |
127 | .align 2 ; \ | |
128 | .section ".opd","aw"; \ | |
129 | name: \ | |
130 | .quad GLUE(.,name); \ | |
131 | .quad .TOC.@tocbase; \ | |
132 | .quad 0; \ | |
133 | .previous; \ | |
134 | .type GLUE(.,name),@function; \ | |
135 | GLUE(.,name): | |
136 | ||
137 | #else /* 32-bit */ | |
138 | ||
139 | #define _GLOBAL(n) \ | |
140 | .text; \ | |
141 | .stabs __stringify(n:F-1),N_FUN,0,0,n;\ | |
142 | .globl n; \ | |
143 | n: | |
144 | ||
145 | #define _KPROBE(n) \ | |
146 | .section ".kprobes.text","a"; \ | |
147 | .globl n; \ | |
148 | n: | |
149 | ||
150 | #endif | |
151 | ||
5f7c6907 KG |
152 | /* |
153 | * LOADADDR( rn, name ) | |
154 | * loads the address of 'name' into 'rn' | |
155 | * | |
156 | * LOADBASE( rn, name ) | |
6316222e | 157 | * loads the address (possibly without the low 16 bits) of 'name' into 'rn' |
5f7c6907 KG |
158 | * suitable for base+disp addressing |
159 | */ | |
160 | #ifdef __powerpc64__ | |
161 | #define LOADADDR(rn,name) \ | |
162 | lis rn,name##@highest; \ | |
163 | ori rn,rn,name##@higher; \ | |
164 | rldicr rn,rn,32,31; \ | |
165 | oris rn,rn,name##@h; \ | |
166 | ori rn,rn,name##@l | |
167 | ||
b85a046a | 168 | #define LOADBASE(rn,name) \ |
6316222e | 169 | ld rn,name@got(r2) |
5f7c6907 | 170 | |
b85a046a | 171 | #define OFF(name) 0 |
5f7c6907 KG |
172 | |
173 | #define SET_REG_TO_CONST(reg, value) \ | |
174 | lis reg,(((value)>>48)&0xFFFF); \ | |
175 | ori reg,reg,(((value)>>32)&0xFFFF); \ | |
176 | rldicr reg,reg,32,31; \ | |
177 | oris reg,reg,(((value)>>16)&0xFFFF); \ | |
178 | ori reg,reg,((value)&0xFFFF); | |
179 | ||
180 | #define SET_REG_TO_LABEL(reg, label) \ | |
181 | lis reg,(label)@highest; \ | |
182 | ori reg,reg,(label)@higher; \ | |
183 | rldicr reg,reg,32,31; \ | |
184 | oris reg,reg,(label)@h; \ | |
185 | ori reg,reg,(label)@l; | |
b85a046a PM |
186 | |
187 | /* operations for longs and pointers */ | |
188 | #define LDL ld | |
189 | #define STL std | |
190 | #define CMPI cmpdi | |
f78541dc PM |
191 | #define SZL 8 |
192 | ||
193 | /* offsets for stack frame layout */ | |
194 | #define LRSAVE 16 | |
b85a046a PM |
195 | |
196 | #else /* 32-bit */ | |
70620186 | 197 | #define LOADADDR(rn,name) \ |
cf764855 | 198 | lis rn,name@ha; \ |
70620186 SR |
199 | addi rn,rn,name@l |
200 | ||
b85a046a PM |
201 | #define LOADBASE(rn,name) \ |
202 | lis rn,name@ha | |
203 | ||
204 | #define OFF(name) name@l | |
205 | ||
206 | /* operations for longs and pointers */ | |
207 | #define LDL lwz | |
208 | #define STL stw | |
209 | #define CMPI cmpwi | |
f78541dc PM |
210 | #define SZL 4 |
211 | ||
212 | /* offsets for stack frame layout */ | |
213 | #define LRSAVE 4 | |
b85a046a | 214 | |
5f7c6907 | 215 | #endif |
1da177e4 | 216 | |
5f7c6907 | 217 | /* various errata or part fixups */ |
1da177e4 LT |
218 | #ifdef CONFIG_PPC601_SYNC_FIX |
219 | #define SYNC \ | |
220 | BEGIN_FTR_SECTION \ | |
221 | sync; \ | |
222 | isync; \ | |
223 | END_FTR_SECTION_IFSET(CPU_FTR_601) | |
224 | #define SYNC_601 \ | |
225 | BEGIN_FTR_SECTION \ | |
226 | sync; \ | |
227 | END_FTR_SECTION_IFSET(CPU_FTR_601) | |
228 | #define ISYNC_601 \ | |
229 | BEGIN_FTR_SECTION \ | |
230 | isync; \ | |
231 | END_FTR_SECTION_IFSET(CPU_FTR_601) | |
232 | #else | |
233 | #define SYNC | |
234 | #define SYNC_601 | |
235 | #define ISYNC_601 | |
236 | #endif | |
237 | ||
5f7c6907 | 238 | |
1da177e4 LT |
239 | #ifndef CONFIG_SMP |
240 | #define TLBSYNC | |
241 | #else /* CONFIG_SMP */ | |
242 | /* tlbsync is not implemented on 601 */ | |
243 | #define TLBSYNC \ | |
244 | BEGIN_FTR_SECTION \ | |
245 | tlbsync; \ | |
246 | sync; \ | |
247 | END_FTR_SECTION_IFCLR(CPU_FTR_601) | |
248 | #endif | |
249 | ||
5f7c6907 | 250 | |
1da177e4 LT |
251 | /* |
252 | * This instruction is not implemented on the PPC 603 or 601; however, on | |
253 | * the 403GCX and 405GP tlbia IS defined and tlbie is not. | |
254 | * All of these instructions exist in the 8xx, they have magical powers, | |
255 | * and they must be used. | |
256 | */ | |
257 | ||
258 | #if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) | |
259 | #define tlbia \ | |
260 | li r4,1024; \ | |
261 | mtctr r4; \ | |
262 | lis r4,KERNELBASE@h; \ | |
263 | 0: tlbie r4; \ | |
264 | addi r4,r4,0x1000; \ | |
265 | bdnz 0b | |
266 | #endif | |
267 | ||
5f7c6907 KG |
268 | |
269 | #ifdef CONFIG_IBM405_ERR77 | |
270 | #define PPC405_ERR77(ra,rb) dcbt ra, rb; | |
271 | #define PPC405_ERR77_SYNC sync; | |
272 | #else | |
273 | #define PPC405_ERR77(ra,rb) | |
274 | #define PPC405_ERR77_SYNC | |
275 | #endif | |
276 | ||
277 | ||
278 | #ifdef CONFIG_IBM440EP_ERR42 | |
279 | #define PPC440EP_ERR42 isync | |
280 | #else | |
281 | #define PPC440EP_ERR42 | |
282 | #endif | |
283 | ||
284 | ||
285 | #if defined(CONFIG_BOOKE) | |
6316222e PM |
286 | #define toreal(rd) |
287 | #define fromreal(rd) | |
288 | ||
1da177e4 LT |
289 | #define tophys(rd,rs) \ |
290 | addis rd,rs,0 | |
291 | ||
292 | #define tovirt(rd,rs) \ | |
293 | addis rd,rs,0 | |
294 | ||
5f7c6907 | 295 | #elif defined(CONFIG_PPC64) |
6316222e PM |
296 | #define toreal(rd) /* we can access c000... in real mode */ |
297 | #define fromreal(rd) | |
298 | ||
5f7c6907 | 299 | #define tophys(rd,rs) \ |
6316222e | 300 | clrldi rd,rs,2 |
5f7c6907 KG |
301 | |
302 | #define tovirt(rd,rs) \ | |
6316222e PM |
303 | rotldi rd,rs,16; \ |
304 | ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ | |
305 | rotldi rd,rd,48 | |
5f7c6907 | 306 | #else |
1da177e4 LT |
307 | /* |
308 | * On APUS (Amiga PowerPC cpu upgrade board), we don't know the | |
309 | * physical base address of RAM at compile time. | |
310 | */ | |
6316222e PM |
311 | #define toreal(rd) tophys(rd,rd) |
312 | #define fromreal(rd) tovirt(rd,rd) | |
313 | ||
1da177e4 LT |
314 | #define tophys(rd,rs) \ |
315 | 0: addis rd,rs,-KERNELBASE@h; \ | |
316 | .section ".vtop_fixup","aw"; \ | |
317 | .align 1; \ | |
318 | .long 0b; \ | |
319 | .previous | |
320 | ||
321 | #define tovirt(rd,rs) \ | |
322 | 0: addis rd,rs,KERNELBASE@h; \ | |
323 | .section ".ptov_fixup","aw"; \ | |
324 | .align 1; \ | |
325 | .long 0b; \ | |
326 | .previous | |
5f7c6907 | 327 | #endif |
1da177e4 | 328 | |
40ef8cbc PM |
329 | #ifdef CONFIG_PPC64 |
330 | #define RFI rfid | |
331 | #define MTMSRD(r) mtmsrd r | |
1da177e4 LT |
332 | |
333 | #else | |
334 | #define FIX_SRR1(ra, rb) | |
335 | #ifndef CONFIG_40x | |
336 | #define RFI rfi | |
337 | #else | |
338 | #define RFI rfi; b . /* Prevent prefetch past rfi */ | |
339 | #endif | |
340 | #define MTMSRD(r) mtmsr r | |
341 | #define CLR_TOP32(r) | |
c9cf73ae MP |
342 | #endif |
343 | ||
1da177e4 LT |
344 | /* The boring bits... */ |
345 | ||
346 | /* Condition Register Bit Fields */ | |
347 | ||
348 | #define cr0 0 | |
349 | #define cr1 1 | |
350 | #define cr2 2 | |
351 | #define cr3 3 | |
352 | #define cr4 4 | |
353 | #define cr5 5 | |
354 | #define cr6 6 | |
355 | #define cr7 7 | |
356 | ||
357 | ||
358 | /* General Purpose Registers (GPRs) */ | |
359 | ||
360 | #define r0 0 | |
361 | #define r1 1 | |
362 | #define r2 2 | |
363 | #define r3 3 | |
364 | #define r4 4 | |
365 | #define r5 5 | |
366 | #define r6 6 | |
367 | #define r7 7 | |
368 | #define r8 8 | |
369 | #define r9 9 | |
370 | #define r10 10 | |
371 | #define r11 11 | |
372 | #define r12 12 | |
373 | #define r13 13 | |
374 | #define r14 14 | |
375 | #define r15 15 | |
376 | #define r16 16 | |
377 | #define r17 17 | |
378 | #define r18 18 | |
379 | #define r19 19 | |
380 | #define r20 20 | |
381 | #define r21 21 | |
382 | #define r22 22 | |
383 | #define r23 23 | |
384 | #define r24 24 | |
385 | #define r25 25 | |
386 | #define r26 26 | |
387 | #define r27 27 | |
388 | #define r28 28 | |
389 | #define r29 29 | |
390 | #define r30 30 | |
391 | #define r31 31 | |
392 | ||
393 | ||
394 | /* Floating Point Registers (FPRs) */ | |
395 | ||
396 | #define fr0 0 | |
397 | #define fr1 1 | |
398 | #define fr2 2 | |
399 | #define fr3 3 | |
400 | #define fr4 4 | |
401 | #define fr5 5 | |
402 | #define fr6 6 | |
403 | #define fr7 7 | |
404 | #define fr8 8 | |
405 | #define fr9 9 | |
406 | #define fr10 10 | |
407 | #define fr11 11 | |
408 | #define fr12 12 | |
409 | #define fr13 13 | |
410 | #define fr14 14 | |
411 | #define fr15 15 | |
412 | #define fr16 16 | |
413 | #define fr17 17 | |
414 | #define fr18 18 | |
415 | #define fr19 19 | |
416 | #define fr20 20 | |
417 | #define fr21 21 | |
418 | #define fr22 22 | |
419 | #define fr23 23 | |
420 | #define fr24 24 | |
421 | #define fr25 25 | |
422 | #define fr26 26 | |
423 | #define fr27 27 | |
424 | #define fr28 28 | |
425 | #define fr29 29 | |
426 | #define fr30 30 | |
427 | #define fr31 31 | |
428 | ||
5f7c6907 KG |
429 | /* AltiVec Registers (VPRs) */ |
430 | ||
1da177e4 LT |
431 | #define vr0 0 |
432 | #define vr1 1 | |
433 | #define vr2 2 | |
434 | #define vr3 3 | |
435 | #define vr4 4 | |
436 | #define vr5 5 | |
437 | #define vr6 6 | |
438 | #define vr7 7 | |
439 | #define vr8 8 | |
440 | #define vr9 9 | |
441 | #define vr10 10 | |
442 | #define vr11 11 | |
443 | #define vr12 12 | |
444 | #define vr13 13 | |
445 | #define vr14 14 | |
446 | #define vr15 15 | |
447 | #define vr16 16 | |
448 | #define vr17 17 | |
449 | #define vr18 18 | |
450 | #define vr19 19 | |
451 | #define vr20 20 | |
452 | #define vr21 21 | |
453 | #define vr22 22 | |
454 | #define vr23 23 | |
455 | #define vr24 24 | |
456 | #define vr25 25 | |
457 | #define vr26 26 | |
458 | #define vr27 27 | |
459 | #define vr28 28 | |
460 | #define vr29 29 | |
461 | #define vr30 30 | |
462 | #define vr31 31 | |
463 | ||
5f7c6907 KG |
464 | /* SPE Registers (EVPRs) */ |
465 | ||
1da177e4 LT |
466 | #define evr0 0 |
467 | #define evr1 1 | |
468 | #define evr2 2 | |
469 | #define evr3 3 | |
470 | #define evr4 4 | |
471 | #define evr5 5 | |
472 | #define evr6 6 | |
473 | #define evr7 7 | |
474 | #define evr8 8 | |
475 | #define evr9 9 | |
476 | #define evr10 10 | |
477 | #define evr11 11 | |
478 | #define evr12 12 | |
479 | #define evr13 13 | |
480 | #define evr14 14 | |
481 | #define evr15 15 | |
482 | #define evr16 16 | |
483 | #define evr17 17 | |
484 | #define evr18 18 | |
485 | #define evr19 19 | |
486 | #define evr20 20 | |
487 | #define evr21 21 | |
488 | #define evr22 22 | |
489 | #define evr23 23 | |
490 | #define evr24 24 | |
491 | #define evr25 25 | |
492 | #define evr26 26 | |
493 | #define evr27 27 | |
494 | #define evr28 28 | |
495 | #define evr29 29 | |
496 | #define evr30 30 | |
497 | #define evr31 31 | |
498 | ||
499 | /* some stab codes */ | |
500 | #define N_FUN 36 | |
501 | #define N_RSYM 64 | |
502 | #define N_SLINE 68 | |
503 | #define N_SO 100 | |
5f7c6907 KG |
504 | |
505 | #define ASM_CONST(x) x | |
506 | #else | |
507 | #define __ASM_CONST(x) x##UL | |
508 | #define ASM_CONST(x) __ASM_CONST(x) | |
2ff2ae7a DG |
509 | |
510 | #ifdef CONFIG_PPC64 | |
511 | #define DATAL ".llong" | |
512 | #else | |
513 | #define DATAL ".long" | |
514 | #endif | |
515 | ||
5f7c6907 KG |
516 | #endif /* __ASSEMBLY__ */ |
517 | ||
518 | #endif /* _ASM_POWERPC_PPC_ASM_H */ |