[linux-block.git] / include / asm-powerpc / ppc_asm.h

/*
 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
 */

#ifndef _ASM_POWERPC_PPC_ASM_H
#define _ASM_POWERPC_PPC_ASM_H

#ifdef __ASSEMBLY__

/*
 * Macros for storing registers into and loading registers from
 * exception frames.
 */
#ifdef __powerpc64__
#define SAVE_GPR(n, base)	std	n,GPR0+8*(n)(base)
#define REST_GPR(n, base)	ld	n,GPR0+8*(n)(base)
#define SAVE_NVGPRS(base)	SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
#define REST_NVGPRS(base)	REST_8GPRS(14, base); REST_10GPRS(22, base)
#else
#define SAVE_GPR(n, base)	stw	n,GPR0+4*(n)(base)
#define REST_GPR(n, base)	lwz	n,GPR0+4*(n)(base)
#define SAVE_NVGPRS(base)	SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
				SAVE_10GPRS(22, base)
#define REST_NVGPRS(base)	REST_GPR(13, base); REST_8GPRS(14, base); \
				REST_10GPRS(22, base)
#endif


#define SAVE_2GPRS(n, base)	SAVE_GPR(n, base); SAVE_GPR(n+1, base)
#define SAVE_4GPRS(n, base)	SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
#define SAVE_8GPRS(n, base)	SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
#define SAVE_10GPRS(n, base)	SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
#define REST_2GPRS(n, base)	REST_GPR(n, base); REST_GPR(n+1, base)
#define REST_4GPRS(n, base)	REST_2GPRS(n, base); REST_2GPRS(n+2, base)
#define REST_8GPRS(n, base)	REST_4GPRS(n, base); REST_4GPRS(n+4, base)
#define REST_10GPRS(n, base)	REST_8GPRS(n, base); REST_2GPRS(n+8, base)

#define SAVE_FPR(n, base)	stfd	n,THREAD_FPR0+8*(n)(base)
#define SAVE_2FPRS(n, base)	SAVE_FPR(n, base); SAVE_FPR(n+1, base)
#define SAVE_4FPRS(n, base)	SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
#define SAVE_8FPRS(n, base)	SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
#define SAVE_16FPRS(n, base)	SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
#define SAVE_32FPRS(n, base)	SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
#define REST_FPR(n, base)	lfd	n,THREAD_FPR0+8*(n)(base)
#define REST_2FPRS(n, base)	REST_FPR(n, base); REST_FPR(n+1, base)
#define REST_4FPRS(n, base)	REST_2FPRS(n, base); REST_2FPRS(n+2, base)
#define REST_8FPRS(n, base)	REST_4FPRS(n, base); REST_4FPRS(n+4, base)
#define REST_16FPRS(n, base)	REST_8FPRS(n, base); REST_8FPRS(n+8, base)
#define REST_32FPRS(n, base)	REST_16FPRS(n, base); REST_16FPRS(n+16, base)

#define SAVE_VR(n,b,base)	li b,THREAD_VR0+(16*(n));  stvx n,b,base
#define SAVE_2VRS(n,b,base)	SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
#define SAVE_4VRS(n,b,base)	SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
#define SAVE_8VRS(n,b,base)	SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
#define SAVE_16VRS(n,b,base)	SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
#define SAVE_32VRS(n,b,base)	SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
#define REST_VR(n,b,base)	li b,THREAD_VR0+(16*(n)); lvx n,b,base
#define REST_2VRS(n,b,base)	REST_VR(n,b,base); REST_VR(n+1,b,base)
#define REST_4VRS(n,b,base)	REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
#define REST_8VRS(n,b,base)	REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
#define REST_16VRS(n,b,base)	REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
#define REST_32VRS(n,b,base)	REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)

#define SAVE_EVR(n,s,base)	evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
#define SAVE_2EVRS(n,s,base)	SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
#define SAVE_4EVRS(n,s,base)	SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
#define SAVE_8EVRS(n,s,base)	SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
#define SAVE_16EVRS(n,s,base)	SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
#define SAVE_32EVRS(n,s,base)	SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
#define REST_EVR(n,s,base)	lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
#define REST_2EVRS(n,s,base)	REST_EVR(n,s,base); REST_EVR(n+1,s,base)
#define REST_4EVRS(n,s,base)	REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
#define REST_8EVRS(n,s,base)	REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
#define REST_16EVRS(n,s,base)	REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
#define REST_32EVRS(n,s,base)	REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)

/* Macros to adjust thread priority for Iseries hardware multithreading */
#define HMT_VERY_LOW    or   31,31,31	# very low priority\n"
#define HMT_LOW		or 1,1,1
#define HMT_MEDIUM_LOW  or   6,6,6	# medium low priority\n"
#define HMT_MEDIUM	or 2,2,2
#define HMT_MEDIUM_HIGH or   5,5,5	# medium high priority\n"
#define HMT_HIGH	or 3,3,3

/* handle instructions that older assemblers may not know */
#define RFCI		.long 0x4c000066	/* rfci instruction */
#define RFDI		.long 0x4c00004e	/* rfdi instruction */
#define RFMCI		.long 0x4c00004c	/* rfmci instruction */

/* 
 * LOADADDR( rn, name )
 *   loads the address of 'name' into 'rn'
 *
 * LOADBASE( rn, name )
 *   loads the address (less the low 16 bits) of 'name' into 'rn'
 *   suitable for base+disp addressing
 */
#ifdef __powerpc64__
#define LOADADDR(rn,name) \
	lis	rn,name##@highest;	\
	ori	rn,rn,name##@higher;	\
	rldicr	rn,rn,32,31;		\
	oris	rn,rn,name##@h;		\
	ori	rn,rn,name##@l

#define LOADBASE(rn,name) \
	lis	rn,name@highest;	\
	ori	rn,rn,name@higher;	\
	rldicr	rn,rn,32,31;		\
	oris	rn,rn,name@ha


#define SET_REG_TO_CONST(reg, value)	         	\
	lis     reg,(((value)>>48)&0xFFFF);             \
	ori     reg,reg,(((value)>>32)&0xFFFF);         \
	rldicr  reg,reg,32,31;                          \
	oris    reg,reg,(((value)>>16)&0xFFFF);         \
	ori     reg,reg,((value)&0xFFFF);

#define SET_REG_TO_LABEL(reg, label)	         	\
	lis     reg,(label)@highest;                    \
	ori     reg,reg,(label)@higher;                 \
	rldicr  reg,reg,32,31;                          \
	oris    reg,reg,(label)@h;                      \
	ori     reg,reg,(label)@l;
#endif

/* various errata or part fixups */
#ifdef CONFIG_PPC601_SYNC_FIX
#define SYNC				\
BEGIN_FTR_SECTION			\
	sync;				\
	isync;				\
END_FTR_SECTION_IFSET(CPU_FTR_601)
#define SYNC_601			\
BEGIN_FTR_SECTION			\
	sync;				\
END_FTR_SECTION_IFSET(CPU_FTR_601)
#define ISYNC_601			\
BEGIN_FTR_SECTION			\
	isync;				\
END_FTR_SECTION_IFSET(CPU_FTR_601)
#else
#define	SYNC
#define SYNC_601
#define ISYNC_601
#endif


#ifndef CONFIG_SMP
#define TLBSYNC
#else /* CONFIG_SMP */
/* tlbsync is not implemented on 601 */
#define TLBSYNC				\
BEGIN_FTR_SECTION			\
	tlbsync;			\
	sync;				\
END_FTR_SECTION_IFCLR(CPU_FTR_601)
#endif

	
/*
 * This instruction is not implemented on the PPC 603 or 601; however, on
 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
 * All of these instructions exist in the 8xx, they have magical powers,
 * and they must be used.
 */

#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
#define tlbia					\
	li	r4,1024;			\
	mtctr	r4;				\
	lis	r4,KERNELBASE@h;		\
0:	tlbie	r4;				\
	addi	r4,r4,0x1000;			\
	bdnz	0b
#endif


#ifdef CONFIG_IBM405_ERR77
#define PPC405_ERR77(ra,rb)	dcbt	ra, rb;
#define	PPC405_ERR77_SYNC	sync;
#else
#define PPC405_ERR77(ra,rb)
#define PPC405_ERR77_SYNC
#endif


#ifdef CONFIG_IBM440EP_ERR42
#define PPC440EP_ERR42 isync
#else
#define PPC440EP_ERR42
#endif


#if defined(CONFIG_BOOKE)
#define tophys(rd,rs)				\
	addis	rd,rs,0

#define tovirt(rd,rs)				\
	addis	rd,rs,0

#elif defined(CONFIG_PPC64)
/* PPPBBB - DRENG  If KERNELBASE is always 0xC0...,
 * Then we can easily do this with one asm insn. -Peter
 */
#define tophys(rd,rs)                           \
        lis     rd,((KERNELBASE>>48)&0xFFFF);   \
        rldicr  rd,rd,32,31;                    \
        sub     rd,rs,rd

#define tovirt(rd,rs)                           \
        lis     rd,((KERNELBASE>>48)&0xFFFF);   \
        rldicr  rd,rd,32,31;                    \
        add     rd,rs,rd
#else
/*
 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
 * physical base address of RAM at compile time.
 */
#define tophys(rd,rs)				\
0:	addis	rd,rs,-KERNELBASE@h;		\
	.section ".vtop_fixup","aw";		\
	.align  1;				\
	.long   0b;				\
	.previous

#define tovirt(rd,rs)				\
0:	addis	rd,rs,KERNELBASE@h;		\
	.section ".ptov_fixup","aw";		\
	.align  1;				\
	.long   0b;				\
	.previous
#endif

/*
 * On 64-bit cpus, we use the rfid instruction instead of rfi, but
 * we then have to make sure we preserve the top 32 bits except for
 * the 64-bit mode bit, which we clear.
 */
#if defined(CONFIG_PPC64BRIDGE)
#define	FIX_SRR1(ra, rb)	\
	mr	rb,ra;		\
	mfmsr	ra;		\
	clrldi	ra,ra,1;		/* turn off 64-bit mode */ \
	rldimi	ra,rb,0,32
#define	RFI		.long	0x4c000024	/* rfid instruction */
#define MTMSRD(r)	.long	(0x7c000164 + ((r) << 21))	/* mtmsrd */
#define CLR_TOP32(r)	rlwinm	(r),(r),0,0,31	/* clear top 32 bits */
#elif defined(CONFIG_PPC64)
/* Insert the high 32 bits of the MSR into what will be the new
   MSR (via SRR1 and rfid)  This preserves the MSR.SF and MSR.ISF
   bits. */

#define FIX_SRR1(ra, rb)	\
	mr	rb,ra;		\
	mfmsr	ra;		\
	rldimi	ra,rb,0,32

#define CLR_TOP32(r)	rlwinm	(r),(r),0,0,31	/* clear top 32 bits */

#else
#define FIX_SRR1(ra, rb)
#ifndef CONFIG_40x
#define	RFI		rfi
#else
#define RFI		rfi; b .	/* Prevent prefetch past rfi */
#endif
#define MTMSRD(r)	mtmsr	r
#define CLR_TOP32(r)
#endif

/* The boring bits... */

/* Condition Register Bit Fields */

#define	cr0	0
#define	cr1	1
#define	cr2	2
#define	cr3	3
#define	cr4	4
#define	cr5	5
#define	cr6	6
#define	cr7	7


/* General Purpose Registers (GPRs) */

#define	r0	0
#define	r1	1
#define	r2	2
#define	r3	3
#define	r4	4
#define	r5	5
#define	r6	6
#define	r7	7
#define	r8	8
#define	r9	9
#define	r10	10
#define	r11	11
#define	r12	12
#define	r13	13
#define	r14	14
#define	r15	15
#define	r16	16
#define	r17	17
#define	r18	18
#define	r19	19
#define	r20	20
#define	r21	21
#define	r22	22
#define	r23	23
#define	r24	24
#define	r25	25
#define	r26	26
#define	r27	27
#define	r28	28
#define	r29	29
#define	r30	30
#define	r31	31


/* Floating Point Registers (FPRs) */

#define	fr0	0
#define	fr1	1
#define	fr2	2
#define	fr3	3
#define	fr4	4
#define	fr5	5
#define	fr6	6
#define	fr7	7
#define	fr8	8
#define	fr9	9
#define	fr10	10
#define	fr11	11
#define	fr12	12
#define	fr13	13
#define	fr14	14
#define	fr15	15
#define	fr16	16
#define	fr17	17
#define	fr18	18
#define	fr19	19
#define	fr20	20
#define	fr21	21
#define	fr22	22
#define	fr23	23
#define	fr24	24
#define	fr25	25
#define	fr26	26
#define	fr27	27
#define	fr28	28
#define	fr29	29
#define	fr30	30
#define	fr31	31

/* AltiVec Registers (VPRs) */

#define	vr0	0
#define	vr1	1
#define	vr2	2
#define	vr3	3
#define	vr4	4
#define	vr5	5
#define	vr6	6
#define	vr7	7
#define	vr8	8
#define	vr9	9
#define	vr10	10
#define	vr11	11
#define	vr12	12
#define	vr13	13
#define	vr14	14
#define	vr15	15
#define	vr16	16
#define	vr17	17
#define	vr18	18
#define	vr19	19
#define	vr20	20
#define	vr21	21
#define	vr22	22
#define	vr23	23
#define	vr24	24
#define	vr25	25
#define	vr26	26
#define	vr27	27
#define	vr28	28
#define	vr29	29
#define	vr30	30
#define	vr31	31

/* SPE Registers (EVPRs) */

#define	evr0	0
#define	evr1	1
#define	evr2	2
#define	evr3	3
#define	evr4	4
#define	evr5	5
#define	evr6	6
#define	evr7	7
#define	evr8	8
#define	evr9	9
#define	evr10	10
#define	evr11	11
#define	evr12	12
#define	evr13	13
#define	evr14	14
#define	evr15	15
#define	evr16	16
#define	evr17	17
#define	evr18	18
#define	evr19	19
#define	evr20	20
#define	evr21	21
#define	evr22	22
#define	evr23	23
#define	evr24	24
#define	evr25	25
#define	evr26	26
#define	evr27	27
#define	evr28	28
#define	evr29	29
#define	evr30	30
#define	evr31	31

/* some stab codes */
#define N_FUN	36
#define N_RSYM	64
#define N_SLINE	68
#define N_SO	100

#define ASM_CONST(x) x
#else
  #define __ASM_CONST(x) x##UL
  #define ASM_CONST(x) __ASM_CONST(x)
#endif /*  __ASSEMBLY__ */

#endif /* _ASM_POWERPC_PPC_ASM_H */
Commit	Line	Data
1da177e4	1	/*
1da177e4	2	* Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
1da177e4 LT	3	*/
1da177e4 LT	4
5f7c6907 KG	5	#ifndef _ASM_POWERPC_PPC_ASM_H
	6	#define _ASM_POWERPC_PPC_ASM_H
	7
	8	#ifdef __ASSEMBLY__
1da177e4 LT	9
	10	/*
	11	* Macros for storing registers into and loading registers from
	12	* exception frames.
	13	*/
5f7c6907 KG	14	#ifdef __powerpc64__
	15	#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
	16	#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
	17	#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
	18	#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
	19	#else
1da177e4	20	#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
5f7c6907 KG	21	#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
	22	#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
	23	SAVE_10GPRS(22, base)
	24	#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
	25	REST_10GPRS(22, base)
	26	#endif
	27
	28
1da177e4 LT	29	#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
	30	#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
	31	#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
	32	#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
1da177e4 LT	33	#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
	34	#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
	35	#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
	36	#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
	37
1da177e4 LT	38	#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
	39	#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
	40	#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
	41	#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
	42	#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
	43	#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
	44	#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
	45	#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
	46	#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
	47	#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
	48	#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
	49	#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
	50
	51	#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
5f7c6907 KG	52	#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
	53	#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
	54	#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
	55	#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
	56	#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
1da177e4	57	#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
5f7c6907 KG	58	#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
	59	#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
	60	#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
	61	#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
	62	#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
1da177e4 LT	63
1da177e4 LT	64	#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
5f7c6907 KG	65	#define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
	66	#define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
	67	#define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
	68	#define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
	69	#define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
1da177e4	70	#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
5f7c6907 KG	71	#define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
	72	#define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
	73	#define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
	74	#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
	75	#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
	76
	77	/* Macros to adjust thread priority for Iseries hardware multithreading */
feaf7cf1	78	#define HMT_VERY_LOW or 31,31,31 # very low priority\n"
5f7c6907	79	#define HMT_LOW or 1,1,1
feaf7cf1	80	#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority\n"
5f7c6907	81	#define HMT_MEDIUM or 2,2,2
feaf7cf1	82	#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority\n"
5f7c6907 KG	83	#define HMT_HIGH or 3,3,3
	84
	85	/* handle instructions that older assemblers may not know */
	86	#define RFCI .long 0x4c000066 /* rfci instruction */
	87	#define RFDI .long 0x4c00004e /* rfdi instruction */
	88	#define RFMCI .long 0x4c00004c /* rfmci instruction */
	89
	90	/*
	91	* LOADADDR( rn, name )
	92	* loads the address of 'name' into 'rn'
	93	*
	94	* LOADBASE( rn, name )
	95	* loads the address (less the low 16 bits) of 'name' into 'rn'
	96	* suitable for base+disp addressing
	97	*/
	98	#ifdef __powerpc64__
	99	#define LOADADDR(rn,name) \
	100	lis rn,name##@highest; \
	101	ori rn,rn,name##@higher; \
	102	rldicr rn,rn,32,31; \
	103	oris rn,rn,name##@h; \
	104	ori rn,rn,name##@l
	105
	106	#define LOADBASE(rn,name) \
	107	lis rn,name@highest; \
	108	ori rn,rn,name@higher; \
	109	rldicr rn,rn,32,31; \
	110	oris rn,rn,name@ha
	111
	112
	113	#define SET_REG_TO_CONST(reg, value) \
	114	lis reg,(((value)>>48)&0xFFFF); \
	115	ori reg,reg,(((value)>>32)&0xFFFF); \
	116	rldicr reg,reg,32,31; \
	117	oris reg,reg,(((value)>>16)&0xFFFF); \
	118	ori reg,reg,((value)&0xFFFF);
	119
	120	#define SET_REG_TO_LABEL(reg, label) \
	121	lis reg,(label)@highest; \
	122	ori reg,reg,(label)@higher; \
	123	rldicr reg,reg,32,31; \
	124	oris reg,reg,(label)@h; \
	125	ori reg,reg,(label)@l;
	126	#endif
1da177e4	127
5f7c6907	128	/* various errata or part fixups */
1da177e4 LT	129	#ifdef CONFIG_PPC601_SYNC_FIX
	130	#define SYNC \
	131	BEGIN_FTR_SECTION \
	132	sync; \
	133	isync; \
	134	END_FTR_SECTION_IFSET(CPU_FTR_601)
	135	#define SYNC_601 \
	136	BEGIN_FTR_SECTION \
	137	sync; \
	138	END_FTR_SECTION_IFSET(CPU_FTR_601)
	139	#define ISYNC_601 \
	140	BEGIN_FTR_SECTION \
	141	isync; \
	142	END_FTR_SECTION_IFSET(CPU_FTR_601)
	143	#else
	144	#define SYNC
	145	#define SYNC_601
	146	#define ISYNC_601
	147	#endif
	148
5f7c6907	149
1da177e4 LT	150	#ifndef CONFIG_SMP
	151	#define TLBSYNC
	152	#else /* CONFIG_SMP */
	153	/* tlbsync is not implemented on 601 */
	154	#define TLBSYNC \
	155	BEGIN_FTR_SECTION \
	156	tlbsync; \
	157	sync; \
	158	END_FTR_SECTION_IFCLR(CPU_FTR_601)
	159	#endif
	160
5f7c6907	161
1da177e4 LT	162	/*
	163	* This instruction is not implemented on the PPC 603 or 601; however, on
	164	* the 403GCX and 405GP tlbia IS defined and tlbie is not.
	165	* All of these instructions exist in the 8xx, they have magical powers,
	166	* and they must be used.
	167	*/
	168
	169	#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
	170	#define tlbia \
	171	li r4,1024; \
	172	mtctr r4; \
	173	lis r4,KERNELBASE@h; \
	174	0: tlbie r4; \
	175	addi r4,r4,0x1000; \
	176	bdnz 0b
	177	#endif
	178
5f7c6907 KG	179
	180	#ifdef CONFIG_IBM405_ERR77
	181	#define PPC405_ERR77(ra,rb) dcbt ra, rb;
	182	#define PPC405_ERR77_SYNC sync;
	183	#else
	184	#define PPC405_ERR77(ra,rb)
	185	#define PPC405_ERR77_SYNC
	186	#endif
	187
	188
	189	#ifdef CONFIG_IBM440EP_ERR42
	190	#define PPC440EP_ERR42 isync
	191	#else
	192	#define PPC440EP_ERR42
	193	#endif
	194
	195
	196	#if defined(CONFIG_BOOKE)
1da177e4 LT	197	#define tophys(rd,rs) \
	198	addis rd,rs,0
	199
	200	#define tovirt(rd,rs) \
	201	addis rd,rs,0
	202
5f7c6907 KG	203	#elif defined(CONFIG_PPC64)
	204	/* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
	205	* Then we can easily do this with one asm insn. -Peter
	206	*/
	207	#define tophys(rd,rs) \
	208	lis rd,((KERNELBASE>>48)&0xFFFF); \
	209	rldicr rd,rd,32,31; \
	210	sub rd,rs,rd
	211
	212	#define tovirt(rd,rs) \
	213	lis rd,((KERNELBASE>>48)&0xFFFF); \
	214	rldicr rd,rd,32,31; \
	215	add rd,rs,rd
	216	#else
1da177e4 LT	217	/*
	218	* On APUS (Amiga PowerPC cpu upgrade board), we don't know the
	219	* physical base address of RAM at compile time.
	220	*/
	221	#define tophys(rd,rs) \
	222	0: addis rd,rs,-KERNELBASE@h; \
	223	.section ".vtop_fixup","aw"; \
	224	.align 1; \
	225	.long 0b; \
	226	.previous
	227
	228	#define tovirt(rd,rs) \
	229	0: addis rd,rs,KERNELBASE@h; \
	230	.section ".ptov_fixup","aw"; \
	231	.align 1; \
	232	.long 0b; \
	233	.previous
5f7c6907	234	#endif
1da177e4 LT	235
	236	/*
	237	* On 64-bit cpus, we use the rfid instruction instead of rfi, but
	238	* we then have to make sure we preserve the top 32 bits except for
	239	* the 64-bit mode bit, which we clear.
	240	*/
5f7c6907	241	#if defined(CONFIG_PPC64BRIDGE)
1da177e4 LT	242	#define FIX_SRR1(ra, rb) \
	243	mr rb,ra; \
	244	mfmsr ra; \
	245	clrldi ra,ra,1; /* turn off 64-bit mode */ \
	246	rldimi ra,rb,0,32
	247	#define RFI .long 0x4c000024 /* rfid instruction */
	248	#define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /* mtmsrd */
	249	#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
5f7c6907 KG	250	#elif defined(CONFIG_PPC64)
	251	/* Insert the high 32 bits of the MSR into what will be the new
	252	MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF
	253	bits. */
	254
	255	#define FIX_SRR1(ra, rb) \
	256	mr rb,ra; \
	257	mfmsr ra; \
	258	rldimi ra,rb,0,32
	259
	260	#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
1da177e4 LT	261
	262	#else
	263	#define FIX_SRR1(ra, rb)
	264	#ifndef CONFIG_40x
	265	#define RFI rfi
	266	#else
	267	#define RFI rfi; b . /* Prevent prefetch past rfi */
	268	#endif
	269	#define MTMSRD(r) mtmsr r
	270	#define CLR_TOP32(r)
c9cf73ae MP	271	#endif
c9cf73ae MP	272
1da177e4 LT	273	/* The boring bits... */
	274
	275	/* Condition Register Bit Fields */
	276
	277	#define cr0 0
	278	#define cr1 1
	279	#define cr2 2
	280	#define cr3 3
	281	#define cr4 4
	282	#define cr5 5
	283	#define cr6 6
	284	#define cr7 7
	285
	286
	287	/* General Purpose Registers (GPRs) */
	288
	289	#define r0 0
	290	#define r1 1
	291	#define r2 2
	292	#define r3 3
	293	#define r4 4
	294	#define r5 5
	295	#define r6 6
	296	#define r7 7
	297	#define r8 8
	298	#define r9 9
	299	#define r10 10
	300	#define r11 11
	301	#define r12 12
	302	#define r13 13
	303	#define r14 14
	304	#define r15 15
	305	#define r16 16
	306	#define r17 17
	307	#define r18 18
	308	#define r19 19
	309	#define r20 20
	310	#define r21 21
	311	#define r22 22
	312	#define r23 23
	313	#define r24 24
	314	#define r25 25
	315	#define r26 26
	316	#define r27 27
	317	#define r28 28
	318	#define r29 29
	319	#define r30 30
	320	#define r31 31
	321
	322
	323	/* Floating Point Registers (FPRs) */
	324
	325	#define fr0 0
	326	#define fr1 1
	327	#define fr2 2
	328	#define fr3 3
	329	#define fr4 4
	330	#define fr5 5
	331	#define fr6 6
	332	#define fr7 7
	333	#define fr8 8
	334	#define fr9 9
	335	#define fr10 10
	336	#define fr11 11
337	#define fr12 12
338	#define fr13 13
339	#define fr14 14
340	#define fr15 15
341	#define fr16 16
342	#define fr17 17
343	#define fr18 18
344	#define fr19 19
345	#define fr20 20
346	#define fr21 21
347	#define fr22 22
348	#define fr23 23
349	#define fr24 24
350	#define fr25 25
351	#define fr26 26
352	#define fr27 27
353	#define fr28 28
354	#define fr29 29
355	#define fr30 30
356	#define fr31 31
357
5f7c6907 KG	358	/* AltiVec Registers (VPRs) */
5f7c6907 KG	359
1da177e4 LT	360	#define vr0 0
	361	#define vr1 1
	362	#define vr2 2
	363	#define vr3 3
	364	#define vr4 4
	365	#define vr5 5
	366	#define vr6 6
	367	#define vr7 7
	368	#define vr8 8
	369	#define vr9 9
	370	#define vr10 10
	371	#define vr11 11
	372	#define vr12 12
	373	#define vr13 13
	374	#define vr14 14
	375	#define vr15 15
	376	#define vr16 16
	377	#define vr17 17
	378	#define vr18 18
	379	#define vr19 19
	380	#define vr20 20
	381	#define vr21 21
	382	#define vr22 22
	383	#define vr23 23
	384	#define vr24 24
	385	#define vr25 25
	386	#define vr26 26
	387	#define vr27 27
	388	#define vr28 28
	389	#define vr29 29
	390	#define vr30 30
	391	#define vr31 31
	392
5f7c6907 KG	393	/* SPE Registers (EVPRs) */
5f7c6907 KG	394
1da177e4 LT	395	#define evr0 0
	396	#define evr1 1
	397	#define evr2 2
	398	#define evr3 3
	399	#define evr4 4
	400	#define evr5 5
	401	#define evr6 6
	402	#define evr7 7
	403	#define evr8 8
	404	#define evr9 9
	405	#define evr10 10
	406	#define evr11 11
	407	#define evr12 12
	408	#define evr13 13
	409	#define evr14 14
	410	#define evr15 15
	411	#define evr16 16
	412	#define evr17 17
	413	#define evr18 18
	414	#define evr19 19
	415	#define evr20 20
	416	#define evr21 21
	417	#define evr22 22
	418	#define evr23 23
	419	#define evr24 24
	420	#define evr25 25
	421	#define evr26 26
	422	#define evr27 27
	423	#define evr28 28
	424	#define evr29 29
	425	#define evr30 30
	426	#define evr31 31
	427
	428	/* some stab codes */
	429	#define N_FUN 36
	430	#define N_RSYM 64
	431	#define N_SLINE 68
	432	#define N_SO 100
5f7c6907 KG	433
	434	#define ASM_CONST(x) x
	435	#else
	436	#define __ASM_CONST(x) x##UL
	437	#define ASM_CONST(x) __ASM_CONST(x)
	438	#endif /* __ASSEMBLY__ */
	439
	440	#endif /* _ASM_POWERPC_PPC_ASM_H */