[linux-2.6-block.git] / include / asm-powerpc / mpic.h

#ifndef _ASM_POWERPC_MPIC_H
#define _ASM_POWERPC_MPIC_H
#ifdef __KERNEL__

#include <linux/irq.h>

/*
 * Global registers
 */

#define MPIC_GREG_BASE			0x01000

#define MPIC_GREG_FEATURE_0		0x00000
#define		MPIC_GREG_FEATURE_LAST_SRC_MASK		0x07ff0000
#define		MPIC_GREG_FEATURE_LAST_SRC_SHIFT	16
#define		MPIC_GREG_FEATURE_LAST_CPU_MASK		0x00001f00
#define		MPIC_GREG_FEATURE_LAST_CPU_SHIFT	8
#define		MPIC_GREG_FEATURE_VERSION_MASK		0xff
#define MPIC_GREG_FEATURE_1		0x00010
#define MPIC_GREG_GLOBAL_CONF_0		0x00020
#define		MPIC_GREG_GCONF_RESET			0x80000000
#define		MPIC_GREG_GCONF_8259_PTHROU_DIS		0x20000000
#define		MPIC_GREG_GCONF_BASE_MASK		0x000fffff
#define MPIC_GREG_GLOBAL_CONF_1		0x00030
#define		MPIC_GREG_GLOBAL_CONF_1_SIE		0x08000000
#define		MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK	0x70000000
#define		MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r)	\
			(((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
#define MPIC_GREG_VENDOR_0		0x00040
#define MPIC_GREG_VENDOR_1		0x00050
#define MPIC_GREG_VENDOR_2		0x00060
#define MPIC_GREG_VENDOR_3		0x00070
#define MPIC_GREG_VENDOR_ID		0x00080
#define 	MPIC_GREG_VENDOR_ID_STEPPING_MASK	0x00ff0000
#define 	MPIC_GREG_VENDOR_ID_STEPPING_SHIFT	16
#define 	MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK	0x0000ff00
#define 	MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT	8
#define 	MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK	0x000000ff
#define MPIC_GREG_PROCESSOR_INIT	0x00090
#define MPIC_GREG_IPI_VECTOR_PRI_0	0x000a0
#define MPIC_GREG_IPI_VECTOR_PRI_1	0x000b0
#define MPIC_GREG_IPI_VECTOR_PRI_2	0x000c0
#define MPIC_GREG_IPI_VECTOR_PRI_3	0x000d0
#define MPIC_GREG_SPURIOUS		0x000e0
#define MPIC_GREG_TIMER_FREQ		0x000f0

/*
 *
 * Timer registers
 */
#define MPIC_TIMER_BASE			0x01100
#define MPIC_TIMER_STRIDE		0x40

#define MPIC_TIMER_CURRENT_CNT		0x00000
#define MPIC_TIMER_BASE_CNT		0x00010
#define MPIC_TIMER_VECTOR_PRI		0x00020
#define MPIC_TIMER_DESTINATION		0x00030

/*
 * Per-Processor registers
 */

#define MPIC_CPU_THISBASE		0x00000
#define MPIC_CPU_BASE			0x20000
#define MPIC_CPU_STRIDE			0x01000

#define MPIC_CPU_IPI_DISPATCH_0		0x00040
#define MPIC_CPU_IPI_DISPATCH_1		0x00050
#define MPIC_CPU_IPI_DISPATCH_2		0x00060
#define MPIC_CPU_IPI_DISPATCH_3		0x00070
#define MPIC_CPU_CURRENT_TASK_PRI	0x00080
#define 	MPIC_CPU_TASKPRI_MASK			0x0000000f
#define MPIC_CPU_WHOAMI			0x00090
#define 	MPIC_CPU_WHOAMI_MASK			0x0000001f
#define MPIC_CPU_INTACK			0x000a0
#define MPIC_CPU_EOI			0x000b0

/*
 * Per-source registers
 */

#define MPIC_IRQ_BASE			0x10000
#define MPIC_IRQ_STRIDE			0x00020
#define MPIC_IRQ_VECTOR_PRI		0x00000
#define 	MPIC_VECPRI_MASK			0x80000000
#define 	MPIC_VECPRI_ACTIVITY			0x40000000	/* Read Only */
#define 	MPIC_VECPRI_PRIORITY_MASK		0x000f0000
#define 	MPIC_VECPRI_PRIORITY_SHIFT		16
#define 	MPIC_VECPRI_VECTOR_MASK			0x000007ff
#define 	MPIC_VECPRI_POLARITY_POSITIVE		0x00800000
#define 	MPIC_VECPRI_POLARITY_NEGATIVE		0x00000000
#define 	MPIC_VECPRI_POLARITY_MASK		0x00800000
#define 	MPIC_VECPRI_SENSE_LEVEL			0x00400000
#define 	MPIC_VECPRI_SENSE_EDGE			0x00000000
#define 	MPIC_VECPRI_SENSE_MASK			0x00400000
#define MPIC_IRQ_DESTINATION		0x00010

#define MPIC_MAX_IRQ_SOURCES	2048
#define MPIC_MAX_CPUS		32
#define MPIC_MAX_ISU		32

/*
 * Special vector numbers (internal use only)
 */
#define MPIC_VEC_SPURRIOUS	255
#define MPIC_VEC_IPI_3		254
#define MPIC_VEC_IPI_2		253
#define MPIC_VEC_IPI_1		252
#define MPIC_VEC_IPI_0		251

/* unused */
#define MPIC_VEC_TIMER_3	250
#define MPIC_VEC_TIMER_2	249
#define MPIC_VEC_TIMER_1	248
#define MPIC_VEC_TIMER_0	247

#ifdef CONFIG_MPIC_BROKEN_U3
/* Fixup table entry */
struct mpic_irq_fixup
{
	u8 __iomem	*base;
	u8 __iomem	*applebase;
	u32		data;
	unsigned int	index;
};
#endif /* CONFIG_MPIC_BROKEN_U3 */


/* The instance data of a given MPIC */
struct mpic
{
	/* The "linux" controller struct */
	struct irq_chip		hc_irq;
#ifdef CONFIG_MPIC_BROKEN_U3
	struct irq_chip		hc_ht_irq;
#endif
#ifdef CONFIG_SMP
	struct irq_chip		hc_ipi;
#endif
	const char		*name;
	/* Flags */
	unsigned int		flags;
	/* How many irq sources in a given ISU */
	unsigned int		isu_size;
	unsigned int		isu_shift;
	unsigned int		isu_mask;
	/* Offset of irq vector numbers */
	unsigned int		irq_offset;	
	unsigned int		irq_count;
	/* Offset of ipi vector numbers */
	unsigned int		ipi_offset;
	/* Number of sources */
	unsigned int		num_sources;
	/* Number of CPUs */
	unsigned int		num_cpus;
	/* senses array */
	unsigned char		*senses;
	unsigned int		senses_count;

#ifdef CONFIG_MPIC_BROKEN_U3
	/* The fixup table */
	struct mpic_irq_fixup	*fixups;
	spinlock_t		fixup_lock;
#endif

	/* The various ioremap'ed bases */
	volatile u32 __iomem	*gregs;
	volatile u32 __iomem	*tmregs;
	volatile u32 __iomem	*cpuregs[MPIC_MAX_CPUS];
	volatile u32 __iomem	*isus[MPIC_MAX_ISU];

	/* link */
	struct mpic		*next;
};

/* This is the primary controller, only that one has IPIs and
 * has afinity control. A non-primary MPIC always uses CPU0
 * registers only
 */
#define MPIC_PRIMARY			0x00000001
/* Set this for a big-endian MPIC */
#define MPIC_BIG_ENDIAN			0x00000002
/* Broken U3 MPIC */
#define MPIC_BROKEN_U3			0x00000004
/* Broken IPI registers (autodetected) */
#define MPIC_BROKEN_IPI			0x00000008
/* MPIC wants a reset */
#define MPIC_WANTS_RESET		0x00000010

/* Allocate the controller structure and setup the linux irq descs
 * for the range if interrupts passed in. No HW initialization is
 * actually performed.
 * 
 * @phys_addr:	physial base address of the MPIC
 * @flags:	flags, see constants above
 * @isu_size:	number of interrupts in an ISU. Use 0 to use a
 *              standard ISU-less setup (aka powermac)
 * @irq_offset: first irq number to assign to this mpic
 * @irq_count:  number of irqs to use with this mpic IRQ sources. Pass 0
 *	        to match the number of sources
 * @ipi_offset: first irq number to assign to this mpic IPI sources,
 *		used only on primary mpic
 * @senses:	array of sense values
 * @senses_num: number of entries in the array
 *
 * Note about the sense array. If none is passed, all interrupts are
 * setup to be level negative unless MPIC_BROKEN_U3 is set in which
 * case they are edge positive (and the array is ignored anyway).
 * The values in the array start at the first source of the MPIC,
 * that is senses[0] correspond to linux irq "irq_offset".
 */
extern struct mpic *mpic_alloc(unsigned long phys_addr,
			       unsigned int flags,
			       unsigned int isu_size,
			       unsigned int irq_offset,
			       unsigned int irq_count,
			       unsigned int ipi_offset,
			       unsigned char *senses,
			       unsigned int senses_num,
			       const char *name);

/* Assign ISUs, to call before mpic_init()
 *
 * @mpic:	controller structure as returned by mpic_alloc()
 * @isu_num:	ISU number
 * @phys_addr:	physical address of the ISU
 */
extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
			    unsigned long phys_addr);

/* Initialize the controller. After this has been called, none of the above
 * should be called again for this mpic
 */
extern void mpic_init(struct mpic *mpic);

/*
 * All of the following functions must only be used after the
 * ISUs have been assigned and the controller fully initialized
 * with mpic_init()
 */


/* Change/Read the priority of an interrupt. Default is 8 for irqs and
 * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
 * IPI number is then the offset'ed (linux irq number mapped to the IPI)
 */
extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
extern unsigned int mpic_irq_get_priority(unsigned int irq);

/* Setup a non-boot CPU */
extern void mpic_setup_this_cpu(void);

/* Clean up for kexec (or cpu offline or ...) */
extern void mpic_teardown_this_cpu(int secondary);

/* Get the current cpu priority for this cpu (0..15) */
extern int mpic_cpu_get_priority(void);

/* Set the current cpu priority for this cpu */
extern void mpic_cpu_set_priority(int prio);

/* Request IPIs on primary mpic */
extern void mpic_request_ipis(void);

/* Send an IPI (non offseted number 0..3) */
extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);

/* Send a message (IPI) to a given target (cpu number or MSG_*) */
void smp_mpic_message_pass(int target, int msg);

/* Fetch interrupt from a given mpic */
extern int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs);
/* This one gets to the primary mpic */
extern int mpic_get_irq(struct pt_regs *regs);

/* Set the EPIC clock ratio */
void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);

/* Enable/Disable EPIC serial interrupt mode */
void mpic_set_serial_int(struct mpic *mpic, int enable);

/* global mpic for pSeries */
extern struct mpic *pSeries_mpic;

#endif /* __KERNEL__ */
#endif	/* _ASM_POWERPC_MPIC_H */
Commit	Line	Data
bbeb3f4c SR	1	#ifndef _ASM_POWERPC_MPIC_H
bbeb3f4c SR	2	#define _ASM_POWERPC_MPIC_H
88ced031	3	#ifdef __KERNEL__
bbeb3f4c	4
14cf11af PM	5	#include <linux/irq.h>
	6
	7	/*
	8	* Global registers
	9	*/
	10
	11	#define MPIC_GREG_BASE 0x01000
	12
	13	#define MPIC_GREG_FEATURE_0 0x00000
	14	#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
	15	#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
	16	#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
	17	#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
	18	#define MPIC_GREG_FEATURE_VERSION_MASK 0xff
	19	#define MPIC_GREG_FEATURE_1 0x00010
	20	#define MPIC_GREG_GLOBAL_CONF_0 0x00020
	21	#define MPIC_GREG_GCONF_RESET 0x80000000
	22	#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
	23	#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
	24	#define MPIC_GREG_GLOBAL_CONF_1 0x00030
868ea0c9 MG	25	#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000
	26	#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000
	27	#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \
	28	(((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
14cf11af PM	29	#define MPIC_GREG_VENDOR_0 0x00040
	30	#define MPIC_GREG_VENDOR_1 0x00050
	31	#define MPIC_GREG_VENDOR_2 0x00060
	32	#define MPIC_GREG_VENDOR_3 0x00070
	33	#define MPIC_GREG_VENDOR_ID 0x00080
	34	#define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000
	35	#define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16
	36	#define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
	37	#define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8
	38	#define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
	39	#define MPIC_GREG_PROCESSOR_INIT 0x00090
	40	#define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0
	41	#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
	42	#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
	43	#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
	44	#define MPIC_GREG_SPURIOUS 0x000e0
	45	#define MPIC_GREG_TIMER_FREQ 0x000f0
	46
	47	/*
	48	*
	49	* Timer registers
	50	*/
	51	#define MPIC_TIMER_BASE 0x01100
	52	#define MPIC_TIMER_STRIDE 0x40
	53
	54	#define MPIC_TIMER_CURRENT_CNT 0x00000
	55	#define MPIC_TIMER_BASE_CNT 0x00010
	56	#define MPIC_TIMER_VECTOR_PRI 0x00020
	57	#define MPIC_TIMER_DESTINATION 0x00030
	58
	59	/*
	60	* Per-Processor registers
	61	*/
	62
	63	#define MPIC_CPU_THISBASE 0x00000
	64	#define MPIC_CPU_BASE 0x20000
	65	#define MPIC_CPU_STRIDE 0x01000
	66
	67	#define MPIC_CPU_IPI_DISPATCH_0 0x00040
	68	#define MPIC_CPU_IPI_DISPATCH_1 0x00050
	69	#define MPIC_CPU_IPI_DISPATCH_2 0x00060
	70	#define MPIC_CPU_IPI_DISPATCH_3 0x00070
	71	#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
	72	#define MPIC_CPU_TASKPRI_MASK 0x0000000f
	73	#define MPIC_CPU_WHOAMI 0x00090
	74	#define MPIC_CPU_WHOAMI_MASK 0x0000001f
	75	#define MPIC_CPU_INTACK 0x000a0
	76	#define MPIC_CPU_EOI 0x000b0
	77
	78	/*
	79	* Per-source registers
	80	*/
	81
	82	#define MPIC_IRQ_BASE 0x10000
	83	#define MPIC_IRQ_STRIDE 0x00020
	84	#define MPIC_IRQ_VECTOR_PRI 0x00000
	85	#define MPIC_VECPRI_MASK 0x80000000
	86	#define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
	87	#define MPIC_VECPRI_PRIORITY_MASK 0x000f0000
	88	#define MPIC_VECPRI_PRIORITY_SHIFT 16
	89	#define MPIC_VECPRI_VECTOR_MASK 0x000007ff
	90	#define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
	91	#define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
	92	#define MPIC_VECPRI_POLARITY_MASK 0x00800000
93	#define MPIC_VECPRI_SENSE_LEVEL 0x00400000
94	#define MPIC_VECPRI_SENSE_EDGE 0x00000000
95	#define MPIC_VECPRI_SENSE_MASK 0x00400000
96	#define MPIC_IRQ_DESTINATION 0x00010
97
98	#define MPIC_MAX_IRQ_SOURCES 2048
99	#define MPIC_MAX_CPUS 32
100	#define MPIC_MAX_ISU 32
101
102	/*
103	* Special vector numbers (internal use only)
104	*/
105	#define MPIC_VEC_SPURRIOUS 255
106	#define MPIC_VEC_IPI_3 254
107	#define MPIC_VEC_IPI_2 253
108	#define MPIC_VEC_IPI_1 252
109	#define MPIC_VEC_IPI_0 251
110
111	/* unused */
112	#define MPIC_VEC_TIMER_3 250
113	#define MPIC_VEC_TIMER_2 249
114	#define MPIC_VEC_TIMER_1 248
115	#define MPIC_VEC_TIMER_0 247
116
14cf11af PM	117	#ifdef CONFIG_MPIC_BROKEN_U3
	118	/* Fixup table entry */
	119	struct mpic_irq_fixup
	120	{
	121	u8 __iomem *base;
1beb6a7d	122	u8 __iomem *applebase;
c4b22f26	123	u32 data;
1beb6a7d	124	unsigned int index;
14cf11af PM	125	};
	126	#endif /* CONFIG_MPIC_BROKEN_U3 */
	127
	128
	129	/* The instance data of a given MPIC */
	130	struct mpic
	131	{
	132	/* The "linux" controller struct */
b9e5b4e6 BH	133	struct irq_chip hc_irq;
	134	#ifdef CONFIG_MPIC_BROKEN_U3
	135	struct irq_chip hc_ht_irq;
	136	#endif
14cf11af	137	#ifdef CONFIG_SMP
b9e5b4e6	138	struct irq_chip hc_ipi;
14cf11af PM	139	#endif
	140	const char *name;
	141	/* Flags */
	142	unsigned int flags;
	143	/* How many irq sources in a given ISU */
	144	unsigned int isu_size;
	145	unsigned int isu_shift;
	146	unsigned int isu_mask;
	147	/* Offset of irq vector numbers */
	148	unsigned int irq_offset;
	149	unsigned int irq_count;
	150	/* Offset of ipi vector numbers */
	151	unsigned int ipi_offset;
	152	/* Number of sources */
	153	unsigned int num_sources;
	154	/* Number of CPUs */
	155	unsigned int num_cpus;
14cf11af PM	156	/* senses array */
	157	unsigned char *senses;
	158	unsigned int senses_count;
	159
	160	#ifdef CONFIG_MPIC_BROKEN_U3
	161	/* The fixup table */
	162	struct mpic_irq_fixup *fixups;
	163	spinlock_t fixup_lock;
	164	#endif
	165
	166	/* The various ioremap'ed bases */
	167	volatile u32 __iomem *gregs;
	168	volatile u32 __iomem *tmregs;
	169	volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS];
	170	volatile u32 __iomem *isus[MPIC_MAX_ISU];
	171
	172	/* link */
	173	struct mpic *next;
	174	};
	175
	176	/* This is the primary controller, only that one has IPIs and
	177	* has afinity control. A non-primary MPIC always uses CPU0
	178	* registers only
	179	*/
	180	#define MPIC_PRIMARY 0x00000001
	181	/* Set this for a big-endian MPIC */
	182	#define MPIC_BIG_ENDIAN 0x00000002
	183	/* Broken U3 MPIC */
	184	#define MPIC_BROKEN_U3 0x00000004
	185	/* Broken IPI registers (autodetected) */
	186	#define MPIC_BROKEN_IPI 0x00000008
	187	/* MPIC wants a reset */
	188	#define MPIC_WANTS_RESET 0x00000010
	189
	190	/* Allocate the controller structure and setup the linux irq descs
	191	* for the range if interrupts passed in. No HW initialization is
	192	* actually performed.
	193	*
	194	* @phys_addr: physial base address of the MPIC
	195	* @flags: flags, see constants above
	196	* @isu_size: number of interrupts in an ISU. Use 0 to use a
	197	* standard ISU-less setup (aka powermac)
	198	* @irq_offset: first irq number to assign to this mpic
	199	* @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0
	200	* to match the number of sources
	201	* @ipi_offset: first irq number to assign to this mpic IPI sources,
	202	* used only on primary mpic
	203	* @senses: array of sense values
	204	* @senses_num: number of entries in the array
	205	*
	206	* Note about the sense array. If none is passed, all interrupts are
	207	* setup to be level negative unless MPIC_BROKEN_U3 is set in which
	208	* case they are edge positive (and the array is ignored anyway).
	209	* The values in the array start at the first source of the MPIC,
	210	* that is senses[0] correspond to linux irq "irq_offset".
	211	*/
	212	extern struct mpic *mpic_alloc(unsigned long phys_addr,
	213	unsigned int flags,
	214	unsigned int isu_size,
	215	unsigned int irq_offset,
	216	unsigned int irq_count,
	217	unsigned int ipi_offset,
	218	unsigned char *senses,
	219	unsigned int senses_num,
220	const char *name);
221
222	/* Assign ISUs, to call before mpic_init()
223	*
224	* @mpic: controller structure as returned by mpic_alloc()
225	* @isu_num: ISU number
226	* @phys_addr: physical address of the ISU
227	*/
228	extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
229	unsigned long phys_addr);
230
231	/* Initialize the controller. After this has been called, none of the above
232	* should be called again for this mpic
233	*/
234	extern void mpic_init(struct mpic *mpic);
235
14cf11af PM	236	/*
	237	* All of the following functions must only be used after the
	238	* ISUs have been assigned and the controller fully initialized
	239	* with mpic_init()
	240	*/
	241
	242
	243	/* Change/Read the priority of an interrupt. Default is 8 for irqs and
	244	* 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
	245	* IPI number is then the offset'ed (linux irq number mapped to the IPI)
	246	*/
	247	extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
	248	extern unsigned int mpic_irq_get_priority(unsigned int irq);
	249
	250	/* Setup a non-boot CPU */
	251	extern void mpic_setup_this_cpu(void);
	252
	253	/* Clean up for kexec (or cpu offline or ...) */
	254	extern void mpic_teardown_this_cpu(int secondary);
	255
	256	/* Get the current cpu priority for this cpu (0..15) */
	257	extern int mpic_cpu_get_priority(void);
	258
	259	/* Set the current cpu priority for this cpu */
	260	extern void mpic_cpu_set_priority(int prio);
	261
	262	/* Request IPIs on primary mpic */
	263	extern void mpic_request_ipis(void);
	264
	265	/* Send an IPI (non offseted number 0..3) */
	266	extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
	267
a9c59264 PM	268	/* Send a message (IPI) to a given target (cpu number or MSG_) /
	269	void smp_mpic_message_pass(int target, int msg);
	270
14cf11af PM	271	/* Fetch interrupt from a given mpic */
	272	extern int mpic_get_one_irq(struct mpic mpic, struct pt_regs regs);
	273	/* This one gets to the primary mpic */
	274	extern int mpic_get_irq(struct pt_regs *regs);
	275
868ea0c9 MG	276	/* Set the EPIC clock ratio */
	277	void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
	278
	279	/* Enable/Disable EPIC serial interrupt mode */
	280	void mpic_set_serial_int(struct mpic *mpic, int enable);
	281
14cf11af PM	282	/* global mpic for pSeries */
14cf11af PM	283	extern struct mpic *pSeries_mpic;
bbeb3f4c	284
88ced031	285	#endif /* __KERNEL__ */
bbeb3f4c	286	#endif /* _ASM_POWERPC_MPIC_H */