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bbeb3f4c SR |
1 | #ifndef _ASM_POWERPC_MPIC_H |
2 | #define _ASM_POWERPC_MPIC_H | |
88ced031 | 3 | #ifdef __KERNEL__ |
bbeb3f4c | 4 | |
14cf11af PM |
5 | #include <linux/irq.h> |
6 | ||
7 | /* | |
8 | * Global registers | |
9 | */ | |
10 | ||
11 | #define MPIC_GREG_BASE 0x01000 | |
12 | ||
13 | #define MPIC_GREG_FEATURE_0 0x00000 | |
14 | #define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000 | |
15 | #define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16 | |
16 | #define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00 | |
17 | #define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8 | |
18 | #define MPIC_GREG_FEATURE_VERSION_MASK 0xff | |
19 | #define MPIC_GREG_FEATURE_1 0x00010 | |
20 | #define MPIC_GREG_GLOBAL_CONF_0 0x00020 | |
21 | #define MPIC_GREG_GCONF_RESET 0x80000000 | |
22 | #define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 | |
23 | #define MPIC_GREG_GCONF_BASE_MASK 0x000fffff | |
24 | #define MPIC_GREG_GLOBAL_CONF_1 0x00030 | |
868ea0c9 MG |
25 | #define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000 |
26 | #define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000 | |
27 | #define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \ | |
28 | (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK) | |
14cf11af PM |
29 | #define MPIC_GREG_VENDOR_0 0x00040 |
30 | #define MPIC_GREG_VENDOR_1 0x00050 | |
31 | #define MPIC_GREG_VENDOR_2 0x00060 | |
32 | #define MPIC_GREG_VENDOR_3 0x00070 | |
33 | #define MPIC_GREG_VENDOR_ID 0x00080 | |
34 | #define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000 | |
35 | #define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16 | |
36 | #define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00 | |
37 | #define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8 | |
38 | #define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff | |
39 | #define MPIC_GREG_PROCESSOR_INIT 0x00090 | |
40 | #define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0 | |
41 | #define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0 | |
42 | #define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0 | |
43 | #define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0 | |
44 | #define MPIC_GREG_SPURIOUS 0x000e0 | |
45 | #define MPIC_GREG_TIMER_FREQ 0x000f0 | |
46 | ||
47 | /* | |
48 | * | |
49 | * Timer registers | |
50 | */ | |
51 | #define MPIC_TIMER_BASE 0x01100 | |
52 | #define MPIC_TIMER_STRIDE 0x40 | |
53 | ||
54 | #define MPIC_TIMER_CURRENT_CNT 0x00000 | |
55 | #define MPIC_TIMER_BASE_CNT 0x00010 | |
56 | #define MPIC_TIMER_VECTOR_PRI 0x00020 | |
57 | #define MPIC_TIMER_DESTINATION 0x00030 | |
58 | ||
59 | /* | |
60 | * Per-Processor registers | |
61 | */ | |
62 | ||
63 | #define MPIC_CPU_THISBASE 0x00000 | |
64 | #define MPIC_CPU_BASE 0x20000 | |
65 | #define MPIC_CPU_STRIDE 0x01000 | |
66 | ||
67 | #define MPIC_CPU_IPI_DISPATCH_0 0x00040 | |
68 | #define MPIC_CPU_IPI_DISPATCH_1 0x00050 | |
69 | #define MPIC_CPU_IPI_DISPATCH_2 0x00060 | |
70 | #define MPIC_CPU_IPI_DISPATCH_3 0x00070 | |
71 | #define MPIC_CPU_CURRENT_TASK_PRI 0x00080 | |
72 | #define MPIC_CPU_TASKPRI_MASK 0x0000000f | |
73 | #define MPIC_CPU_WHOAMI 0x00090 | |
74 | #define MPIC_CPU_WHOAMI_MASK 0x0000001f | |
75 | #define MPIC_CPU_INTACK 0x000a0 | |
76 | #define MPIC_CPU_EOI 0x000b0 | |
77 | ||
78 | /* | |
79 | * Per-source registers | |
80 | */ | |
81 | ||
82 | #define MPIC_IRQ_BASE 0x10000 | |
83 | #define MPIC_IRQ_STRIDE 0x00020 | |
84 | #define MPIC_IRQ_VECTOR_PRI 0x00000 | |
85 | #define MPIC_VECPRI_MASK 0x80000000 | |
86 | #define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */ | |
87 | #define MPIC_VECPRI_PRIORITY_MASK 0x000f0000 | |
88 | #define MPIC_VECPRI_PRIORITY_SHIFT 16 | |
89 | #define MPIC_VECPRI_VECTOR_MASK 0x000007ff | |
90 | #define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000 | |
91 | #define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000 | |
92 | #define MPIC_VECPRI_POLARITY_MASK 0x00800000 | |
93 | #define MPIC_VECPRI_SENSE_LEVEL 0x00400000 | |
94 | #define MPIC_VECPRI_SENSE_EDGE 0x00000000 | |
95 | #define MPIC_VECPRI_SENSE_MASK 0x00400000 | |
96 | #define MPIC_IRQ_DESTINATION 0x00010 | |
97 | ||
98 | #define MPIC_MAX_IRQ_SOURCES 2048 | |
99 | #define MPIC_MAX_CPUS 32 | |
100 | #define MPIC_MAX_ISU 32 | |
101 | ||
102 | /* | |
103 | * Special vector numbers (internal use only) | |
104 | */ | |
105 | #define MPIC_VEC_SPURRIOUS 255 | |
106 | #define MPIC_VEC_IPI_3 254 | |
107 | #define MPIC_VEC_IPI_2 253 | |
108 | #define MPIC_VEC_IPI_1 252 | |
109 | #define MPIC_VEC_IPI_0 251 | |
110 | ||
111 | /* unused */ | |
112 | #define MPIC_VEC_TIMER_3 250 | |
113 | #define MPIC_VEC_TIMER_2 249 | |
114 | #define MPIC_VEC_TIMER_1 248 | |
115 | #define MPIC_VEC_TIMER_0 247 | |
116 | ||
14cf11af PM |
117 | #ifdef CONFIG_MPIC_BROKEN_U3 |
118 | /* Fixup table entry */ | |
119 | struct mpic_irq_fixup | |
120 | { | |
121 | u8 __iomem *base; | |
1beb6a7d | 122 | u8 __iomem *applebase; |
c4b22f26 | 123 | u32 data; |
1beb6a7d | 124 | unsigned int index; |
14cf11af PM |
125 | }; |
126 | #endif /* CONFIG_MPIC_BROKEN_U3 */ | |
127 | ||
128 | ||
129 | /* The instance data of a given MPIC */ | |
130 | struct mpic | |
131 | { | |
0ebfff14 BH |
132 | /* The device node of the interrupt controller */ |
133 | struct device_node *of_node; | |
134 | ||
135 | /* The remapper for this MPIC */ | |
136 | struct irq_host *irqhost; | |
137 | ||
14cf11af | 138 | /* The "linux" controller struct */ |
b9e5b4e6 BH |
139 | struct irq_chip hc_irq; |
140 | #ifdef CONFIG_MPIC_BROKEN_U3 | |
141 | struct irq_chip hc_ht_irq; | |
142 | #endif | |
14cf11af | 143 | #ifdef CONFIG_SMP |
b9e5b4e6 | 144 | struct irq_chip hc_ipi; |
14cf11af PM |
145 | #endif |
146 | const char *name; | |
147 | /* Flags */ | |
148 | unsigned int flags; | |
149 | /* How many irq sources in a given ISU */ | |
150 | unsigned int isu_size; | |
151 | unsigned int isu_shift; | |
152 | unsigned int isu_mask; | |
14cf11af | 153 | unsigned int irq_count; |
14cf11af PM |
154 | /* Number of sources */ |
155 | unsigned int num_sources; | |
156 | /* Number of CPUs */ | |
157 | unsigned int num_cpus; | |
0ebfff14 | 158 | /* default senses array */ |
14cf11af PM |
159 | unsigned char *senses; |
160 | unsigned int senses_count; | |
161 | ||
162 | #ifdef CONFIG_MPIC_BROKEN_U3 | |
163 | /* The fixup table */ | |
164 | struct mpic_irq_fixup *fixups; | |
165 | spinlock_t fixup_lock; | |
166 | #endif | |
167 | ||
168 | /* The various ioremap'ed bases */ | |
169 | volatile u32 __iomem *gregs; | |
170 | volatile u32 __iomem *tmregs; | |
171 | volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS]; | |
172 | volatile u32 __iomem *isus[MPIC_MAX_ISU]; | |
173 | ||
174 | /* link */ | |
175 | struct mpic *next; | |
176 | }; | |
177 | ||
178 | /* This is the primary controller, only that one has IPIs and | |
179 | * has afinity control. A non-primary MPIC always uses CPU0 | |
180 | * registers only | |
181 | */ | |
182 | #define MPIC_PRIMARY 0x00000001 | |
183 | /* Set this for a big-endian MPIC */ | |
184 | #define MPIC_BIG_ENDIAN 0x00000002 | |
185 | /* Broken U3 MPIC */ | |
186 | #define MPIC_BROKEN_U3 0x00000004 | |
187 | /* Broken IPI registers (autodetected) */ | |
188 | #define MPIC_BROKEN_IPI 0x00000008 | |
189 | /* MPIC wants a reset */ | |
190 | #define MPIC_WANTS_RESET 0x00000010 | |
191 | ||
192 | /* Allocate the controller structure and setup the linux irq descs | |
193 | * for the range if interrupts passed in. No HW initialization is | |
194 | * actually performed. | |
195 | * | |
196 | * @phys_addr: physial base address of the MPIC | |
197 | * @flags: flags, see constants above | |
198 | * @isu_size: number of interrupts in an ISU. Use 0 to use a | |
199 | * standard ISU-less setup (aka powermac) | |
200 | * @irq_offset: first irq number to assign to this mpic | |
201 | * @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0 | |
202 | * to match the number of sources | |
203 | * @ipi_offset: first irq number to assign to this mpic IPI sources, | |
204 | * used only on primary mpic | |
205 | * @senses: array of sense values | |
206 | * @senses_num: number of entries in the array | |
207 | * | |
208 | * Note about the sense array. If none is passed, all interrupts are | |
209 | * setup to be level negative unless MPIC_BROKEN_U3 is set in which | |
210 | * case they are edge positive (and the array is ignored anyway). | |
211 | * The values in the array start at the first source of the MPIC, | |
212 | * that is senses[0] correspond to linux irq "irq_offset". | |
213 | */ | |
0ebfff14 BH |
214 | extern struct mpic *mpic_alloc(struct device_node *node, |
215 | unsigned long phys_addr, | |
14cf11af PM |
216 | unsigned int flags, |
217 | unsigned int isu_size, | |
14cf11af | 218 | unsigned int irq_count, |
14cf11af PM |
219 | const char *name); |
220 | ||
221 | /* Assign ISUs, to call before mpic_init() | |
222 | * | |
223 | * @mpic: controller structure as returned by mpic_alloc() | |
224 | * @isu_num: ISU number | |
225 | * @phys_addr: physical address of the ISU | |
226 | */ | |
227 | extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, | |
228 | unsigned long phys_addr); | |
229 | ||
0ebfff14 BH |
230 | /* Set default sense codes |
231 | * | |
232 | * @mpic: controller | |
233 | * @senses: array of sense codes | |
234 | * @count: size of above array | |
235 | * | |
236 | * Optionally provide an array (indexed on hardware interrupt numbers | |
237 | * for this MPIC) of default sense codes for the chip. Those are linux | |
238 | * sense codes IRQ_TYPE_* | |
239 | * | |
240 | * The driver gets ownership of the pointer, don't dispose of it or | |
241 | * anything like that. __init only. | |
242 | */ | |
243 | extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count); | |
244 | ||
245 | ||
14cf11af PM |
246 | /* Initialize the controller. After this has been called, none of the above |
247 | * should be called again for this mpic | |
248 | */ | |
249 | extern void mpic_init(struct mpic *mpic); | |
250 | ||
14cf11af PM |
251 | /* |
252 | * All of the following functions must only be used after the | |
253 | * ISUs have been assigned and the controller fully initialized | |
254 | * with mpic_init() | |
255 | */ | |
256 | ||
257 | ||
258 | /* Change/Read the priority of an interrupt. Default is 8 for irqs and | |
259 | * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the | |
260 | * IPI number is then the offset'ed (linux irq number mapped to the IPI) | |
261 | */ | |
262 | extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri); | |
263 | extern unsigned int mpic_irq_get_priority(unsigned int irq); | |
264 | ||
265 | /* Setup a non-boot CPU */ | |
266 | extern void mpic_setup_this_cpu(void); | |
267 | ||
268 | /* Clean up for kexec (or cpu offline or ...) */ | |
269 | extern void mpic_teardown_this_cpu(int secondary); | |
270 | ||
271 | /* Get the current cpu priority for this cpu (0..15) */ | |
272 | extern int mpic_cpu_get_priority(void); | |
273 | ||
274 | /* Set the current cpu priority for this cpu */ | |
275 | extern void mpic_cpu_set_priority(int prio); | |
276 | ||
277 | /* Request IPIs on primary mpic */ | |
278 | extern void mpic_request_ipis(void); | |
279 | ||
280 | /* Send an IPI (non offseted number 0..3) */ | |
281 | extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask); | |
282 | ||
a9c59264 PM |
283 | /* Send a message (IPI) to a given target (cpu number or MSG_*) */ |
284 | void smp_mpic_message_pass(int target, int msg); | |
285 | ||
14cf11af | 286 | /* Fetch interrupt from a given mpic */ |
0ebfff14 | 287 | extern unsigned int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs); |
14cf11af | 288 | /* This one gets to the primary mpic */ |
0ebfff14 | 289 | extern unsigned int mpic_get_irq(struct pt_regs *regs); |
14cf11af | 290 | |
868ea0c9 MG |
291 | /* Set the EPIC clock ratio */ |
292 | void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio); | |
293 | ||
294 | /* Enable/Disable EPIC serial interrupt mode */ | |
295 | void mpic_set_serial_int(struct mpic *mpic, int enable); | |
296 | ||
88ced031 | 297 | #endif /* __KERNEL__ */ |
bbeb3f4c | 298 | #endif /* _ASM_POWERPC_MPIC_H */ |