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047ea784 PM |
1 | #ifndef _ASM_POWERPC_MMU_H_ |
2 | #define _ASM_POWERPC_MMU_H_ | |
88ced031 | 3 | #ifdef __KERNEL__ |
047ea784 PM |
4 | |
5 | #ifndef CONFIG_PPC64 | |
6 | #include <asm-ppc/mmu.h> | |
7 | #else | |
8 | ||
1da177e4 LT |
9 | /* |
10 | * PowerPC memory management structures | |
11 | * | |
12 | * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com> | |
13 | * PPC64 rework. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License | |
17 | * as published by the Free Software Foundation; either version | |
18 | * 2 of the License, or (at your option) any later version. | |
19 | */ | |
20 | ||
3ddfbcf1 | 21 | #include <asm/asm-compat.h> |
1da177e4 | 22 | #include <asm/page.h> |
1da177e4 | 23 | |
1f8d419e DG |
24 | /* |
25 | * Segment table | |
26 | */ | |
1da177e4 LT |
27 | |
28 | #define STE_ESID_V 0x80 | |
29 | #define STE_ESID_KS 0x20 | |
30 | #define STE_ESID_KP 0x10 | |
31 | #define STE_ESID_N 0x08 | |
32 | ||
33 | #define STE_VSID_SHIFT 12 | |
34 | ||
1f8d419e | 35 | /* Location of cpu0's segment table */ |
c59c464a | 36 | #define STAB0_PAGE 0x6 |
758438a7 ME |
37 | #define STAB0_OFFSET (STAB0_PAGE << 12) |
38 | #define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START) | |
c59c464a DG |
39 | |
40 | #ifndef __ASSEMBLY__ | |
41 | extern char initial_stab[]; | |
42 | #endif /* ! __ASSEMBLY */ | |
1f8d419e DG |
43 | |
44 | /* | |
45 | * SLB | |
46 | */ | |
1da177e4 | 47 | |
1f8d419e DG |
48 | #define SLB_NUM_BOLTED 3 |
49 | #define SLB_CACHE_ENTRIES 8 | |
50 | ||
51 | /* Bits in the SLB ESID word */ | |
52 | #define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */ | |
53 | ||
54 | /* Bits in the SLB VSID word */ | |
55 | #define SLB_VSID_SHIFT 12 | |
3c726f8d BH |
56 | #define SLB_VSID_B ASM_CONST(0xc000000000000000) |
57 | #define SLB_VSID_B_256M ASM_CONST(0x0000000000000000) | |
58 | #define SLB_VSID_B_1T ASM_CONST(0x4000000000000000) | |
1f8d419e DG |
59 | #define SLB_VSID_KS ASM_CONST(0x0000000000000800) |
60 | #define SLB_VSID_KP ASM_CONST(0x0000000000000400) | |
61 | #define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */ | |
3c726f8d | 62 | #define SLB_VSID_L ASM_CONST(0x0000000000000100) |
1f8d419e | 63 | #define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */ |
3c726f8d BH |
64 | #define SLB_VSID_LP ASM_CONST(0x0000000000000030) |
65 | #define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000) | |
66 | #define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010) | |
67 | #define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020) | |
68 | #define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030) | |
69 | #define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP) | |
70 | ||
14b34661 DG |
71 | #define SLB_VSID_KERNEL (SLB_VSID_KP) |
72 | #define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C) | |
73 | ||
74 | #define SLBIE_C (0x08000000) | |
1f8d419e DG |
75 | |
76 | /* | |
77 | * Hash table | |
78 | */ | |
1da177e4 LT |
79 | |
80 | #define HPTES_PER_GROUP 8 | |
81 | ||
96e28449 DG |
82 | #define HPTE_V_AVPN_SHIFT 7 |
83 | #define HPTE_V_AVPN ASM_CONST(0xffffffffffffff80) | |
84 | #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT) | |
3c726f8d | 85 | #define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & HPTE_V_AVPN)) |
96e28449 DG |
86 | #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010) |
87 | #define HPTE_V_LOCK ASM_CONST(0x0000000000000008) | |
88 | #define HPTE_V_LARGE ASM_CONST(0x0000000000000004) | |
89 | #define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002) | |
90 | #define HPTE_V_VALID ASM_CONST(0x0000000000000001) | |
91 | ||
92 | #define HPTE_R_PP0 ASM_CONST(0x8000000000000000) | |
93 | #define HPTE_R_TS ASM_CONST(0x4000000000000000) | |
94 | #define HPTE_R_RPN_SHIFT 12 | |
95 | #define HPTE_R_RPN ASM_CONST(0x3ffffffffffff000) | |
96 | #define HPTE_R_FLAGS ASM_CONST(0x00000000000003ff) | |
97 | #define HPTE_R_PP ASM_CONST(0x0000000000000003) | |
3c726f8d | 98 | #define HPTE_R_N ASM_CONST(0x0000000000000004) |
96e28449 | 99 | |
1f8d419e DG |
100 | /* Values for PP (assumes Ks=0, Kp=1) */ |
101 | /* pp0 will always be 0 for linux */ | |
102 | #define PP_RWXX 0 /* Supervisor read/write, User none */ | |
103 | #define PP_RWRX 1 /* Supervisor read/write, User read */ | |
104 | #define PP_RWRW 2 /* Supervisor read/write, User read/write */ | |
105 | #define PP_RXRX 3 /* Supervisor read, User read */ | |
106 | ||
107 | #ifndef __ASSEMBLY__ | |
108 | ||
1da177e4 | 109 | typedef struct { |
96e28449 DG |
110 | unsigned long v; |
111 | unsigned long r; | |
112 | } hpte_t; | |
1da177e4 | 113 | |
96e28449 DG |
114 | extern hpte_t *htab_address; |
115 | extern unsigned long htab_hash_mask; | |
1da177e4 | 116 | |
3c726f8d BH |
117 | /* |
118 | * Page size definition | |
119 | * | |
120 | * shift : is the "PAGE_SHIFT" value for that page size | |
121 | * sllp : is a bit mask with the value of SLB L || LP to be or'ed | |
122 | * directly to a slbmte "vsid" value | |
123 | * penc : is the HPTE encoding mask for the "LP" field: | |
124 | * | |
125 | */ | |
126 | struct mmu_psize_def | |
1da177e4 | 127 | { |
3c726f8d BH |
128 | unsigned int shift; /* number of bits */ |
129 | unsigned int penc; /* HPTE encoding */ | |
130 | unsigned int tlbiel; /* tlbiel supported for that page size */ | |
131 | unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */ | |
132 | unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */ | |
133 | }; | |
1da177e4 | 134 | |
3c726f8d | 135 | #endif /* __ASSEMBLY__ */ |
1da177e4 | 136 | |
3c726f8d BH |
137 | /* |
138 | * The kernel use the constants below to index in the page sizes array. | |
139 | * The use of fixed constants for this purpose is better for performances | |
140 | * of the low level hash refill handlers. | |
141 | * | |
142 | * A non supported page size has a "shift" field set to 0 | |
143 | * | |
144 | * Any new page size being implemented can get a new entry in here. Whether | |
145 | * the kernel will use it or not is a different matter though. The actual page | |
146 | * size used by hugetlbfs is not defined here and may be made variable | |
147 | */ | |
1da177e4 | 148 | |
3c726f8d BH |
149 | #define MMU_PAGE_4K 0 /* 4K */ |
150 | #define MMU_PAGE_64K 1 /* 64K */ | |
151 | #define MMU_PAGE_64K_AP 2 /* 64K Admixed (in a 4K segment) */ | |
152 | #define MMU_PAGE_1M 3 /* 1M */ | |
153 | #define MMU_PAGE_16M 4 /* 16M */ | |
154 | #define MMU_PAGE_16G 5 /* 16G */ | |
155 | #define MMU_PAGE_COUNT 6 | |
1da177e4 | 156 | |
3c726f8d | 157 | #ifndef __ASSEMBLY__ |
1da177e4 | 158 | |
3c726f8d BH |
159 | /* |
160 | * The current system page sizes | |
161 | */ | |
162 | extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; | |
163 | extern int mmu_linear_psize; | |
164 | extern int mmu_virtual_psize; | |
f4c82d51 | 165 | |
3c726f8d BH |
166 | #ifdef CONFIG_HUGETLB_PAGE |
167 | /* | |
168 | * The page size index of the huge pages for use by hugetlbfs | |
169 | */ | |
170 | extern int mmu_huge_psize; | |
f4c82d51 | 171 | |
3c726f8d | 172 | #endif /* CONFIG_HUGETLB_PAGE */ |
f4c82d51 | 173 | |
3c726f8d BH |
174 | /* |
175 | * This function sets the AVPN and L fields of the HPTE appropriately | |
176 | * for the page size | |
177 | */ | |
178 | static inline unsigned long hpte_encode_v(unsigned long va, int psize) | |
179 | { | |
180 | unsigned long v = | |
181 | v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm); | |
182 | v <<= HPTE_V_AVPN_SHIFT; | |
183 | if (psize != MMU_PAGE_4K) | |
184 | v |= HPTE_V_LARGE; | |
185 | return v; | |
186 | } | |
f4c82d51 | 187 | |
3c726f8d BH |
188 | /* |
189 | * This function sets the ARPN, and LP fields of the HPTE appropriately | |
190 | * for the page size. We assume the pa is already "clean" that is properly | |
191 | * aligned for the requested page size | |
192 | */ | |
193 | static inline unsigned long hpte_encode_r(unsigned long pa, int psize) | |
194 | { | |
195 | unsigned long r; | |
f4c82d51 | 196 | |
3c726f8d BH |
197 | /* A 4K page needs no special encoding */ |
198 | if (psize == MMU_PAGE_4K) | |
199 | return pa & HPTE_R_RPN; | |
200 | else { | |
201 | unsigned int penc = mmu_psize_defs[psize].penc; | |
202 | unsigned int shift = mmu_psize_defs[psize].shift; | |
203 | return (pa & ~((1ul << shift) - 1)) | (penc << 12); | |
f4c82d51 | 204 | } |
3c726f8d | 205 | return r; |
f4c82d51 S |
206 | } |
207 | ||
1da177e4 | 208 | /* |
3c726f8d | 209 | * This hashes a virtual address for a 256Mb segment only for now |
1da177e4 | 210 | */ |
3c726f8d BH |
211 | |
212 | static inline unsigned long hpt_hash(unsigned long va, unsigned int shift) | |
213 | { | |
214 | return ((va >> 28) & 0x7fffffffffUL) ^ ((va & 0x0fffffffUL) >> shift); | |
215 | } | |
216 | ||
217 | extern int __hash_page_4K(unsigned long ea, unsigned long access, | |
218 | unsigned long vsid, pte_t *ptep, unsigned long trap, | |
219 | unsigned int local); | |
220 | extern int __hash_page_64K(unsigned long ea, unsigned long access, | |
221 | unsigned long vsid, pte_t *ptep, unsigned long trap, | |
222 | unsigned int local); | |
223 | struct mm_struct; | |
224 | extern int hash_huge_page(struct mm_struct *mm, unsigned long access, | |
cbf52afd DG |
225 | unsigned long ea, unsigned long vsid, int local, |
226 | unsigned long trap); | |
1da177e4 LT |
227 | |
228 | extern void htab_finish_init(void); | |
3c726f8d BH |
229 | extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, |
230 | unsigned long pstart, unsigned long mode, | |
231 | int psize); | |
1da177e4 | 232 | |
799d6046 PM |
233 | extern void htab_initialize(void); |
234 | extern void htab_initialize_secondary(void); | |
1f8d419e DG |
235 | extern void hpte_init_native(void); |
236 | extern void hpte_init_lpar(void); | |
237 | extern void hpte_init_iSeries(void); | |
49b09853 | 238 | extern void mm_init_ppc64(void); |
1f8d419e DG |
239 | |
240 | extern long pSeries_lpar_hpte_insert(unsigned long hpte_group, | |
241 | unsigned long va, unsigned long prpn, | |
3c726f8d BH |
242 | unsigned long rflags, |
243 | unsigned long vflags, int psize); | |
244 | ||
245 | extern long native_hpte_insert(unsigned long hpte_group, | |
246 | unsigned long va, unsigned long prpn, | |
247 | unsigned long rflags, | |
248 | unsigned long vflags, int psize); | |
1f8d419e | 249 | |
3c726f8d BH |
250 | extern long iSeries_hpte_insert(unsigned long hpte_group, |
251 | unsigned long va, unsigned long prpn, | |
252 | unsigned long rflags, | |
253 | unsigned long vflags, int psize); | |
4c55130b | 254 | |
533f0817 | 255 | extern void stabs_alloc(void); |
3c726f8d | 256 | extern void slb_initialize(void); |
799d6046 | 257 | extern void stab_initialize(unsigned long stab); |
533f0817 | 258 | |
1da177e4 LT |
259 | #endif /* __ASSEMBLY__ */ |
260 | ||
261 | /* | |
1f8d419e DG |
262 | * VSID allocation |
263 | * | |
264 | * We first generate a 36-bit "proto-VSID". For kernel addresses this | |
265 | * is equal to the ESID, for user addresses it is: | |
266 | * (context << 15) | (esid & 0x7fff) | |
267 | * | |
268 | * The two forms are distinguishable because the top bit is 0 for user | |
269 | * addresses, whereas the top two bits are 1 for kernel addresses. | |
270 | * Proto-VSIDs with the top two bits equal to 0b10 are reserved for | |
271 | * now. | |
272 | * | |
273 | * The proto-VSIDs are then scrambled into real VSIDs with the | |
274 | * multiplicative hash: | |
275 | * | |
276 | * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS | |
277 | * where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7 | |
278 | * VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF | |
279 | * | |
280 | * This scramble is only well defined for proto-VSIDs below | |
281 | * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are | |
282 | * reserved. VSID_MULTIPLIER is prime, so in particular it is | |
283 | * co-prime to VSID_MODULUS, making this a 1:1 scrambling function. | |
284 | * Because the modulus is 2^n-1 we can compute it efficiently without | |
285 | * a divide or extra multiply (see below). | |
286 | * | |
287 | * This scheme has several advantages over older methods: | |
288 | * | |
289 | * - We have VSIDs allocated for every kernel address | |
290 | * (i.e. everything above 0xC000000000000000), except the very top | |
291 | * segment, which simplifies several things. | |
292 | * | |
293 | * - We allow for 15 significant bits of ESID and 20 bits of | |
294 | * context for user addresses. i.e. 8T (43 bits) of address space for | |
295 | * up to 1M contexts (although the page table structure and context | |
296 | * allocation will need changes to take advantage of this). | |
297 | * | |
298 | * - The scramble function gives robust scattering in the hash | |
299 | * table (at least based on some initial results). The previous | |
300 | * method was more susceptible to pathological cases giving excessive | |
301 | * hash collisions. | |
302 | */ | |
303 | /* | |
304 | * WARNING - If you change these you must make sure the asm | |
305 | * implementations in slb_allocate (slb_low.S), do_stab_bolted | |
306 | * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly. | |
307 | * | |
308 | * You'll also need to change the precomputed VSID values in head.S | |
309 | * which are used by the iSeries firmware. | |
1da177e4 | 310 | */ |
1da177e4 LT |
311 | |
312 | #define VSID_MULTIPLIER ASM_CONST(200730139) /* 28-bit prime */ | |
313 | #define VSID_BITS 36 | |
314 | #define VSID_MODULUS ((1UL<<VSID_BITS)-1) | |
315 | ||
e28f7faf DG |
316 | #define CONTEXT_BITS 19 |
317 | #define USER_ESID_BITS 16 | |
318 | ||
319 | #define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT)) | |
1da177e4 LT |
320 | |
321 | /* | |
322 | * This macro generates asm code to compute the VSID scramble | |
323 | * function. Used in slb_allocate() and do_stab_bolted. The function | |
324 | * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS | |
325 | * | |
326 | * rt = register continaing the proto-VSID and into which the | |
327 | * VSID will be stored | |
328 | * rx = scratch register (clobbered) | |
329 | * | |
330 | * - rt and rx must be different registers | |
331 | * - The answer will end up in the low 36 bits of rt. The higher | |
332 | * bits may contain other garbage, so you may need to mask the | |
333 | * result. | |
334 | */ | |
335 | #define ASM_VSID_SCRAMBLE(rt, rx) \ | |
336 | lis rx,VSID_MULTIPLIER@h; \ | |
337 | ori rx,rx,VSID_MULTIPLIER@l; \ | |
338 | mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \ | |
339 | \ | |
340 | srdi rx,rt,VSID_BITS; \ | |
341 | clrldi rt,rt,(64-VSID_BITS); \ | |
342 | add rt,rt,rx; /* add high and low bits */ \ | |
343 | /* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \ | |
344 | * 2^36-1+2^28-1. That in particular means that if r3 >= \ | |
345 | * 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \ | |
346 | * the bit clear, r3 already has the answer we want, if it \ | |
347 | * doesn't, the answer is the low 36 bits of r3+1. So in all \ | |
348 | * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\ | |
349 | addi rx,rt,1; \ | |
350 | srdi rx,rx,VSID_BITS; /* extract 2^36 bit */ \ | |
351 | add rt,rt,rx | |
352 | ||
1f8d419e DG |
353 | |
354 | #ifndef __ASSEMBLY__ | |
355 | ||
356 | typedef unsigned long mm_context_id_t; | |
357 | ||
358 | typedef struct { | |
359 | mm_context_id_t id; | |
360 | #ifdef CONFIG_HUGETLB_PAGE | |
c594adad | 361 | u16 low_htlb_areas, high_htlb_areas; |
1f8d419e DG |
362 | #endif |
363 | } mm_context_t; | |
364 | ||
365 | ||
366 | static inline unsigned long vsid_scramble(unsigned long protovsid) | |
367 | { | |
368 | #if 0 | |
369 | /* The code below is equivalent to this function for arguments | |
370 | * < 2^VSID_BITS, which is all this should ever be called | |
371 | * with. However gcc is not clever enough to compute the | |
372 | * modulus (2^n-1) without a second multiply. */ | |
373 | return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS); | |
374 | #else /* 1 */ | |
375 | unsigned long x; | |
376 | ||
377 | x = protovsid * VSID_MULTIPLIER; | |
378 | x = (x >> VSID_BITS) + (x & VSID_MODULUS); | |
379 | return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS; | |
380 | #endif /* 1 */ | |
381 | } | |
382 | ||
383 | /* This is only valid for addresses >= KERNELBASE */ | |
384 | static inline unsigned long get_kernel_vsid(unsigned long ea) | |
385 | { | |
386 | return vsid_scramble(ea >> SID_SHIFT); | |
387 | } | |
388 | ||
389 | /* This is only valid for user addresses (which are below 2^41) */ | |
390 | static inline unsigned long get_vsid(unsigned long context, unsigned long ea) | |
391 | { | |
392 | return vsid_scramble((context << USER_ESID_BITS) | |
393 | | (ea >> SID_SHIFT)); | |
394 | } | |
395 | ||
488f8499 DG |
396 | #define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS) |
397 | #define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea)) | |
398 | ||
d1405b86 BH |
399 | /* Physical address used by some IO functions */ |
400 | typedef unsigned long phys_addr_t; | |
401 | ||
402 | ||
1f8d419e DG |
403 | #endif /* __ASSEMBLY */ |
404 | ||
047ea784 | 405 | #endif /* CONFIG_PPC64 */ |
88ced031 | 406 | #endif /* __KERNEL__ */ |
047ea784 | 407 | #endif /* _ASM_POWERPC_MMU_H_ */ |