[linux-block.git] / include / asm-powerpc / mmu.h

#ifndef _ASM_POWERPC_MMU_H_
#define _ASM_POWERPC_MMU_H_
#ifdef __KERNEL__

#ifndef CONFIG_PPC64
#include <asm-ppc/mmu.h>
#else

/*
 * PowerPC memory management structures
 *
 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
 *   PPC64 rework.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#include <asm/asm-compat.h>
#include <asm/page.h>

/*
 * Segment table
 */

#define STE_ESID_V	0x80
#define STE_ESID_KS	0x20
#define STE_ESID_KP	0x10
#define STE_ESID_N	0x08

#define STE_VSID_SHIFT	12

/* Location of cpu0's segment table */
#define STAB0_PAGE	0x6
#define STAB0_OFFSET	(STAB0_PAGE << 12)
#define STAB0_PHYS_ADDR	(STAB0_OFFSET + PHYSICAL_START)

#ifndef __ASSEMBLY__
extern char initial_stab[];
#endif /* ! __ASSEMBLY */

/*
 * SLB
 */

#define SLB_NUM_BOLTED		3
#define SLB_CACHE_ENTRIES	8

/* Bits in the SLB ESID word */
#define SLB_ESID_V		ASM_CONST(0x0000000008000000) /* valid */

/* Bits in the SLB VSID word */
#define SLB_VSID_SHIFT		12
#define SLB_VSID_B		ASM_CONST(0xc000000000000000)
#define SLB_VSID_B_256M		ASM_CONST(0x0000000000000000)
#define SLB_VSID_B_1T		ASM_CONST(0x4000000000000000)
#define SLB_VSID_KS		ASM_CONST(0x0000000000000800)
#define SLB_VSID_KP		ASM_CONST(0x0000000000000400)
#define SLB_VSID_N		ASM_CONST(0x0000000000000200) /* no-execute */
#define SLB_VSID_L		ASM_CONST(0x0000000000000100)
#define SLB_VSID_C		ASM_CONST(0x0000000000000080) /* class */
#define SLB_VSID_LP		ASM_CONST(0x0000000000000030)
#define SLB_VSID_LP_00		ASM_CONST(0x0000000000000000)
#define SLB_VSID_LP_01		ASM_CONST(0x0000000000000010)
#define SLB_VSID_LP_10		ASM_CONST(0x0000000000000020)
#define SLB_VSID_LP_11		ASM_CONST(0x0000000000000030)
#define SLB_VSID_LLP		(SLB_VSID_L|SLB_VSID_LP)

#define SLB_VSID_KERNEL		(SLB_VSID_KP)
#define SLB_VSID_USER		(SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)

#define SLBIE_C			(0x08000000)

/*
 * Hash table
 */

#define HPTES_PER_GROUP 8

#define HPTE_V_AVPN_SHIFT	7
#define HPTE_V_AVPN		ASM_CONST(0xffffffffffffff80)
#define HPTE_V_AVPN_VAL(x)	(((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
#define HPTE_V_COMPARE(x,y)	(!(((x) ^ (y)) & HPTE_V_AVPN))
#define HPTE_V_BOLTED		ASM_CONST(0x0000000000000010)
#define HPTE_V_LOCK		ASM_CONST(0x0000000000000008)
#define HPTE_V_LARGE		ASM_CONST(0x0000000000000004)
#define HPTE_V_SECONDARY	ASM_CONST(0x0000000000000002)
#define HPTE_V_VALID		ASM_CONST(0x0000000000000001)

#define HPTE_R_PP0		ASM_CONST(0x8000000000000000)
#define HPTE_R_TS		ASM_CONST(0x4000000000000000)
#define HPTE_R_RPN_SHIFT	12
#define HPTE_R_RPN		ASM_CONST(0x3ffffffffffff000)
#define HPTE_R_FLAGS		ASM_CONST(0x00000000000003ff)
#define HPTE_R_PP		ASM_CONST(0x0000000000000003)
#define HPTE_R_N		ASM_CONST(0x0000000000000004)
#define HPTE_R_C		ASM_CONST(0x0000000000000080)
#define HPTE_R_R		ASM_CONST(0x0000000000000100)

/* Values for PP (assumes Ks=0, Kp=1) */
/* pp0 will always be 0 for linux     */
#define PP_RWXX	0	/* Supervisor read/write, User none */
#define PP_RWRX 1	/* Supervisor read/write, User read */
#define PP_RWRW 2	/* Supervisor read/write, User read/write */
#define PP_RXRX 3	/* Supervisor read,       User read */

#ifndef __ASSEMBLY__

typedef struct {
	unsigned long v;
	unsigned long r;
} hpte_t;

extern hpte_t *htab_address;
extern unsigned long htab_size_bytes;
extern unsigned long htab_hash_mask;

/*
 * Page size definition
 *
 *    shift : is the "PAGE_SHIFT" value for that page size
 *    sllp  : is a bit mask with the value of SLB L || LP to be or'ed
 *            directly to a slbmte "vsid" value
 *    penc  : is the HPTE encoding mask for the "LP" field:
 *
 */
struct mmu_psize_def
{
	unsigned int	shift;	/* number of bits */
	unsigned int	penc;	/* HPTE encoding */
	unsigned int	tlbiel;	/* tlbiel supported for that page size */
	unsigned long	avpnm;	/* bits to mask out in AVPN in the HPTE */
	unsigned long	sllp;	/* SLB L||LP (exact mask to use in slbmte) */
};

#endif /* __ASSEMBLY__ */

/*
 * The kernel use the constants below to index in the page sizes array.
 * The use of fixed constants for this purpose is better for performances
 * of the low level hash refill handlers.
 *
 * A non supported page size has a "shift" field set to 0
 *
 * Any new page size being implemented can get a new entry in here. Whether
 * the kernel will use it or not is a different matter though. The actual page
 * size used by hugetlbfs is not defined here and may be made variable
 */

#define MMU_PAGE_4K		0	/* 4K */
#define MMU_PAGE_64K		1	/* 64K */
#define MMU_PAGE_64K_AP		2	/* 64K Admixed (in a 4K segment) */
#define MMU_PAGE_1M		3	/* 1M */
#define MMU_PAGE_16M		4	/* 16M */
#define MMU_PAGE_16G		5	/* 16G */
#define MMU_PAGE_COUNT		6

#ifndef __ASSEMBLY__

/*
 * The current system page sizes
 */
extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
extern int mmu_linear_psize;
extern int mmu_virtual_psize;
extern int mmu_vmalloc_psize;
extern int mmu_io_psize;

/*
 * If the processor supports 64k normal pages but not 64k cache
 * inhibited pages, we have to be prepared to switch processes
 * to use 4k pages when they create cache-inhibited mappings.
 * If this is the case, mmu_ci_restrictions will be set to 1.
 */
extern int mmu_ci_restrictions;

#ifdef CONFIG_HUGETLB_PAGE
/*
 * The page size index of the huge pages for use by hugetlbfs
 */
extern int mmu_huge_psize;

#endif /* CONFIG_HUGETLB_PAGE */

/*
 * This function sets the AVPN and L fields of the HPTE  appropriately
 * for the page size
 */
static inline unsigned long hpte_encode_v(unsigned long va, int psize)
{
	unsigned long v =
	v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
	v <<= HPTE_V_AVPN_SHIFT;
	if (psize != MMU_PAGE_4K)
		v |= HPTE_V_LARGE;
	return v;
}

/*
 * This function sets the ARPN, and LP fields of the HPTE appropriately
 * for the page size. We assume the pa is already "clean" that is properly
 * aligned for the requested page size
 */
static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
{
	unsigned long r;

	/* A 4K page needs no special encoding */
	if (psize == MMU_PAGE_4K)
		return pa & HPTE_R_RPN;
	else {
		unsigned int penc = mmu_psize_defs[psize].penc;
		unsigned int shift = mmu_psize_defs[psize].shift;
		return (pa & ~((1ul << shift) - 1)) | (penc << 12);
	}
	return r;
}

/*
 * This hashes a virtual address for a 256Mb segment only for now
 */

static inline unsigned long hpt_hash(unsigned long va, unsigned int shift)
{
	return ((va >> 28) & 0x7fffffffffUL) ^ ((va & 0x0fffffffUL) >> shift);
}

extern int __hash_page_4K(unsigned long ea, unsigned long access,
			  unsigned long vsid, pte_t *ptep, unsigned long trap,
			  unsigned int local);
extern int __hash_page_64K(unsigned long ea, unsigned long access,
			   unsigned long vsid, pte_t *ptep, unsigned long trap,
			   unsigned int local);
struct mm_struct;
extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
			  unsigned long ea, unsigned long vsid, int local,
			  unsigned long trap);

extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
			     unsigned long pstart, unsigned long mode,
			     int psize);

extern void htab_initialize(void);
extern void htab_initialize_secondary(void);
extern void hpte_init_native(void);
extern void hpte_init_lpar(void);
extern void hpte_init_iSeries(void);

extern long pSeries_lpar_hpte_insert(unsigned long hpte_group,
				     unsigned long va, unsigned long prpn,
				     unsigned long rflags,
				     unsigned long vflags, int psize);

extern long native_hpte_insert(unsigned long hpte_group,
			       unsigned long va, unsigned long prpn,
			       unsigned long rflags,
			       unsigned long vflags, int psize);

extern long iSeries_hpte_insert(unsigned long hpte_group,
				unsigned long va, unsigned long prpn,
				unsigned long rflags,
				unsigned long vflags, int psize);

extern void stabs_alloc(void);
extern void slb_initialize(void);
extern void slb_flush_and_rebolt(void);
extern void stab_initialize(unsigned long stab);

#endif /* __ASSEMBLY__ */

/*
 * VSID allocation
 *
 * We first generate a 36-bit "proto-VSID".  For kernel addresses this
 * is equal to the ESID, for user addresses it is:
 *	(context << 15) | (esid & 0x7fff)
 *
 * The two forms are distinguishable because the top bit is 0 for user
 * addresses, whereas the top two bits are 1 for kernel addresses.
 * Proto-VSIDs with the top two bits equal to 0b10 are reserved for
 * now.
 *
 * The proto-VSIDs are then scrambled into real VSIDs with the
 * multiplicative hash:
 *
 *	VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
 *	where	VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
 *		VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
 *
 * This scramble is only well defined for proto-VSIDs below
 * 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
 * reserved.  VSID_MULTIPLIER is prime, so in particular it is
 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
 * Because the modulus is 2^n-1 we can compute it efficiently without
 * a divide or extra multiply (see below).
 *
 * This scheme has several advantages over older methods:
 *
 * 	- We have VSIDs allocated for every kernel address
 * (i.e. everything above 0xC000000000000000), except the very top
 * segment, which simplifies several things.
 *
 * 	- We allow for 15 significant bits of ESID and 20 bits of
 * context for user addresses.  i.e. 8T (43 bits) of address space for
 * up to 1M contexts (although the page table structure and context
 * allocation will need changes to take advantage of this).
 *
 * 	- The scramble function gives robust scattering in the hash
 * table (at least based on some initial results).  The previous
 * method was more susceptible to pathological cases giving excessive
 * hash collisions.
 */
/*
 * WARNING - If you change these you must make sure the asm
 * implementations in slb_allocate (slb_low.S), do_stab_bolted
 * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
 *
 * You'll also need to change the precomputed VSID values in head.S
 * which are used by the iSeries firmware.
 */

#define VSID_MULTIPLIER	ASM_CONST(200730139)	/* 28-bit prime */
#define VSID_BITS	36
#define VSID_MODULUS	((1UL<<VSID_BITS)-1)

#define CONTEXT_BITS	19
#define USER_ESID_BITS	16

#define USER_VSID_RANGE	(1UL << (USER_ESID_BITS + SID_SHIFT))

/*
 * This macro generates asm code to compute the VSID scramble
 * function.  Used in slb_allocate() and do_stab_bolted.  The function
 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
 *
 *	rt = register continaing the proto-VSID and into which the
 *		VSID will be stored
 *	rx = scratch register (clobbered)
 *
 * 	- rt and rx must be different registers
 * 	- The answer will end up in the low 36 bits of rt.  The higher
 * 	  bits may contain other garbage, so you may need to mask the
 * 	  result.
 */
#define ASM_VSID_SCRAMBLE(rt, rx)	\
	lis	rx,VSID_MULTIPLIER@h;					\
	ori	rx,rx,VSID_MULTIPLIER@l;				\
	mulld	rt,rt,rx;		/* rt = rt * MULTIPLIER */	\
									\
	srdi	rx,rt,VSID_BITS;					\
	clrldi	rt,rt,(64-VSID_BITS);					\
	add	rt,rt,rx;		/* add high and low bits */	\
	/* Now, r3 == VSID (mod 2^36-1), and lies between 0 and		\
	 * 2^36-1+2^28-1.  That in particular means that if r3 >=	\
	 * 2^36-1, then r3+1 has the 2^36 bit set.  So, if r3+1 has	\
	 * the bit clear, r3 already has the answer we want, if it	\
	 * doesn't, the answer is the low 36 bits of r3+1.  So in all	\
	 * cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
	addi	rx,rt,1;						\
	srdi	rx,rx,VSID_BITS;	/* extract 2^36 bit */		\
	add	rt,rt,rx


#ifndef __ASSEMBLY__

typedef unsigned long mm_context_id_t;

typedef struct {
	mm_context_id_t id;
	u16 user_psize;			/* page size index */
	u16 sllp;			/* SLB entry page size encoding */
#ifdef CONFIG_HUGETLB_PAGE
	u16 low_htlb_areas, high_htlb_areas;
#endif
	unsigned long vdso_base;
} mm_context_t;


static inline unsigned long vsid_scramble(unsigned long protovsid)
{
#if 0
	/* The code below is equivalent to this function for arguments
	 * < 2^VSID_BITS, which is all this should ever be called
	 * with.  However gcc is not clever enough to compute the
	 * modulus (2^n-1) without a second multiply. */
	return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS);
#else /* 1 */
	unsigned long x;

	x = protovsid * VSID_MULTIPLIER;
	x = (x >> VSID_BITS) + (x & VSID_MODULUS);
	return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS;
#endif /* 1 */
}

/* This is only valid for addresses >= KERNELBASE */
static inline unsigned long get_kernel_vsid(unsigned long ea)
{
	return vsid_scramble(ea >> SID_SHIFT);
}

/* This is only valid for user addresses (which are below 2^41) */
static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
{
	return vsid_scramble((context << USER_ESID_BITS)
			     | (ea >> SID_SHIFT));
}

#define VSID_SCRAMBLE(pvsid)	(((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS)
#define KERNEL_VSID(ea)		VSID_SCRAMBLE(GET_ESID(ea))

/* Physical address used by some IO functions */
typedef unsigned long phys_addr_t;


#endif /* __ASSEMBLY */

#endif /* CONFIG_PPC64 */
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_MMU_H_ */
Commit	Line	Data
047ea784 PM	1	#ifndef _ASM_POWERPC_MMU_H_
047ea784 PM	2	#define _ASM_POWERPC_MMU_H_
88ced031	3	#ifdef __KERNEL__
047ea784 PM	4
	5	#ifndef CONFIG_PPC64
	6	#include <asm-ppc/mmu.h>
	7	#else
	8
1da177e4 LT	9	/*
	10	* PowerPC memory management structures
	11	*
	12	* Dave Engebretsen & Mike Corrigan <{engebret\|mikejc}@us.ibm.com>
	13	* PPC64 rework.
	14	*
	15	* This program is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License
	17	* as published by the Free Software Foundation; either version
	18	* 2 of the License, or (at your option) any later version.
	19	*/
	20
3ddfbcf1	21	#include <asm/asm-compat.h>
1da177e4	22	#include <asm/page.h>
1da177e4	23
1f8d419e DG	24	/*
	25	* Segment table
	26	*/
1da177e4 LT	27
	28	#define STE_ESID_V 0x80
	29	#define STE_ESID_KS 0x20
	30	#define STE_ESID_KP 0x10
	31	#define STE_ESID_N 0x08
	32
	33	#define STE_VSID_SHIFT 12
	34
1f8d419e	35	/* Location of cpu0's segment table */
c59c464a	36	#define STAB0_PAGE 0x6
758438a7 ME	37	#define STAB0_OFFSET (STAB0_PAGE << 12)
758438a7 ME	38	#define STAB0_PHYS_ADDR (STAB0_OFFSET + PHYSICAL_START)
c59c464a DG	39
	40	#ifndef __ASSEMBLY__
	41	extern char initial_stab[];
	42	#endif /* ! __ASSEMBLY */
1f8d419e DG	43
	44	/*
	45	* SLB
	46	*/
1da177e4	47
1f8d419e DG	48	#define SLB_NUM_BOLTED 3
	49	#define SLB_CACHE_ENTRIES 8
	50
	51	/* Bits in the SLB ESID word */
	52	#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
	53
	54	/* Bits in the SLB VSID word */
	55	#define SLB_VSID_SHIFT 12
3c726f8d BH	56	#define SLB_VSID_B ASM_CONST(0xc000000000000000)
	57	#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
	58	#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
1f8d419e DG	59	#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
	60	#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
	61	#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
3c726f8d	62	#define SLB_VSID_L ASM_CONST(0x0000000000000100)
1f8d419e	63	#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
3c726f8d BH	64	#define SLB_VSID_LP ASM_CONST(0x0000000000000030)
	65	#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
	66	#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
	67	#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
	68	#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
	69	#define SLB_VSID_LLP (SLB_VSID_L\|SLB_VSID_LP)
	70
14b34661 DG	71	#define SLB_VSID_KERNEL (SLB_VSID_KP)
	72	#define SLB_VSID_USER (SLB_VSID_KP\|SLB_VSID_KS\|SLB_VSID_C)
	73
	74	#define SLBIE_C (0x08000000)
1f8d419e DG	75
	76	/*
	77	* Hash table
	78	*/
1da177e4 LT	79
	80	#define HPTES_PER_GROUP 8
	81
96e28449 DG	82	#define HPTE_V_AVPN_SHIFT 7
	83	#define HPTE_V_AVPN ASM_CONST(0xffffffffffffff80)
	84	#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
3c726f8d	85	#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & HPTE_V_AVPN))
96e28449 DG	86	#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
	87	#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
	88	#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
	89	#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
	90	#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
	91
	92	#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
	93	#define HPTE_R_TS ASM_CONST(0x4000000000000000)
	94	#define HPTE_R_RPN_SHIFT 12
	95	#define HPTE_R_RPN ASM_CONST(0x3ffffffffffff000)
	96	#define HPTE_R_FLAGS ASM_CONST(0x00000000000003ff)
	97	#define HPTE_R_PP ASM_CONST(0x0000000000000003)
3c726f8d	98	#define HPTE_R_N ASM_CONST(0x0000000000000004)
c5cf0e30 BH	99	#define HPTE_R_C ASM_CONST(0x0000000000000080)
c5cf0e30 BH	100	#define HPTE_R_R ASM_CONST(0x0000000000000100)
96e28449	101
1f8d419e DG	102	/* Values for PP (assumes Ks=0, Kp=1) */
	103	/* pp0 will always be 0 for linux */
	104	#define PP_RWXX 0 /* Supervisor read/write, User none */
	105	#define PP_RWRX 1 /* Supervisor read/write, User read */
	106	#define PP_RWRW 2 /* Supervisor read/write, User read/write */
	107	#define PP_RXRX 3 /* Supervisor read, User read */
	108
	109	#ifndef __ASSEMBLY__
	110
1da177e4	111	typedef struct {
96e28449 DG	112	unsigned long v;
	113	unsigned long r;
	114	} hpte_t;
1da177e4	115
96e28449	116	extern hpte_t *htab_address;
337a7128	117	extern unsigned long htab_size_bytes;
96e28449	118	extern unsigned long htab_hash_mask;
1da177e4	119
3c726f8d BH	120	/*
	121	* Page size definition
	122	*
	123	* shift : is the "PAGE_SHIFT" value for that page size
	124	* sllp : is a bit mask with the value of SLB L \|\| LP to be or'ed
	125	* directly to a slbmte "vsid" value
	126	* penc : is the HPTE encoding mask for the "LP" field:
	127	*
	128	*/
	129	struct mmu_psize_def
1da177e4	130	{
3c726f8d BH	131	unsigned int shift; /* number of bits */
	132	unsigned int penc; /* HPTE encoding */
	133	unsigned int tlbiel; /* tlbiel supported for that page size */
	134	unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
	135	unsigned long sllp; /* SLB L\|\|LP (exact mask to use in slbmte) */
	136	};
1da177e4	137
3c726f8d	138	#endif /* __ASSEMBLY__ */
1da177e4	139
3c726f8d BH	140	/*
	141	* The kernel use the constants below to index in the page sizes array.
	142	* The use of fixed constants for this purpose is better for performances
	143	* of the low level hash refill handlers.
	144	*
	145	* A non supported page size has a "shift" field set to 0
	146	*
	147	* Any new page size being implemented can get a new entry in here. Whether
	148	* the kernel will use it or not is a different matter though. The actual page
	149	* size used by hugetlbfs is not defined here and may be made variable
	150	*/
1da177e4	151
3c726f8d BH	152	#define MMU_PAGE_4K 0 /* 4K */
	153	#define MMU_PAGE_64K 1 /* 64K */
	154	#define MMU_PAGE_64K_AP 2 /* 64K Admixed (in a 4K segment) */
	155	#define MMU_PAGE_1M 3 /* 1M */
	156	#define MMU_PAGE_16M 4 /* 16M */
	157	#define MMU_PAGE_16G 5 /* 16G */
	158	#define MMU_PAGE_COUNT 6
1da177e4	159
3c726f8d	160	#ifndef __ASSEMBLY__
1da177e4	161
3c726f8d BH	162	/*
	163	* The current system page sizes
	164	*/
	165	extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
	166	extern int mmu_linear_psize;
	167	extern int mmu_virtual_psize;
bf72aeba PM	168	extern int mmu_vmalloc_psize;
	169	extern int mmu_io_psize;
	170
	171	/*
	172	* If the processor supports 64k normal pages but not 64k cache
	173	* inhibited pages, we have to be prepared to switch processes
	174	* to use 4k pages when they create cache-inhibited mappings.
	175	* If this is the case, mmu_ci_restrictions will be set to 1.
	176	*/
	177	extern int mmu_ci_restrictions;
f4c82d51	178
3c726f8d BH	179	#ifdef CONFIG_HUGETLB_PAGE
	180	/*
	181	* The page size index of the huge pages for use by hugetlbfs
	182	*/
	183	extern int mmu_huge_psize;
f4c82d51	184
3c726f8d	185	#endif /* CONFIG_HUGETLB_PAGE */
f4c82d51	186
3c726f8d BH	187	/*
	188	* This function sets the AVPN and L fields of the HPTE appropriately
	189	* for the page size
	190	*/
	191	static inline unsigned long hpte_encode_v(unsigned long va, int psize)
	192	{
	193	unsigned long v =
	194	v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
	195	v <<= HPTE_V_AVPN_SHIFT;
	196	if (psize != MMU_PAGE_4K)
	197	v \|= HPTE_V_LARGE;
	198	return v;
	199	}
f4c82d51	200
3c726f8d BH	201	/*
	202	* This function sets the ARPN, and LP fields of the HPTE appropriately
	203	* for the page size. We assume the pa is already "clean" that is properly
	204	* aligned for the requested page size
	205	*/
	206	static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
	207	{
	208	unsigned long r;
f4c82d51	209
3c726f8d BH	210	/* A 4K page needs no special encoding */
	211	if (psize == MMU_PAGE_4K)
	212	return pa & HPTE_R_RPN;
	213	else {
	214	unsigned int penc = mmu_psize_defs[psize].penc;
	215	unsigned int shift = mmu_psize_defs[psize].shift;
	216	return (pa & ~((1ul << shift) - 1)) \| (penc << 12);
f4c82d51	217	}
3c726f8d	218	return r;
f4c82d51 S	219	}
f4c82d51 S	220
1da177e4	221	/*
3c726f8d	222	* This hashes a virtual address for a 256Mb segment only for now
1da177e4	223	*/
3c726f8d BH	224
	225	static inline unsigned long hpt_hash(unsigned long va, unsigned int shift)
	226	{
	227	return ((va >> 28) & 0x7fffffffffUL) ^ ((va & 0x0fffffffUL) >> shift);
	228	}
	229
	230	extern int __hash_page_4K(unsigned long ea, unsigned long access,
	231	unsigned long vsid, pte_t *ptep, unsigned long trap,
	232	unsigned int local);
	233	extern int __hash_page_64K(unsigned long ea, unsigned long access,
	234	unsigned long vsid, pte_t *ptep, unsigned long trap,
	235	unsigned int local);
	236	struct mm_struct;
	237	extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
cbf52afd DG	238	unsigned long ea, unsigned long vsid, int local,
cbf52afd DG	239	unsigned long trap);
1da177e4	240
3c726f8d BH	241	extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
	242	unsigned long pstart, unsigned long mode,
	243	int psize);
1da177e4	244
799d6046 PM	245	extern void htab_initialize(void);
799d6046 PM	246	extern void htab_initialize_secondary(void);
1f8d419e DG	247	extern void hpte_init_native(void);
	248	extern void hpte_init_lpar(void);
	249	extern void hpte_init_iSeries(void);
	250
	251	extern long pSeries_lpar_hpte_insert(unsigned long hpte_group,
	252	unsigned long va, unsigned long prpn,
3c726f8d BH	253	unsigned long rflags,
	254	unsigned long vflags, int psize);
	255
	256	extern long native_hpte_insert(unsigned long hpte_group,
	257	unsigned long va, unsigned long prpn,
	258	unsigned long rflags,
	259	unsigned long vflags, int psize);
1f8d419e	260
3c726f8d BH	261	extern long iSeries_hpte_insert(unsigned long hpte_group,
	262	unsigned long va, unsigned long prpn,
	263	unsigned long rflags,
	264	unsigned long vflags, int psize);
4c55130b	265
533f0817	266	extern void stabs_alloc(void);
3c726f8d	267	extern void slb_initialize(void);
bf72aeba	268	extern void slb_flush_and_rebolt(void);
799d6046	269	extern void stab_initialize(unsigned long stab);
533f0817	270
1da177e4 LT	271	#endif /* __ASSEMBLY__ */
	272
	273	/*
1f8d419e DG	274	* VSID allocation
	275	*
	276	* We first generate a 36-bit "proto-VSID". For kernel addresses this
	277	* is equal to the ESID, for user addresses it is:
	278	* (context << 15) \| (esid & 0x7fff)
	279	*
	280	* The two forms are distinguishable because the top bit is 0 for user
	281	* addresses, whereas the top two bits are 1 for kernel addresses.
	282	* Proto-VSIDs with the top two bits equal to 0b10 are reserved for
	283	* now.
	284	*
	285	* The proto-VSIDs are then scrambled into real VSIDs with the
	286	* multiplicative hash:
	287	*
	288	* VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
	289	* where VSID_MULTIPLIER = 268435399 = 0xFFFFFC7
	290	* VSID_MODULUS = 2^36-1 = 0xFFFFFFFFF
	291	*
	292	* This scramble is only well defined for proto-VSIDs below
	293	* 0xFFFFFFFFF, so both proto-VSID and actual VSID 0xFFFFFFFFF are
	294	* reserved. VSID_MULTIPLIER is prime, so in particular it is
	295	* co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
	296	* Because the modulus is 2^n-1 we can compute it efficiently without
	297	* a divide or extra multiply (see below).
	298	*
	299	* This scheme has several advantages over older methods:
	300	*
	301	* - We have VSIDs allocated for every kernel address
	302	* (i.e. everything above 0xC000000000000000), except the very top
	303	* segment, which simplifies several things.
	304	*
	305	* - We allow for 15 significant bits of ESID and 20 bits of
	306	* context for user addresses. i.e. 8T (43 bits) of address space for
	307	* up to 1M contexts (although the page table structure and context
	308	* allocation will need changes to take advantage of this).
	309	*
	310	* - The scramble function gives robust scattering in the hash
	311	* table (at least based on some initial results). The previous
	312	* method was more susceptible to pathological cases giving excessive
	313	* hash collisions.
	314	*/
	315	/*
	316	* WARNING - If you change these you must make sure the asm
	317	* implementations in slb_allocate (slb_low.S), do_stab_bolted
	318	* (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
	319	*
	320	* You'll also need to change the precomputed VSID values in head.S
	321	* which are used by the iSeries firmware.
1da177e4	322	*/
1da177e4 LT	323
	324	#define VSID_MULTIPLIER ASM_CONST(200730139) /* 28-bit prime */
	325	#define VSID_BITS 36
	326	#define VSID_MODULUS ((1UL<<VSID_BITS)-1)
	327
e28f7faf DG	328	#define CONTEXT_BITS 19
	329	#define USER_ESID_BITS 16
	330
	331	#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
1da177e4 LT	332
	333	/*
	334	* This macro generates asm code to compute the VSID scramble
	335	* function. Used in slb_allocate() and do_stab_bolted. The function
	336	* computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS
	337	*
	338	* rt = register continaing the proto-VSID and into which the
	339	* VSID will be stored
	340	* rx = scratch register (clobbered)
	341	*
	342	* - rt and rx must be different registers
	343	* - The answer will end up in the low 36 bits of rt. The higher
	344	* bits may contain other garbage, so you may need to mask the
	345	* result.
	346	*/
	347	#define ASM_VSID_SCRAMBLE(rt, rx) \
	348	lis rx,VSID_MULTIPLIER@h; \
	349	ori rx,rx,VSID_MULTIPLIER@l; \
	350	mulld rt,rt,rx; /* rt = rt * MULTIPLIER */ \
	351	\
	352	srdi rx,rt,VSID_BITS; \
	353	clrldi rt,rt,(64-VSID_BITS); \
	354	add rt,rt,rx; /* add high and low bits */ \
	355	/* Now, r3 == VSID (mod 2^36-1), and lies between 0 and \
	356	* 2^36-1+2^28-1. That in particular means that if r3 >= \
	357	* 2^36-1, then r3+1 has the 2^36 bit set. So, if r3+1 has \
	358	* the bit clear, r3 already has the answer we want, if it \
	359	* doesn't, the answer is the low 36 bits of r3+1. So in all \
	360	* cases the answer is the low 36 bits of (r3 + ((r3+1) >> 36))*/\
	361	addi rx,rt,1; \
	362	srdi rx,rx,VSID_BITS; /* extract 2^36 bit */ \
	363	add rt,rt,rx
	364
1f8d419e DG	365
	366	#ifndef __ASSEMBLY__
	367
	368	typedef unsigned long mm_context_id_t;
	369
	370	typedef struct {
	371	mm_context_id_t id;
bf72aeba PM	372	u16 user_psize; /* page size index */
bf72aeba PM	373	u16 sllp; /* SLB entry page size encoding */
1f8d419e	374	#ifdef CONFIG_HUGETLB_PAGE
c594adad	375	u16 low_htlb_areas, high_htlb_areas;
1f8d419e	376	#endif
a5bba930	377	unsigned long vdso_base;
1f8d419e DG	378	} mm_context_t;
	379
	380
	381	static inline unsigned long vsid_scramble(unsigned long protovsid)
	382	{
	383	#if 0
	384	/* The code below is equivalent to this function for arguments
	385	* < 2^VSID_BITS, which is all this should ever be called
	386	* with. However gcc is not clever enough to compute the
	387	* modulus (2^n-1) without a second multiply. */
	388	return ((protovsid * VSID_MULTIPLIER) % VSID_MODULUS);
	389	#else /* 1 */
	390	unsigned long x;
	391
	392	x = protovsid * VSID_MULTIPLIER;
	393	x = (x >> VSID_BITS) + (x & VSID_MODULUS);
	394	return (x + ((x+1) >> VSID_BITS)) & VSID_MODULUS;
	395	#endif /* 1 */
	396	}
	397
	398	/* This is only valid for addresses >= KERNELBASE */
	399	static inline unsigned long get_kernel_vsid(unsigned long ea)
	400	{
	401	return vsid_scramble(ea >> SID_SHIFT);
	402	}
	403
	404	/* This is only valid for user addresses (which are below 2^41) */
	405	static inline unsigned long get_vsid(unsigned long context, unsigned long ea)
	406	{
	407	return vsid_scramble((context << USER_ESID_BITS)
	408	\| (ea >> SID_SHIFT));
	409	}
	410
488f8499 DG	411	#define VSID_SCRAMBLE(pvsid) (((pvsid) * VSID_MULTIPLIER) % VSID_MODULUS)
	412	#define KERNEL_VSID(ea) VSID_SCRAMBLE(GET_ESID(ea))
	413
d1405b86 BH	414	/* Physical address used by some IO functions */
	415	typedef unsigned long phys_addr_t;
	416
	417
1f8d419e DG	418	#endif /* __ASSEMBLY */
1f8d419e DG	419
047ea784	420	#endif /* CONFIG_PPC64 */
88ced031	421	#endif /* __KERNEL__ */
047ea784	422	#endif /* _ASM_POWERPC_MMU_H_ */