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[PATCH] powerpc: Merge vdso's and add vdso support to 32 bits kernel
[linux-2.6-block.git] / include / asm-powerpc / elf.h
CommitLineData
a99eb2ef
BB		 1#ifndef _ASM_POWERPC_ELF_H
2#define _ASM_POWERPC_ELF_H
1da177e4 3
8c65b4a6 4#include <linux/sched.h> /* for task_struct */
1da177e4
LT		 5#include <asm/types.h>
6#include <asm/ptrace.h>
7#include <asm/cputable.h>
36d57ac4 8#include <asm/auxvec.h>
637a6ff6 9#include <asm/page.h>
8c65b4a6 10#include <asm/string.h>
1da177e4
LT		 11
12/* PowerPC relocations defined by the ABIs */
13#define R_PPC_NONE 0
14#define R_PPC_ADDR32 1 /* 32bit absolute address */
15#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
16#define R_PPC_ADDR16 3 /* 16bit absolute address */
17#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
18#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
19#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
20#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
21#define R_PPC_ADDR14_BRTAKEN 8
22#define R_PPC_ADDR14_BRNTAKEN 9
23#define R_PPC_REL24 10 /* PC relative 26 bit */
24#define R_PPC_REL14 11 /* PC relative 16 bit */
25#define R_PPC_REL14_BRTAKEN 12
26#define R_PPC_REL14_BRNTAKEN 13
27#define R_PPC_GOT16 14
28#define R_PPC_GOT16_LO 15
29#define R_PPC_GOT16_HI 16
30#define R_PPC_GOT16_HA 17
31#define R_PPC_PLTREL24 18
32#define R_PPC_COPY 19
33#define R_PPC_GLOB_DAT 20
34#define R_PPC_JMP_SLOT 21
35#define R_PPC_RELATIVE 22
36#define R_PPC_LOCAL24PC 23
37#define R_PPC_UADDR32 24
38#define R_PPC_UADDR16 25
39#define R_PPC_REL32 26
40#define R_PPC_PLT32 27
41#define R_PPC_PLTREL32 28
42#define R_PPC_PLT16_LO 29
43#define R_PPC_PLT16_HI 30
44#define R_PPC_PLT16_HA 31
45#define R_PPC_SDAREL16 32
46#define R_PPC_SECTOFF 33
47#define R_PPC_SECTOFF_LO 34
48#define R_PPC_SECTOFF_HI 35
49#define R_PPC_SECTOFF_HA 36
50
51/* PowerPC relocations defined for the TLS access ABI. */
52#define R_PPC_TLS 67 /* none (sym+add)@tls */
53#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */
54#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */
55#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
56#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
57#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
58#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */
59#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */
60#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
61#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
62#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
63#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */
64#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
65#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
66#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
67#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
68#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
69#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
70#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
71#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
72#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */
73#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */
74#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
75#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
76#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */
77#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */
78#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */
79#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */
80
a99eb2ef 81/* keep this the last entry. */
1da177e4
LT		 82#define R_PPC_NUM 95
83
84/*
85 * ELF register definitions..
86 *
87 * This program is free software; you can redistribute it and/or
88 * modify it under the terms of the GNU General Public License
89 * as published by the Free Software Foundation; either version
90 * 2 of the License, or (at your option) any later version.
91 */
92#include <asm/ptrace.h>
93
94#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
95#define ELF_NFPREG 33 /* includes fpscr */
1da177e4
LT		 96
97typedef unsigned long elf_greg_t64;
98typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
99
100typedef unsigned int elf_greg_t32;
101typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
102
103/*
a99eb2ef 104 * ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
1da177e4 105 */
a99eb2ef
BB		 106#ifdef __powerpc64__
107# define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
108# define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
109# define ELF_GREG_TYPE elf_greg_t64
110#else
111# define ELF_NEVRREG 34 /* includes acc (as 2) */
112# define ELF_NVRREG 33 /* includes vscr */
113# define ELF_GREG_TYPE elf_greg_t32
114# define ELF_ARCH EM_PPC
115# define ELF_CLASS ELFCLASS32
116# define ELF_DATA ELFDATA2MSB
117#endif /* __powerpc64__ */
118
1da177e4
LT		 119#ifndef ELF_ARCH
120# define ELF_ARCH EM_PPC64
121# define ELF_CLASS ELFCLASS64
122# define ELF_DATA ELFDATA2MSB
123 typedef elf_greg_t64 elf_greg_t;
124 typedef elf_gregset_t64 elf_gregset_t;
125# define elf_addr_t unsigned long
126#else
127 /* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
128 typedef elf_greg_t32 elf_greg_t;
129 typedef elf_gregset_t32 elf_gregset_t;
130# define elf_addr_t u32
a99eb2ef 131#endif /* ELF_ARCH */
1da177e4 132
a99eb2ef 133/* Floating point registers */
1da177e4
LT		 134typedef double elf_fpreg_t;
135typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
136
137/* Altivec registers */
138/*
139 * The entries with indexes 0-31 contain the corresponding vector registers.
140 * The entry with index 32 contains the vscr as the last word (offset 12)
141 * within the quadword. This allows the vscr to be stored as either a
142 * quadword (since it must be copied via a vector register to/from storage)
a99eb2ef
BB		 143 * or as a word.
144 *
145 * 64-bit kernel notes: The entry at index 33 contains the vrsave as the first
1da177e4
LT		 146 * word (offset 0) within the quadword.
147 *
148 * This definition of the VMX state is compatible with the current PPC32
149 * ptrace interface. This allows signal handling and ptrace to use the same
150 * structures. This also simplifies the implementation of a bi-arch
151 * (combined (32- and 64-bit) gdb.
152 *
153 * Note that it's _not_ compatible with 32 bits ucontext which stuffs the
154 * vrsave along with vscr and so only uses 33 vectors for the register set
155 */
156typedef __vector128 elf_vrreg_t;
157typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
a99eb2ef 158#ifdef __powerpc64__
1da177e4 159typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
a99eb2ef 160#endif
1da177e4
LT		 161
162/*
163 * This is used to ensure we don't load something for the wrong architecture.
164 */
165#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
166
167#define USE_ELF_CORE_DUMP
637a6ff6 168#define ELF_EXEC_PAGESIZE PAGE_SIZE
1da177e4
LT		 169
170/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
171 use of this is to invoke "./ld.so someprog" to test out a new version of
172 the loader. We need to make sure that it is out of the way of the program
173 that it will "exec", and that there is sufficient room for the brk. */
174
175#define ELF_ET_DYN_BASE (0x08000000)
176
177#ifdef __KERNEL__
178
179/* Common routine for both 32-bit and 64-bit processes */
a99eb2ef 180static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs,
1da177e4
LT		 181 struct pt_regs *regs)
182{
30415f6a 183 int i, nregs;
1da177e4 184
30415f6a 185 memset((void *)elf_regs, 0, sizeof(elf_gregset_t));
1da177e4 186
30415f6a
ME		 187 /* Our registers are always unsigned longs, whether we're a 32 bit
188 * process or 64 bit, on either a 64 bit or 32 bit kernel.
189 * Don't use ELF_GREG_TYPE here. */
190 nregs = sizeof(struct pt_regs) / sizeof(unsigned long);
191 if (nregs > ELF_NGREG)
192 nregs = ELF_NGREG;
a99eb2ef 193
30415f6a
ME		 194 for (i = 0; i < nregs; i++) {
195 /* This will correctly truncate 64 bit registers to 32 bits
196 * for a 32 bit process on a 64 bit kernel. */
197 elf_regs[i] = (elf_greg_t)((ELF_GREG_TYPE *)regs)[i];
198 }
1da177e4 199}
a99eb2ef 200#define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs);
1da177e4
LT		 201
202static inline int dump_task_regs(struct task_struct *tsk,
203 elf_gregset_t *elf_regs)
204{
205 struct pt_regs *regs = tsk->thread.regs;
206 if (regs)
a99eb2ef 207 ppc_elf_core_copy_regs(*elf_regs, regs);
1da177e4
LT		 208
209 return 1;
210}
211#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
212
213extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
214#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
215
a99eb2ef 216#endif /* __KERNEL__ */
1da177e4 217
a99eb2ef 218/* ELF_HWCAP yields a mask that user programs can use to figure out what
1da177e4
LT		 219 instruction set this cpu supports. This could be done in userspace,
220 but it's not easy, and we've already done it here. */
a99eb2ef 221# define ELF_HWCAP (cur_cpu_spec->cpu_user_features)
400d2212 222#ifdef __powerpc64__
06d67d54
PM		 223# define ELF_PLAT_INIT(_r, load_addr) do { \
224 _r->gpr[2] = load_addr; \
a99eb2ef 225} while (0)
a99eb2ef 226#endif /* __powerpc64__ */
1da177e4
LT		 227
228/* This yields a string that ld.so will use to load implementation
229 specific libraries for optimization. This is more specific in
230 intent than poking at uname or /proc/cpuinfo.
231
232 For the moment, we have only optimizations for the Intel generations,
233 but that could change... */
234
235#define ELF_PLATFORM (NULL)
236
1da177e4 237#ifdef __KERNEL__
a99eb2ef
BB		 238
239#ifdef __powerpc64__
240# define SET_PERSONALITY(ex, ibcs2) \
1da177e4
LT		 241do { \
242 unsigned long new_flags = 0; \
243 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
244 new_flags = _TIF_32BIT; \
245 if ((current_thread_info()->flags & _TIF_32BIT) \
246 != new_flags) \
247 set_thread_flag(TIF_ABI_PENDING); \
248 else \
249 clear_thread_flag(TIF_ABI_PENDING); \
ce10d979 250 if (personality(current->personality) != PER_LINUX32) \
1da177e4
LT		 251 set_personality(PER_LINUX); \
252} while (0)
1da177e4
LT		 253/*
254 * An executable for which elf_read_implies_exec() returns TRUE will
a2f95a5a
AB		 255 * have the READ_IMPLIES_EXEC personality flag set automatically. This
256 * is only required to work around bugs in old 32bit toolchains. Since
257 * the 64bit ABI has never had these issues dont enable the workaround
258 * even if we have an executable stack.
1da177e4 259 */
a99eb2ef 260# define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
a2f95a5a 261 (exec_stk != EXSTACK_DISABLE_X) : 0)
a99eb2ef
BB		 262#else
263# define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
264#endif /* __powerpc64__ */
1da177e4 265
a99eb2ef 266#endif /* __KERNEL__ */
1da177e4 267
1da177e4
LT		 268extern int dcache_bsize;
269extern int icache_bsize;
270extern int ucache_bsize;
271
a7f290da
BH		 272/* vDSO has arch_setup_additional_pages */
273#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
1da177e4 274struct linux_binprm;
a7f290da
BH		 275extern int arch_setup_additional_pages(struct linux_binprm *bprm,
276 int executable_stack);
a99eb2ef 277#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b);
1da177e4
LT		 278
279/*
280 * The requirements here are:
281 * - keep the final alignment of sp (sp & 0xf)
282 * - make sure the 32-bit value at the first 16 byte aligned position of
283 * AUXV is greater than 16 for glibc compatibility.
284 * AT_IGNOREPPC is used for that.
285 * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
286 * even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
287 */
288#define ARCH_DLINFO \
289do { \
290 /* Handle glibc compatibility. */ \
291 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
292 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
293 /* Cache size items */ \
294 NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
295 NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
296 NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
a99eb2ef
BB		 297 VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->thread.vdso_base) \
298} while (0)
1da177e4
LT		 299
300/* PowerPC64 relocations defined by the ABIs */
301#define R_PPC64_NONE R_PPC_NONE
302#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address. */
303#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned. */
304#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address. */
305#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address. */
306#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
307#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */
308#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned. */
309#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN
310#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
311#define R_PPC64_REL24 R_PPC_REL24 /* PC relative 26 bit, word aligned. */
312#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit. */
313#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN
314#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN
315#define R_PPC64_GOT16 R_PPC_GOT16
316#define R_PPC64_GOT16_LO R_PPC_GOT16_LO
317#define R_PPC64_GOT16_HI R_PPC_GOT16_HI
318#define R_PPC64_GOT16_HA R_PPC_GOT16_HA
319
320#define R_PPC64_COPY R_PPC_COPY
321#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT
322#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT
323#define R_PPC64_RELATIVE R_PPC_RELATIVE
324
325#define R_PPC64_UADDR32 R_PPC_UADDR32
326#define R_PPC64_UADDR16 R_PPC_UADDR16
327#define R_PPC64_REL32 R_PPC_REL32
328#define R_PPC64_PLT32 R_PPC_PLT32
329#define R_PPC64_PLTREL32 R_PPC_PLTREL32
330#define R_PPC64_PLT16_LO R_PPC_PLT16_LO
331#define R_PPC64_PLT16_HI R_PPC_PLT16_HI
332#define R_PPC64_PLT16_HA R_PPC_PLT16_HA
333
334#define R_PPC64_SECTOFF R_PPC_SECTOFF
335#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO
336#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI
337#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA
338#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2. */
339#define R_PPC64_ADDR64 38 /* doubleword64 S + A. */
340#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A). */
341#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A). */
342#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A). */
343#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A). */
344#define R_PPC64_UADDR64 43 /* doubleword64 S + A. */
345#define R_PPC64_REL64 44 /* doubleword64 S + A - P. */
346#define R_PPC64_PLT64 45 /* doubleword64 L + A. */
347#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P. */
348#define R_PPC64_TOC16 47 /* half16* S + A - .TOC. */
349#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.). */
350#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.). */
351#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.). */
352#define R_PPC64_TOC 51 /* doubleword64 .TOC. */
353#define R_PPC64_PLTGOT16 52 /* half16* M + A. */
354#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A). */
355#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A). */
356#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A). */
357
358#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2. */
359#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2. */
360#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2. */
361#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2. */
362#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2. */
363#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2. */
364#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2. */
365#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2. */
366#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2. */
367#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2. */
368#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2. */
369
370/* PowerPC64 relocations defined for the TLS access ABI. */
371#define R_PPC64_TLS 67 /* none (sym+add)@tls */
372#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */
373#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */
374#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
375#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
376#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
377#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */
378#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */
379#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
380#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
381#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
382#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */
383#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
384#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
385#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
386#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
387#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
388#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
389#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
390#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
391#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */
392#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
393#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
394#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
395#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */
396#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
397#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */
398#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */
399#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */
400#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */
401#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */
402#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */
403#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */
404#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */
405#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */
406#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */
407#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */
408#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */
409#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */
410#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
411
412/* Keep this the last entry. */
413#define R_PPC64_NUM 107
414
a99eb2ef 415#endif /* _ASM_POWERPC_ELF_H */
Linux 6.x block layer and io_uring tree(s)