Commit | Line | Data |
---|---|---|
10b35d99 KG |
1 | #ifndef __ASM_POWERPC_CPUTABLE_H |
2 | #define __ASM_POWERPC_CPUTABLE_H | |
3 | ||
4 | #include <linux/config.h> | |
3ddfbcf1 | 5 | #include <asm/asm-compat.h> |
10b35d99 KG |
6 | |
7 | #define PPC_FEATURE_32 0x80000000 | |
8 | #define PPC_FEATURE_64 0x40000000 | |
9 | #define PPC_FEATURE_601_INSTR 0x20000000 | |
10 | #define PPC_FEATURE_HAS_ALTIVEC 0x10000000 | |
11 | #define PPC_FEATURE_HAS_FPU 0x08000000 | |
12 | #define PPC_FEATURE_HAS_MMU 0x04000000 | |
13 | #define PPC_FEATURE_HAS_4xxMAC 0x02000000 | |
14 | #define PPC_FEATURE_UNIFIED_CACHE 0x01000000 | |
15 | #define PPC_FEATURE_HAS_SPE 0x00800000 | |
16 | #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000 | |
17 | #define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000 | |
98599013 | 18 | #define PPC_FEATURE_NO_TB 0x00100000 |
10b35d99 KG |
19 | |
20 | #ifdef __KERNEL__ | |
21 | #ifndef __ASSEMBLY__ | |
22 | ||
23 | /* This structure can grow, it's real size is used by head.S code | |
24 | * via the mkdefs mechanism. | |
25 | */ | |
26 | struct cpu_spec; | |
27 | struct op_powerpc_model; | |
28 | ||
10b35d99 | 29 | typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); |
10b35d99 KG |
30 | |
31 | struct cpu_spec { | |
32 | /* CPU is matched via (PVR & pvr_mask) == pvr_value */ | |
33 | unsigned int pvr_mask; | |
34 | unsigned int pvr_value; | |
35 | ||
36 | char *cpu_name; | |
37 | unsigned long cpu_features; /* Kernel features */ | |
38 | unsigned int cpu_user_features; /* Userland features */ | |
39 | ||
40 | /* cache line sizes */ | |
41 | unsigned int icache_bsize; | |
42 | unsigned int dcache_bsize; | |
43 | ||
44 | /* number of performance monitor counters */ | |
45 | unsigned int num_pmcs; | |
46 | ||
47 | /* this is called to initialize various CPU bits like L1 cache, | |
48 | * BHT, SPD, etc... from head.S before branching to identify_machine | |
49 | */ | |
50 | cpu_setup_t cpu_setup; | |
10b35d99 KG |
51 | |
52 | /* Used by oprofile userspace to select the right counters */ | |
53 | char *oprofile_cpu_type; | |
54 | ||
55 | /* Processor specific oprofile operations */ | |
56 | struct op_powerpc_model *oprofile_model; | |
10b35d99 KG |
57 | }; |
58 | ||
10b35d99 | 59 | extern struct cpu_spec *cur_cpu_spec; |
10b35d99 | 60 | |
9b6b563c PM |
61 | extern void identify_cpu(unsigned long offset, unsigned long cpu); |
62 | extern void do_cpu_ftr_fixups(unsigned long offset); | |
63 | ||
10b35d99 KG |
64 | #endif /* __ASSEMBLY__ */ |
65 | ||
66 | /* CPU kernel features */ | |
67 | ||
68 | /* Retain the 32b definitions all use bottom half of word */ | |
69 | #define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001) | |
70 | #define CPU_FTR_L2CR ASM_CONST(0x0000000000000002) | |
71 | #define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004) | |
72 | #define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008) | |
73 | #define CPU_FTR_TAU ASM_CONST(0x0000000000000010) | |
74 | #define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020) | |
75 | #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040) | |
76 | #define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080) | |
77 | #define CPU_FTR_601 ASM_CONST(0x0000000000000100) | |
78 | #define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200) | |
79 | #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400) | |
80 | #define CPU_FTR_L3CR ASM_CONST(0x0000000000000800) | |
81 | #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000) | |
82 | #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000) | |
83 | #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000) | |
84 | #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000) | |
85 | #define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000) | |
86 | #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) | |
87 | #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) | |
88 | #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000) | |
89 | ||
90 | #ifdef __powerpc64__ | |
91 | /* Add the 64b processor unique features in the top half of the word */ | |
92 | #define CPU_FTR_SLB ASM_CONST(0x0000000100000000) | |
93 | #define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000) | |
94 | #define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000) | |
95 | #define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000) | |
96 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000) | |
97 | #define CPU_FTR_IABR ASM_CONST(0x0000002000000000) | |
98 | #define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000) | |
99 | #define CPU_FTR_CTRL ASM_CONST(0x0000008000000000) | |
100 | #define CPU_FTR_SMT ASM_CONST(0x0000010000000000) | |
101 | #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000) | |
102 | #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000) | |
103 | #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000) | |
3c726f8d | 104 | #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000) |
10b35d99 KG |
105 | #else |
106 | /* ensure on 32b processors the flags are available for compiling but | |
107 | * don't do anything */ | |
108 | #define CPU_FTR_SLB ASM_CONST(0x0) | |
109 | #define CPU_FTR_16M_PAGE ASM_CONST(0x0) | |
110 | #define CPU_FTR_TLBIEL ASM_CONST(0x0) | |
111 | #define CPU_FTR_NOEXECUTE ASM_CONST(0x0) | |
112 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0) | |
113 | #define CPU_FTR_IABR ASM_CONST(0x0) | |
114 | #define CPU_FTR_MMCRA ASM_CONST(0x0) | |
115 | #define CPU_FTR_CTRL ASM_CONST(0x0) | |
116 | #define CPU_FTR_SMT ASM_CONST(0x0) | |
117 | #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0) | |
118 | #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0) | |
119 | #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0) | |
3c726f8d | 120 | #define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0) |
10b35d99 KG |
121 | #endif |
122 | ||
123 | #ifndef __ASSEMBLY__ | |
124 | ||
10b35d99 KG |
125 | #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \ |
126 | CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \ | |
127 | CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL) | |
128 | ||
129 | /* iSeries doesn't support large pages */ | |
130 | #ifdef CONFIG_PPC_ISERIES | |
131 | #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE) | |
132 | #else | |
133 | #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE) | |
134 | #endif /* CONFIG_PPC_ISERIES */ | |
135 | ||
136 | /* We only set the altivec features if the kernel was compiled with altivec | |
137 | * support | |
138 | */ | |
139 | #ifdef CONFIG_ALTIVEC | |
140 | #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC | |
141 | #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC | |
142 | #else | |
143 | #define CPU_FTR_ALTIVEC_COMP 0 | |
144 | #define PPC_FEATURE_HAS_ALTIVEC_COMP 0 | |
145 | #endif | |
146 | ||
147 | /* We need to mark all pages as being coherent if we're SMP or we | |
148 | * have a 74[45]x and an MPC107 host bridge. | |
149 | */ | |
150 | #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) | |
151 | #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT | |
152 | #else | |
153 | #define CPU_FTR_COMMON 0 | |
154 | #endif | |
155 | ||
156 | /* The powersave features NAP & DOZE seems to confuse BDI when | |
157 | debugging. So if a BDI is used, disable theses | |
158 | */ | |
159 | #ifndef CONFIG_BDI_SWITCH | |
160 | #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE | |
161 | #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP | |
162 | #else | |
163 | #define CPU_FTR_MAYBE_CAN_DOZE 0 | |
164 | #define CPU_FTR_MAYBE_CAN_NAP 0 | |
165 | #endif | |
166 | ||
167 | #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \ | |
168 | !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ | |
169 | !defined(CONFIG_BOOKE)) | |
170 | ||
171 | enum { | |
172 | CPU_FTRS_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE, | |
173 | CPU_FTRS_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
174 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | | |
175 | CPU_FTR_MAYBE_CAN_NAP, | |
176 | CPU_FTRS_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
177 | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE, | |
178 | CPU_FTRS_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
179 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | | |
180 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, | |
181 | CPU_FTRS_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
182 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | | |
183 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, | |
184 | CPU_FTRS_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
185 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | | |
186 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP, | |
187 | CPU_FTRS_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
188 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | | |
189 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | | |
190 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM, | |
191 | CPU_FTRS_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
192 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | | |
193 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | | |
194 | CPU_FTR_NO_DPM, | |
195 | CPU_FTRS_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
196 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | | |
197 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | | |
198 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS, | |
199 | CPU_FTRS_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | | |
200 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | | |
201 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | | |
202 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS, | |
203 | CPU_FTRS_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
204 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | | |
205 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | | |
206 | CPU_FTR_MAYBE_CAN_NAP, | |
207 | CPU_FTRS_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
208 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | | |
209 | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | | |
210 | CPU_FTR_MAYBE_CAN_NAP, | |
211 | CPU_FTRS_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
212 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | | |
213 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | | |
214 | CPU_FTR_NEED_COHERENT, | |
215 | CPU_FTRS_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
216 | CPU_FTR_USE_TB | | |
217 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | | |
218 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | | |
219 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | | |
220 | CPU_FTR_NEED_COHERENT, | |
221 | CPU_FTRS_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
222 | CPU_FTR_USE_TB | | |
223 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | | |
224 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | | |
225 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT, | |
226 | CPU_FTRS_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
227 | CPU_FTR_USE_TB | | |
228 | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | | |
229 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | | |
230 | CPU_FTR_NEED_COHERENT, | |
231 | CPU_FTRS_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
232 | CPU_FTR_USE_TB | | |
233 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | | |
234 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | | |
235 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | | |
236 | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS, | |
237 | CPU_FTRS_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
238 | CPU_FTR_USE_TB | | |
239 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | | |
240 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | | |
241 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | | |
242 | CPU_FTR_NEED_COHERENT, | |
243 | CPU_FTRS_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
244 | CPU_FTR_USE_TB | | |
245 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | | |
246 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | | |
247 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | | |
248 | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC, | |
249 | CPU_FTRS_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
250 | CPU_FTR_USE_TB | | |
251 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | | |
252 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | | |
253 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | | |
254 | CPU_FTR_NEED_COHERENT, | |
255 | CPU_FTRS_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
256 | CPU_FTR_USE_TB | | |
257 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | | |
258 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | | |
259 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | | |
260 | CPU_FTR_NEED_COHERENT, | |
261 | CPU_FTRS_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
262 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB, | |
263 | CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | | |
264 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS, | |
265 | CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | | |
266 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS, | |
267 | CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
268 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, | |
269 | CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
270 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, | |
271 | CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
272 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE, | |
273 | CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | | |
274 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP | | |
275 | CPU_FTR_MAYBE_CAN_NAP, | |
276 | CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, | |
277 | CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, | |
278 | CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, | |
279 | CPU_FTRS_E200 = CPU_FTR_USE_TB, | |
280 | CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB, | |
281 | CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | |
282 | CPU_FTR_BIG_PHYS, | |
283 | CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON, | |
284 | #ifdef __powerpc64__ | |
285 | CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | |
286 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR, | |
287 | CPU_FTRS_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | |
288 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | | |
289 | CPU_FTR_MMCRA | CPU_FTR_CTRL, | |
290 | CPU_FTRS_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | |
291 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA, | |
292 | CPU_FTRS_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | |
293 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | | |
294 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA, | |
295 | CPU_FTRS_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | |
296 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | | |
297 | CPU_FTR_MMCRA | CPU_FTR_SMT | | |
298 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | | |
299 | CPU_FTR_MMCRA_SIHV, | |
300 | CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | |
301 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | | |
302 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT, | |
303 | CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | | |
304 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2, | |
305 | #endif | |
306 | ||
307 | CPU_FTRS_POSSIBLE = | |
308 | #if CLASSIC_PPC | |
309 | CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU | | |
310 | CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | | |
311 | CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX | | |
312 | CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 | | |
313 | CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | | |
314 | CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | | |
315 | CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | | |
316 | CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 | | |
317 | #else | |
318 | CPU_FTRS_GENERIC_32 | | |
319 | #endif | |
320 | #ifdef CONFIG_PPC64BRIDGE | |
321 | CPU_FTRS_POWER3_32 | | |
322 | #endif | |
323 | #ifdef CONFIG_POWER4 | |
324 | CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 | | |
325 | #endif | |
326 | #ifdef CONFIG_8xx | |
327 | CPU_FTRS_8XX | | |
328 | #endif | |
329 | #ifdef CONFIG_40x | |
330 | CPU_FTRS_40X | | |
331 | #endif | |
332 | #ifdef CONFIG_44x | |
333 | CPU_FTRS_44X | | |
334 | #endif | |
335 | #ifdef CONFIG_E200 | |
336 | CPU_FTRS_E200 | | |
337 | #endif | |
338 | #ifdef CONFIG_E500 | |
339 | CPU_FTRS_E500 | CPU_FTRS_E500_2 | | |
340 | #endif | |
341 | #ifdef __powerpc64__ | |
342 | CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | | |
343 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL | | |
3c726f8d | 344 | CPU_FTR_CI_LARGE_PAGE | |
10b35d99 KG |
345 | #endif |
346 | 0, | |
347 | ||
348 | CPU_FTRS_ALWAYS = | |
349 | #if CLASSIC_PPC | |
350 | CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU & | |
351 | CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & | |
352 | CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX & | |
353 | CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 & | |
354 | CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & | |
355 | CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & | |
356 | CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & | |
357 | CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 & | |
358 | #else | |
359 | CPU_FTRS_GENERIC_32 & | |
360 | #endif | |
361 | #ifdef CONFIG_PPC64BRIDGE | |
362 | CPU_FTRS_POWER3_32 & | |
363 | #endif | |
364 | #ifdef CONFIG_POWER4 | |
365 | CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 & | |
366 | #endif | |
367 | #ifdef CONFIG_8xx | |
368 | CPU_FTRS_8XX & | |
369 | #endif | |
370 | #ifdef CONFIG_40x | |
371 | CPU_FTRS_40X & | |
372 | #endif | |
373 | #ifdef CONFIG_44x | |
374 | CPU_FTRS_44X & | |
375 | #endif | |
376 | #ifdef CONFIG_E200 | |
377 | CPU_FTRS_E200 & | |
378 | #endif | |
379 | #ifdef CONFIG_E500 | |
380 | CPU_FTRS_E500 & CPU_FTRS_E500_2 & | |
381 | #endif | |
382 | #ifdef __powerpc64__ | |
383 | CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & | |
384 | CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL & | |
385 | #endif | |
386 | CPU_FTRS_POSSIBLE, | |
387 | }; | |
388 | ||
389 | static inline int cpu_has_feature(unsigned long feature) | |
390 | { | |
391 | return (CPU_FTRS_ALWAYS & feature) || | |
392 | (CPU_FTRS_POSSIBLE | |
10b35d99 | 393 | & cur_cpu_spec->cpu_features |
10b35d99 KG |
394 | & feature); |
395 | } | |
396 | ||
397 | #endif /* !__ASSEMBLY__ */ | |
398 | ||
399 | #ifdef __ASSEMBLY__ | |
400 | ||
401 | #define BEGIN_FTR_SECTION 98: | |
402 | ||
403 | #ifndef __powerpc64__ | |
404 | #define END_FTR_SECTION(msk, val) \ | |
405 | 99: \ | |
406 | .section __ftr_fixup,"a"; \ | |
407 | .align 2; \ | |
408 | .long msk; \ | |
409 | .long val; \ | |
410 | .long 98b; \ | |
411 | .long 99b; \ | |
412 | .previous | |
413 | #else /* __powerpc64__ */ | |
414 | #define END_FTR_SECTION(msk, val) \ | |
415 | 99: \ | |
416 | .section __ftr_fixup,"a"; \ | |
417 | .align 3; \ | |
418 | .llong msk; \ | |
419 | .llong val; \ | |
420 | .llong 98b; \ | |
421 | .llong 99b; \ | |
422 | .previous | |
423 | #endif /* __powerpc64__ */ | |
424 | ||
425 | #define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk)) | |
426 | #define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0) | |
427 | #endif /* __ASSEMBLY__ */ | |
428 | ||
429 | #endif /* __KERNEL__ */ | |
430 | #endif /* __ASM_POWERPC_CPUTABLE_H */ |