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Merge git://git.kernel.org/pub/scm/linux/kernel/git/sfrench/cifs-2.6
[linux-2.6-block.git] / include / asm-powerpc / cpm2.h
CommitLineData
33d71d26
KG		 1/*
2 * Communication Processor Module v2.
3 *
4 * This file contains structures and information for the communication
5 * processor channels found in the dual port RAM or parameter RAM.
6 * All CPM control and status is available through the CPM2 internal
7 * memory map. See immap_cpm2.h for details.
8 */
9#ifdef __KERNEL__
10#ifndef __CPM2__
11#define __CPM2__
12
13#include <asm/immap_cpm2.h>
15f8c604 14#include <asm/cpm.h>
33d71d26 15
0bfd5df5
KG		 16#ifdef CONFIG_PPC_85xx
17#define CPM_MAP_ADDR (get_immrbase() + 0x80000)
18#endif
19
33d71d26
KG		 20/* CPM Command register.
21*/
22#define CPM_CR_RST ((uint)0x80000000)
23#define CPM_CR_PAGE ((uint)0x7c000000)
24#define CPM_CR_SBLOCK ((uint)0x03e00000)
25#define CPM_CR_FLG ((uint)0x00010000)
26#define CPM_CR_MCN ((uint)0x00003fc0)
27#define CPM_CR_OPCODE ((uint)0x0000000f)
28
29/* Device sub-block and page codes.
30*/
31#define CPM_CR_SCC1_SBLOCK (0x04)
32#define CPM_CR_SCC2_SBLOCK (0x05)
33#define CPM_CR_SCC3_SBLOCK (0x06)
34#define CPM_CR_SCC4_SBLOCK (0x07)
35#define CPM_CR_SMC1_SBLOCK (0x08)
36#define CPM_CR_SMC2_SBLOCK (0x09)
37#define CPM_CR_SPI_SBLOCK (0x0a)
38#define CPM_CR_I2C_SBLOCK (0x0b)
39#define CPM_CR_TIMER_SBLOCK (0x0f)
40#define CPM_CR_RAND_SBLOCK (0x0e)
41#define CPM_CR_FCC1_SBLOCK (0x10)
42#define CPM_CR_FCC2_SBLOCK (0x11)
43#define CPM_CR_FCC3_SBLOCK (0x12)
44#define CPM_CR_IDMA1_SBLOCK (0x14)
45#define CPM_CR_IDMA2_SBLOCK (0x15)
46#define CPM_CR_IDMA3_SBLOCK (0x16)
47#define CPM_CR_IDMA4_SBLOCK (0x17)
48#define CPM_CR_MCC1_SBLOCK (0x1c)
49
50#define CPM_CR_FCC_SBLOCK(x) (x + 0x10)
51
52#define CPM_CR_SCC1_PAGE (0x00)
53#define CPM_CR_SCC2_PAGE (0x01)
54#define CPM_CR_SCC3_PAGE (0x02)
55#define CPM_CR_SCC4_PAGE (0x03)
56#define CPM_CR_SMC1_PAGE (0x07)
57#define CPM_CR_SMC2_PAGE (0x08)
58#define CPM_CR_SPI_PAGE (0x09)
59#define CPM_CR_I2C_PAGE (0x0a)
60#define CPM_CR_TIMER_PAGE (0x0a)
61#define CPM_CR_RAND_PAGE (0x0a)
62#define CPM_CR_FCC1_PAGE (0x04)
63#define CPM_CR_FCC2_PAGE (0x05)
64#define CPM_CR_FCC3_PAGE (0x06)
65#define CPM_CR_IDMA1_PAGE (0x07)
66#define CPM_CR_IDMA2_PAGE (0x08)
67#define CPM_CR_IDMA3_PAGE (0x09)
68#define CPM_CR_IDMA4_PAGE (0x0a)
69#define CPM_CR_MCC1_PAGE (0x07)
70#define CPM_CR_MCC2_PAGE (0x08)
71
72#define CPM_CR_FCC_PAGE(x) (x + 0x04)
73
e24e788a 74/* CPM2-specific opcodes (see cpm.h for common opcodes)
33d71d26 75*/
33d71d26 76#define CPM_CR_START_IDMA ((ushort)0x0009)
33d71d26
KG		 77
78#define mk_cr_cmd(PG, SBC, MCN, OP) \
79 ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
80
15f8c604 81#ifndef CONFIG_PPC_CPM_NEW_BINDING
33d71d26
KG		 82/* Dual Port RAM addresses. The first 16K is available for almost
83 * any CPM use, so we put the BDs there. The first 128 bytes are
84 * used for SMC1 and SMC2 parameter RAM, so we start allocating
85 * BDs above that. All of this must change when we start
86 * downloading RAM microcode.
87 */
88#define CPM_DATAONLY_BASE ((uint)128)
89#define CPM_DP_NOSPACE ((uint)0x7fffffff)
90#if defined(CONFIG_8272) || defined(CONFIG_MPC8555)
91#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
92#define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
93#else
94#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
95#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000)
96#endif
15f8c604 97#endif
33d71d26
KG		 98
99/* The number of pages of host memory we allocate for CPM. This is
100 * done early in kernel initialization to get physically contiguous
101 * pages.
102 */
103#define NUM_CPM_HOST_PAGES 2
104
105/* Export the base address of the communication processor registers
106 * and dual port ram.
107 */
449012da 108extern cpm_cpm2_t __iomem *cpmp; /* Pointer to comm processor */
33d71d26 109
15f8c604
SW		 110#ifdef CONFIG_PPC_CPM_NEW_BINDING
111#define cpm_dpalloc cpm_muram_alloc
112#define cpm_dpfree cpm_muram_free
113#define cpm_dpram_addr cpm_muram_addr
114#else
33d71d26
KG		 115extern unsigned long cpm_dpalloc(uint size, uint align);
116extern int cpm_dpfree(unsigned long offset);
117extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align);
118extern void cpm_dpdump(void);
119extern void *cpm_dpram_addr(unsigned long offset);
15f8c604
SW		 120#endif
121
33d71d26
KG		 122extern void cpm_setbrg(uint brg, uint rate);
123extern void cpm2_fastbrg(uint brg, uint rate, int div16);
124extern void cpm2_reset(void);
125
33d71d26
KG		 126/* Function code bits, usually generic to devices.
127*/
128#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
129#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
130#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
131#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
132#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
133
134/* Parameter RAM offsets from the base.
135*/
136#define PROFF_SCC1 ((uint)0x8000)
137#define PROFF_SCC2 ((uint)0x8100)
138#define PROFF_SCC3 ((uint)0x8200)
139#define PROFF_SCC4 ((uint)0x8300)
140#define PROFF_FCC1 ((uint)0x8400)
141#define PROFF_FCC2 ((uint)0x8500)
142#define PROFF_FCC3 ((uint)0x8600)
143#define PROFF_MCC1 ((uint)0x8700)
144#define PROFF_SMC1_BASE ((uint)0x87fc)
145#define PROFF_IDMA1_BASE ((uint)0x87fe)
146#define PROFF_MCC2 ((uint)0x8800)
147#define PROFF_SMC2_BASE ((uint)0x88fc)
148#define PROFF_IDMA2_BASE ((uint)0x88fe)
149#define PROFF_SPI_BASE ((uint)0x89fc)
150#define PROFF_IDMA3_BASE ((uint)0x89fe)
151#define PROFF_TIMERS ((uint)0x8ae0)
152#define PROFF_REVNUM ((uint)0x8af0)
153#define PROFF_RAND ((uint)0x8af8)
154#define PROFF_I2C_BASE ((uint)0x8afc)
155#define PROFF_IDMA4_BASE ((uint)0x8afe)
156
157#define PROFF_SCC_SIZE ((uint)0x100)
158#define PROFF_FCC_SIZE ((uint)0x100)
159#define PROFF_SMC_SIZE ((uint)64)
160
161/* The SMCs are relocated to any of the first eight DPRAM pages.
162 * We will fix these at the first locations of DPRAM, until we
163 * get some microcode patches :-).
164 * The parameter ram space for the SMCs is fifty-some bytes, and
165 * they are required to start on a 64 byte boundary.
166 */
167#define PROFF_SMC1 (0)
168#define PROFF_SMC2 (64)
169
170
171/* Define enough so I can at least use the serial port as a UART.
172 */
173typedef struct smc_uart {
174 ushort smc_rbase; /* Rx Buffer descriptor base address */
175 ushort smc_tbase; /* Tx Buffer descriptor base address */
176 u_char smc_rfcr; /* Rx function code */
177 u_char smc_tfcr; /* Tx function code */
178 ushort smc_mrblr; /* Max receive buffer length */
179 uint smc_rstate; /* Internal */
180 uint smc_idp; /* Internal */
181 ushort smc_rbptr; /* Internal */
182 ushort smc_ibc; /* Internal */
183 uint smc_rxtmp; /* Internal */
184 uint smc_tstate; /* Internal */
185 uint smc_tdp; /* Internal */
186 ushort smc_tbptr; /* Internal */
187 ushort smc_tbc; /* Internal */
188 uint smc_txtmp; /* Internal */
189 ushort smc_maxidl; /* Maximum idle characters */
190 ushort smc_tmpidl; /* Temporary idle counter */
191 ushort smc_brklen; /* Last received break length */
192 ushort smc_brkec; /* rcv'd break condition counter */
193 ushort smc_brkcr; /* xmt break count register */
194 ushort smc_rmask; /* Temporary bit mask */
195 uint smc_stmp; /* SDMA Temp */
196} smc_uart_t;
197
198/* SMC uart mode register (Internal memory map).
199*/
200#define SMCMR_REN ((ushort)0x0001)
201#define SMCMR_TEN ((ushort)0x0002)
202#define SMCMR_DM ((ushort)0x000c)
203#define SMCMR_SM_GCI ((ushort)0x0000)
204#define SMCMR_SM_UART ((ushort)0x0020)
205#define SMCMR_SM_TRANS ((ushort)0x0030)
206#define SMCMR_SM_MASK ((ushort)0x0030)
207#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
208#define SMCMR_REVD SMCMR_PM_EVEN
209#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
210#define SMCMR_BS SMCMR_PEN
211#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
212#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
213#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
214
215/* SMC Event and Mask register.
216*/
217#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
218#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
219#define SMCM_TXE ((unsigned char)0x10)
220#define SMCM_BSY ((unsigned char)0x04)
221#define SMCM_TX ((unsigned char)0x02)
222#define SMCM_RX ((unsigned char)0x01)
223
224/* Baud rate generators.
225*/
226#define CPM_BRG_RST ((uint)0x00020000)
227#define CPM_BRG_EN ((uint)0x00010000)
228#define CPM_BRG_EXTC_INT ((uint)0x00000000)
229#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
230#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
231#define CPM_BRG_ATB ((uint)0x00002000)
232#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
233#define CPM_BRG_DIV16 ((uint)0x00000001)
234
235/* SCCs.
236*/
237#define SCC_GSMRH_IRP ((uint)0x00040000)
238#define SCC_GSMRH_GDE ((uint)0x00010000)
239#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
240#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
241#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
242#define SCC_GSMRH_REVD ((uint)0x00002000)
243#define SCC_GSMRH_TRX ((uint)0x00001000)
244#define SCC_GSMRH_TTX ((uint)0x00000800)
245#define SCC_GSMRH_CDP ((uint)0x00000400)
246#define SCC_GSMRH_CTSP ((uint)0x00000200)
247#define SCC_GSMRH_CDS ((uint)0x00000100)
248#define SCC_GSMRH_CTSS ((uint)0x00000080)
249#define SCC_GSMRH_TFL ((uint)0x00000040)
250#define SCC_GSMRH_RFW ((uint)0x00000020)
251#define SCC_GSMRH_TXSY ((uint)0x00000010)
252#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
253#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
254#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
255#define SCC_GSMRH_RTSM ((uint)0x00000002)
256#define SCC_GSMRH_RSYN ((uint)0x00000001)
257
258#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
259#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
260#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
261#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
262#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
263#define SCC_GSMRL_TCI ((uint)0x10000000)
264#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
265#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
266#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
267#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
268#define SCC_GSMRL_RINV ((uint)0x02000000)
269#define SCC_GSMRL_TINV ((uint)0x01000000)
270#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
271#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
272#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
273#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
274#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
275#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
276#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
277#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
278#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
279#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
280#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
281#define SCC_GSMRL_TEND ((uint)0x00040000)
282#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
283#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
284#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
285#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
286#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
287#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
288#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
289#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
290#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
291#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
292#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
293#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
294#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
295#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
296#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
297#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
298#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
299#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
300#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
301#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
302#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
303#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
304#define SCC_GSMRL_ENR ((uint)0x00000020)
305#define SCC_GSMRL_ENT ((uint)0x00000010)
306#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
307#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
308#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
309#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
310#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
311#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
312#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
313#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
314#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
315#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
316
317#define SCC_TODR_TOD ((ushort)0x8000)
318
319/* SCC Event and Mask register.
320*/
321#define SCCM_TXE ((unsigned char)0x10)
322#define SCCM_BSY ((unsigned char)0x04)
323#define SCCM_TX ((unsigned char)0x02)
324#define SCCM_RX ((unsigned char)0x01)
325
326typedef struct scc_param {
327 ushort scc_rbase; /* Rx Buffer descriptor base address */
328 ushort scc_tbase; /* Tx Buffer descriptor base address */
329 u_char scc_rfcr; /* Rx function code */
330 u_char scc_tfcr; /* Tx function code */
331 ushort scc_mrblr; /* Max receive buffer length */
332 uint scc_rstate; /* Internal */
333 uint scc_idp; /* Internal */
334 ushort scc_rbptr; /* Internal */
335 ushort scc_ibc; /* Internal */
336 uint scc_rxtmp; /* Internal */
337 uint scc_tstate; /* Internal */
338 uint scc_tdp; /* Internal */
339 ushort scc_tbptr; /* Internal */
340 ushort scc_tbc; /* Internal */
341 uint scc_txtmp; /* Internal */
342 uint scc_rcrc; /* Internal */
343 uint scc_tcrc; /* Internal */
344} sccp_t;
345
346/* CPM Ethernet through SCC1.
347 */
348typedef struct scc_enet {
349 sccp_t sen_genscc;
350 uint sen_cpres; /* Preset CRC */
351 uint sen_cmask; /* Constant mask for CRC */
352 uint sen_crcec; /* CRC Error counter */
353 uint sen_alec; /* alignment error counter */
354 uint sen_disfc; /* discard frame counter */
355 ushort sen_pads; /* Tx short frame pad character */
356 ushort sen_retlim; /* Retry limit threshold */
357 ushort sen_retcnt; /* Retry limit counter */
358 ushort sen_maxflr; /* maximum frame length register */
359 ushort sen_minflr; /* minimum frame length register */
360 ushort sen_maxd1; /* maximum DMA1 length */
361 ushort sen_maxd2; /* maximum DMA2 length */
362 ushort sen_maxd; /* Rx max DMA */
363 ushort sen_dmacnt; /* Rx DMA counter */
364 ushort sen_maxb; /* Max BD byte count */
365 ushort sen_gaddr1; /* Group address filter */
366 ushort sen_gaddr2;
367 ushort sen_gaddr3;
368 ushort sen_gaddr4;
369 uint sen_tbuf0data0; /* Save area 0 - current frame */
370 uint sen_tbuf0data1; /* Save area 1 - current frame */
371 uint sen_tbuf0rba; /* Internal */
372 uint sen_tbuf0crc; /* Internal */
373 ushort sen_tbuf0bcnt; /* Internal */
374 ushort sen_paddrh; /* physical address (MSB) */
375 ushort sen_paddrm;
376 ushort sen_paddrl; /* physical address (LSB) */
377 ushort sen_pper; /* persistence */
378 ushort sen_rfbdptr; /* Rx first BD pointer */
379 ushort sen_tfbdptr; /* Tx first BD pointer */
380 ushort sen_tlbdptr; /* Tx last BD pointer */
381 uint sen_tbuf1data0; /* Save area 0 - current frame */
382 uint sen_tbuf1data1; /* Save area 1 - current frame */
383 uint sen_tbuf1rba; /* Internal */
384 uint sen_tbuf1crc; /* Internal */
385 ushort sen_tbuf1bcnt; /* Internal */
386 ushort sen_txlen; /* Tx Frame length counter */
387 ushort sen_iaddr1; /* Individual address filter */
388 ushort sen_iaddr2;
389 ushort sen_iaddr3;
390 ushort sen_iaddr4;
391 ushort sen_boffcnt; /* Backoff counter */
392
393 /* NOTE: Some versions of the manual have the following items
394 * incorrectly documented. Below is the proper order.
395 */
396 ushort sen_taddrh; /* temp address (MSB) */
397 ushort sen_taddrm;
398 ushort sen_taddrl; /* temp address (LSB) */
399} scc_enet_t;
400
401
402/* SCC Event register as used by Ethernet.
403*/
404#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
405#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
406#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
407#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
408#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
409#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
410
411/* SCC Mode Register (PSMR) as used by Ethernet.
412*/
413#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
414#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
415#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
416#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
417#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
418#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
419#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
420#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
421#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
422#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
423#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
424#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
425#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
426
33d71d26
KG		 427/* SCC as UART
428*/
429typedef struct scc_uart {
430 sccp_t scc_genscc;
431 uint scc_res1; /* Reserved */
432 uint scc_res2; /* Reserved */
433 ushort scc_maxidl; /* Maximum idle chars */
434 ushort scc_idlc; /* temp idle counter */
435 ushort scc_brkcr; /* Break count register */
436 ushort scc_parec; /* receive parity error counter */
437 ushort scc_frmec; /* receive framing error counter */
438 ushort scc_nosec; /* receive noise counter */
439 ushort scc_brkec; /* receive break condition counter */
440 ushort scc_brkln; /* last received break length */
441 ushort scc_uaddr1; /* UART address character 1 */
442 ushort scc_uaddr2; /* UART address character 2 */
443 ushort scc_rtemp; /* Temp storage */
444 ushort scc_toseq; /* Transmit out of sequence char */
445 ushort scc_char1; /* control character 1 */
446 ushort scc_char2; /* control character 2 */
447 ushort scc_char3; /* control character 3 */
448 ushort scc_char4; /* control character 4 */
449 ushort scc_char5; /* control character 5 */
450 ushort scc_char6; /* control character 6 */
451 ushort scc_char7; /* control character 7 */
452 ushort scc_char8; /* control character 8 */
453 ushort scc_rccm; /* receive control character mask */
454 ushort scc_rccr; /* receive control character register */
455 ushort scc_rlbc; /* receive last break character */
456} scc_uart_t;
457
458/* SCC Event and Mask registers when it is used as a UART.
459*/
460#define UART_SCCM_GLR ((ushort)0x1000)
461#define UART_SCCM_GLT ((ushort)0x0800)
462#define UART_SCCM_AB ((ushort)0x0200)
463#define UART_SCCM_IDL ((ushort)0x0100)
464#define UART_SCCM_GRA ((ushort)0x0080)
465#define UART_SCCM_BRKE ((ushort)0x0040)
466#define UART_SCCM_BRKS ((ushort)0x0020)
467#define UART_SCCM_CCR ((ushort)0x0008)
468#define UART_SCCM_BSY ((ushort)0x0004)
469#define UART_SCCM_TX ((ushort)0x0002)
470#define UART_SCCM_RX ((ushort)0x0001)
471
472/* The SCC PSMR when used as a UART.
473*/
474#define SCU_PSMR_FLC ((ushort)0x8000)
475#define SCU_PSMR_SL ((ushort)0x4000)
476#define SCU_PSMR_CL ((ushort)0x3000)
477#define SCU_PSMR_UM ((ushort)0x0c00)
478#define SCU_PSMR_FRZ ((ushort)0x0200)
479#define SCU_PSMR_RZS ((ushort)0x0100)
480#define SCU_PSMR_SYN ((ushort)0x0080)
481#define SCU_PSMR_DRT ((ushort)0x0040)
482#define SCU_PSMR_PEN ((ushort)0x0010)
483#define SCU_PSMR_RPM ((ushort)0x000c)
484#define SCU_PSMR_REVP ((ushort)0x0008)
485#define SCU_PSMR_TPM ((ushort)0x0003)
486#define SCU_PSMR_TEVP ((ushort)0x0002)
487
488/* CPM Transparent mode SCC.
489 */
490typedef struct scc_trans {
491 sccp_t st_genscc;
492 uint st_cpres; /* Preset CRC */
493 uint st_cmask; /* Constant mask for CRC */
494} scc_trans_t;
495
33d71d26
KG		 496/* How about some FCCs.....
497*/
498#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
499#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
500#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
501#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
502#define FCC_GFMR_TCI ((uint)0x20000000)
503#define FCC_GFMR_TRX ((uint)0x10000000)
504#define FCC_GFMR_TTX ((uint)0x08000000)
505#define FCC_GFMR_TTX ((uint)0x08000000)
506#define FCC_GFMR_CDP ((uint)0x04000000)
507#define FCC_GFMR_CTSP ((uint)0x02000000)
508#define FCC_GFMR_CDS ((uint)0x01000000)
509#define FCC_GFMR_CTSS ((uint)0x00800000)
510#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
511#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
512#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
513#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
514#define FCC_GFMR_RTSM ((uint)0x00002000)
515#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
516#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
517#define FCC_GFMR_REVD ((uint)0x00000400)
518#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
519#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
520#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
521#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
522#define FCC_GFMR_ENR ((uint)0x00000020)
523#define FCC_GFMR_ENT ((uint)0x00000010)
524#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
525#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
526#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
527
528/* Generic FCC parameter ram.
529*/
530typedef struct fcc_param {
531 ushort fcc_riptr; /* Rx Internal temp pointer */
532 ushort fcc_tiptr; /* Tx Internal temp pointer */
533 ushort fcc_res1;
534 ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
535 uint fcc_rstate; /* Upper byte is Func code, must be set */
536 uint fcc_rbase; /* Receive BD base */
537 ushort fcc_rbdstat; /* RxBD status */
538 ushort fcc_rbdlen; /* RxBD down counter */
539 uint fcc_rdptr; /* RxBD internal data pointer */
540 uint fcc_tstate; /* Upper byte is Func code, must be set */
541 uint fcc_tbase; /* Transmit BD base */
542 ushort fcc_tbdstat; /* TxBD status */
543 ushort fcc_tbdlen; /* TxBD down counter */
544 uint fcc_tdptr; /* TxBD internal data pointer */
545 uint fcc_rbptr; /* Rx BD Internal buf pointer */
546 uint fcc_tbptr; /* Tx BD Internal buf pointer */
547 uint fcc_rcrc; /* Rx temp CRC */
548 uint fcc_res2;
549 uint fcc_tcrc; /* Tx temp CRC */
550} fccp_t;
551
552
553/* Ethernet controller through FCC.
554*/
555typedef struct fcc_enet {
556 fccp_t fen_genfcc;
557 uint fen_statbuf; /* Internal status buffer */
558 uint fen_camptr; /* CAM address */
559 uint fen_cmask; /* Constant mask for CRC */
560 uint fen_cpres; /* Preset CRC */
561 uint fen_crcec; /* CRC Error counter */
562 uint fen_alec; /* alignment error counter */
563 uint fen_disfc; /* discard frame counter */
564 ushort fen_retlim; /* Retry limit */
565 ushort fen_retcnt; /* Retry counter */
566 ushort fen_pper; /* Persistence */
567 ushort fen_boffcnt; /* backoff counter */
568 uint fen_gaddrh; /* Group address filter, high 32-bits */
569 uint fen_gaddrl; /* Group address filter, low 32-bits */
570 ushort fen_tfcstat; /* out of sequence TxBD */
571 ushort fen_tfclen;
572 uint fen_tfcptr;
573 ushort fen_mflr; /* Maximum frame length (1518) */
574 ushort fen_paddrh; /* MAC address */
575 ushort fen_paddrm;
576 ushort fen_paddrl;
577 ushort fen_ibdcount; /* Internal BD counter */
578 ushort fen_ibdstart; /* Internal BD start pointer */
579 ushort fen_ibdend; /* Internal BD end pointer */
580 ushort fen_txlen; /* Internal Tx frame length counter */
581 uint fen_ibdbase[8]; /* Internal use */
582 uint fen_iaddrh; /* Individual address filter */
583 uint fen_iaddrl;
584 ushort fen_minflr; /* Minimum frame length (64) */
585 ushort fen_taddrh; /* Filter transfer MAC address */
586 ushort fen_taddrm;
587 ushort fen_taddrl;
588 ushort fen_padptr; /* Pointer to pad byte buffer */
589 ushort fen_cftype; /* control frame type */
590 ushort fen_cfrange; /* control frame range */
591 ushort fen_maxb; /* maximum BD count */
592 ushort fen_maxd1; /* Max DMA1 length (1520) */
593 ushort fen_maxd2; /* Max DMA2 length (1520) */
594 ushort fen_maxd; /* internal max DMA count */
595 ushort fen_dmacnt; /* internal DMA counter */
596 uint fen_octc; /* Total octect counter */
597 uint fen_colc; /* Total collision counter */
598 uint fen_broc; /* Total broadcast packet counter */
599 uint fen_mulc; /* Total multicast packet count */
600 uint fen_uspc; /* Total packets < 64 bytes */
601 uint fen_frgc; /* Total packets < 64 bytes with errors */
602 uint fen_ospc; /* Total packets > 1518 */
603 uint fen_jbrc; /* Total packets > 1518 with errors */
604 uint fen_p64c; /* Total packets == 64 bytes */
605 uint fen_p65c; /* Total packets 64 < bytes <= 127 */
606 uint fen_p128c; /* Total packets 127 < bytes <= 255 */
607 uint fen_p256c; /* Total packets 256 < bytes <= 511 */
608 uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
609 uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
610 uint fen_cambuf; /* Internal CAM buffer poiner */
611 ushort fen_rfthr; /* Received frames threshold */
612 ushort fen_rfcnt; /* Received frames count */
613} fcc_enet_t;
614
615/* FCC Event/Mask register as used by Ethernet.
616*/
617#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
618#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
619#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
620#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
621#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
622#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
623#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
624#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
625
626/* FCC Mode Register (FPSMR) as used by Ethernet.
627*/
628#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
629#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
630#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
631#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
632#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
633#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
634#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
635#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
636#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
637#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
638#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
639#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
640#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
641
642/* IIC parameter RAM.
643*/
644typedef struct iic {
645 ushort iic_rbase; /* Rx Buffer descriptor base address */
646 ushort iic_tbase; /* Tx Buffer descriptor base address */
647 u_char iic_rfcr; /* Rx function code */
648 u_char iic_tfcr; /* Tx function code */
649 ushort iic_mrblr; /* Max receive buffer length */
650 uint iic_rstate; /* Internal */
651 uint iic_rdp; /* Internal */
652 ushort iic_rbptr; /* Internal */
653 ushort iic_rbc; /* Internal */
654 uint iic_rxtmp; /* Internal */
655 uint iic_tstate; /* Internal */
656 uint iic_tdp; /* Internal */
657 ushort iic_tbptr; /* Internal */
658 ushort iic_tbc; /* Internal */
659 uint iic_txtmp; /* Internal */
660} iic_t;
661
662/* SPI parameter RAM.
663*/
664typedef struct spi {
665 ushort spi_rbase; /* Rx Buffer descriptor base address */
666 ushort spi_tbase; /* Tx Buffer descriptor base address */
667 u_char spi_rfcr; /* Rx function code */
668 u_char spi_tfcr; /* Tx function code */
669 ushort spi_mrblr; /* Max receive buffer length */
670 uint spi_rstate; /* Internal */
671 uint spi_rdp; /* Internal */
672 ushort spi_rbptr; /* Internal */
673 ushort spi_rbc; /* Internal */
674 uint spi_rxtmp; /* Internal */
675 uint spi_tstate; /* Internal */
676 uint spi_tdp; /* Internal */
677 ushort spi_tbptr; /* Internal */
678 ushort spi_tbc; /* Internal */
679 uint spi_txtmp; /* Internal */
680 uint spi_res; /* Tx temp. */
681 uint spi_res1[4]; /* SDMA temp. */
682} spi_t;
683
684/* SPI Mode register.
685*/
686#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
687#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
688#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
689#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
690#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
691#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
692#define SPMODE_EN ((ushort)0x0100) /* Enable */
693#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
694#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
695
696#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
697#define SPMODE_PM(x) ((x) &0xF)
698
699#define SPI_EB ((u_char)0x10) /* big endian byte order */
700
33d71d26
KG		 701/* IDMA parameter RAM
702*/
703typedef struct idma {
704 ushort ibase; /* IDMA buffer descriptor table base address */
705 ushort dcm; /* DMA channel mode */
706 ushort ibdptr; /* IDMA current buffer descriptor pointer */
707 ushort dpr_buf; /* IDMA transfer buffer base address */
708 ushort buf_inv; /* internal buffer inventory */
709 ushort ss_max; /* steady-state maximum transfer size */
710 ushort dpr_in_ptr; /* write pointer inside the internal buffer */
711 ushort sts; /* source transfer size */
712 ushort dpr_out_ptr; /* read pointer inside the internal buffer */
713 ushort seob; /* source end of burst */
714 ushort deob; /* destination end of burst */
715 ushort dts; /* destination transfer size */
716 ushort ret_add; /* return address when working in ERM=1 mode */
717 ushort res0; /* reserved */
718 uint bd_cnt; /* internal byte count */
719 uint s_ptr; /* source internal data pointer */
720 uint d_ptr; /* destination internal data pointer */
721 uint istate; /* internal state */
722 u_char res1[20]; /* pad to 64-byte length */
723} idma_t;
724
725/* DMA channel mode bit fields
726*/
727#define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
728#define IDMA_DCM_LP ((ushort)0x4000) /* low priority */
729#define IDMA_DCM_TC2 ((ushort)0x0400) /* value driven on TC[2] */
730#define IDMA_DCM_DMA_WRAP_MASK ((ushort)0x01c0) /* mask for DMA wrap */
731#define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
732#define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
733#define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
734#define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
735#define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
736#define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
737#define IDMA_DCM_SINC ((ushort)0x0020) /* source inc addr */
738#define IDMA_DCM_DINC ((ushort)0x0010) /* destination inc addr */
739#define IDMA_DCM_ERM ((ushort)0x0008) /* external request mode */
740#define IDMA_DCM_DT ((ushort)0x0004) /* DONE treatment */
741#define IDMA_DCM_SD_MASK ((ushort)0x0003) /* mask for SD bit field */
742#define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
743#define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
744#define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
745
746/* IDMA Buffer Descriptors
747*/
748typedef struct idma_bd {
749 uint flags;
750 uint len; /* data length */
751 uint src; /* source data buffer pointer */
752 uint dst; /* destination data buffer pointer */
753} idma_bd_t;
754
755/* IDMA buffer descriptor flag bit fields
756*/
757#define IDMA_BD_V ((uint)0x80000000) /* valid */
758#define IDMA_BD_W ((uint)0x20000000) /* wrap */
759#define IDMA_BD_I ((uint)0x10000000) /* interrupt */
760#define IDMA_BD_L ((uint)0x08000000) /* last */
761#define IDMA_BD_CM ((uint)0x02000000) /* continuous mode */
762#define IDMA_BD_SDN ((uint)0x00400000) /* source done */
763#define IDMA_BD_DDN ((uint)0x00200000) /* destination done */
764#define IDMA_BD_DGBL ((uint)0x00100000) /* destination global */
765#define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */
766#define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */
767#define IDMA_BD_DDTB ((uint)0x00010000) /* destination data bus */
768#define IDMA_BD_SGBL ((uint)0x00002000) /* source global */
769#define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */
770#define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */
771#define IDMA_BD_SDTB ((uint)0x00000200) /* source data bus */
772
773/* per-channel IDMA registers
774*/
775typedef struct im_idma {
776 u_char idsr; /* IDMAn event status register */
777 u_char res0[3];
778 u_char idmr; /* IDMAn event mask register */
779 u_char res1[3];
780} im_idma_t;
781
782/* IDMA event register bit fields
783*/
784#define IDMA_EVENT_SC ((unsigned char)0x08) /* stop completed */
785#define IDMA_EVENT_OB ((unsigned char)0x04) /* out of buffers */
786#define IDMA_EVENT_EDN ((unsigned char)0x02) /* external DONE asserted */
787#define IDMA_EVENT_BC ((unsigned char)0x01) /* buffer descriptor complete */
788
789/* RISC Controller Configuration Register (RCCR) bit fields
790*/
791#define RCCR_TIME ((uint)0x80000000) /* timer enable */
792#define RCCR_TIMEP_MASK ((uint)0x3f000000) /* mask for timer period bit field */
793#define RCCR_DR0M ((uint)0x00800000) /* IDMA0 request mode */
794#define RCCR_DR1M ((uint)0x00400000) /* IDMA1 request mode */
795#define RCCR_DR2M ((uint)0x00000080) /* IDMA2 request mode */
796#define RCCR_DR3M ((uint)0x00000040) /* IDMA3 request mode */
797#define RCCR_DR0QP_MASK ((uint)0x00300000) /* mask for IDMA0 req priority */
798#define RCCR_DR0QP_HIGH ((uint)0x00000000) /* IDMA0 has high req priority */
799#define RCCR_DR0QP_MED ((uint)0x00100000) /* IDMA0 has medium req priority */
800#define RCCR_DR0QP_LOW ((uint)0x00200000) /* IDMA0 has low req priority */
801#define RCCR_DR1QP_MASK ((uint)0x00030000) /* mask for IDMA1 req priority */
802#define RCCR_DR1QP_HIGH ((uint)0x00000000) /* IDMA1 has high req priority */
803#define RCCR_DR1QP_MED ((uint)0x00010000) /* IDMA1 has medium req priority */
804#define RCCR_DR1QP_LOW ((uint)0x00020000) /* IDMA1 has low req priority */
805#define RCCR_DR2QP_MASK ((uint)0x00000030) /* mask for IDMA2 req priority */
806#define RCCR_DR2QP_HIGH ((uint)0x00000000) /* IDMA2 has high req priority */
807#define RCCR_DR2QP_MED ((uint)0x00000010) /* IDMA2 has medium req priority */
808#define RCCR_DR2QP_LOW ((uint)0x00000020) /* IDMA2 has low req priority */
809#define RCCR_DR3QP_MASK ((uint)0x00000003) /* mask for IDMA3 req priority */
810#define RCCR_DR3QP_HIGH ((uint)0x00000000) /* IDMA3 has high req priority */
811#define RCCR_DR3QP_MED ((uint)0x00000001) /* IDMA3 has medium req priority */
812#define RCCR_DR3QP_LOW ((uint)0x00000002) /* IDMA3 has low req priority */
813#define RCCR_EIE ((uint)0x00080000) /* external interrupt enable */
814#define RCCR_SCD ((uint)0x00040000) /* scheduler configuration */
815#define RCCR_ERAM_MASK ((uint)0x0000e000) /* mask for enable RAM microcode */
816#define RCCR_ERAM_0KB ((uint)0x00000000) /* use 0KB of dpram for microcode */
817#define RCCR_ERAM_2KB ((uint)0x00002000) /* use 2KB of dpram for microcode */
818#define RCCR_ERAM_4KB ((uint)0x00004000) /* use 4KB of dpram for microcode */
819#define RCCR_ERAM_6KB ((uint)0x00006000) /* use 6KB of dpram for microcode */
820#define RCCR_ERAM_8KB ((uint)0x00008000) /* use 8KB of dpram for microcode */
821#define RCCR_ERAM_10KB ((uint)0x0000a000) /* use 10KB of dpram for microcode */
822#define RCCR_ERAM_12KB ((uint)0x0000c000) /* use 12KB of dpram for microcode */
823#define RCCR_EDM0 ((uint)0x00000800) /* DREQ0 edge detect mode */
824#define RCCR_EDM1 ((uint)0x00000400) /* DREQ1 edge detect mode */
825#define RCCR_EDM2 ((uint)0x00000200) /* DREQ2 edge detect mode */
826#define RCCR_EDM3 ((uint)0x00000100) /* DREQ3 edge detect mode */
827#define RCCR_DEM01 ((uint)0x00000008) /* DONE0/DONE1 edge detect mode */
828#define RCCR_DEM23 ((uint)0x00000004) /* DONE2/DONE3 edge detect mode */
829
830/*-----------------------------------------------------------------------
831 * CMXFCR - CMX FCC Clock Route Register
832 */
833#define CMXFCR_FC1 0x40000000 /* FCC1 connection */
834#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
835#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
836#define CMXFCR_FC2 0x00400000 /* FCC2 connection */
837#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
838#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
839#define CMXFCR_FC3 0x00004000 /* FCC3 connection */
840#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
841#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
842
843#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
844#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
845#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
846#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
847#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
848#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
849#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
850#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
851
852#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
853#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
854#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
855#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
856#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
857#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
858#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
859#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
860
861#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
862#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
863#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
864#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
865#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
866#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
867#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
868#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
869
870#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
871#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
872#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
873#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
874#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
875#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
876#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
877#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
878
879#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
880#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
881#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
882#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
883#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
884#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
885#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
886#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
887
888#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
889#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
890#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
891#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
892#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
893#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
894#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
895#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
896
897/*-----------------------------------------------------------------------
898 * CMXSCR - CMX SCC Clock Route Register
899 */
900#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
901#define CMXSCR_SC1 0x40000000 /* SCC1 connection */
902#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
903#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
904#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
905#define CMXSCR_SC2 0x00400000 /* SCC2 connection */
906#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
907#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
908#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
909#define CMXSCR_SC3 0x00004000 /* SCC3 connection */
910#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
911#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
912#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
913#define CMXSCR_SC4 0x00000040 /* SCC4 connection */
914#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
915#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
916
917#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
918#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
919#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
920#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
921#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
922#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
923#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
924#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
925
926#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
927#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
928#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
929#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
930#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
931#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
932#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
933#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
934
935#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
936#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
937#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
938#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
939#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
940#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
941#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
942#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
943
944#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
945#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
946#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
947#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
948#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
949#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
950#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
951#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
952
953#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
954#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
955#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
956#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
957#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
958#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
959#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
960#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
961
962#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
963#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
964#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
965#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
966#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
967#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
968#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
969#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
970
971#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
972#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
973#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
974#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
975#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
976#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
977#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
978#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
979
980#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
981#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
982#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
983#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
984#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
985#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
986#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
987#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
988
989/*-----------------------------------------------------------------------
990 * SIUMCR - SIU Module Configuration Register 4-31
991 */
992#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
993#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
994#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
995#define SIUMCR_CDIS 0x10000000 /* Core Disable */
996#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
997#define SIUMCR_DPPC01 0x04000000 /* - " - */
998#define SIUMCR_DPPC10 0x08000000 /* - " - */
999#define SIUMCR_DPPC11 0x0c000000 /* - " - */
1000#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
1001#define SIUMCR_L2CPC01 0x01000000 /* - " - */
1002#define SIUMCR_L2CPC10 0x02000000 /* - " - */
1003#define SIUMCR_L2CPC11 0x03000000 /* - " - */
1004#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
1005#define SIUMCR_LBPC01 0x00400000 /* - " - */
1006#define SIUMCR_LBPC10 0x00800000 /* - " - */
1007#define SIUMCR_LBPC11 0x00c00000 /* - " - */
1008#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
1009#define SIUMCR_APPC01 0x00100000 /* - " - */
1010#define SIUMCR_APPC10 0x00200000 /* - " - */
1011#define SIUMCR_APPC11 0x00300000 /* - " - */
1012#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
1013#define SIUMCR_CS10PC01 0x00040000 /* - " - */
1014#define SIUMCR_CS10PC10 0x00080000 /* - " - */
1015#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
1016#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
1017#define SIUMCR_BCTLC01 0x00010000 /* - " - */
1018#define SIUMCR_BCTLC10 0x00020000 /* - " - */
1019#define SIUMCR_BCTLC11 0x00030000 /* - " - */
1020#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
1021#define SIUMCR_MMR01 0x00004000 /* - " - */
1022#define SIUMCR_MMR10 0x00008000 /* - " - */
1023#define SIUMCR_MMR11 0x0000c000 /* - " - */
1024#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
1025
1026/*-----------------------------------------------------------------------
1027 * SCCR - System Clock Control Register 9-8
1028*/
1029#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
1030#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
1031#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
1032#define SCCR_PCIDF_SHIFT 3
1033
1034#ifndef CPM_IMMR_OFFSET
1035#define CPM_IMMR_OFFSET 0x101a8
1036#endif
1037
1038#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
1039
1040/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
1041 * in order to use clock-computing stuff below for the FCC x
1042 */
1043
1044/* Automatically generates register configurations */
1045#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
1046
1047#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
1048#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
1049#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
1050#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
1051#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
1052#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
1053
1054#define PC_F1RXCLK PC_CLK(F1_RXCLK)
1055#define PC_F1TXCLK PC_CLK(F1_TXCLK)
1056#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
1057#define CMX1_CLK_MASK ((uint)0xff000000)
1058
1059#define PC_F2RXCLK PC_CLK(F2_RXCLK)
1060#define PC_F2TXCLK PC_CLK(F2_TXCLK)
1061#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
1062#define CMX2_CLK_MASK ((uint)0x00ff0000)
1063
1064#define PC_F3RXCLK PC_CLK(F3_RXCLK)
1065#define PC_F3TXCLK PC_CLK(F3_TXCLK)
1066#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
1067#define CMX3_CLK_MASK ((uint)0x0000ff00)
1068
1069#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
1070#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
1071
1072#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
1073
1074/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
1075 * but there is little variation among the choices.
1076 */
1077#define PA1_COL 0x00000001U
1078#define PA1_CRS 0x00000002U
1079#define PA1_TXER 0x00000004U
1080#define PA1_TXEN 0x00000008U
1081#define PA1_RXDV 0x00000010U
1082#define PA1_RXER 0x00000020U
1083#define PA1_TXDAT 0x00003c00U
1084#define PA1_RXDAT 0x0003c000U
1085#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
1086#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
1087 PA1_RXDV | PA1_RXER)
1088#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
1089#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
1090
1091
1092/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
1093 * but there is little variation among the choices.
1094 */
1095#define PB2_TXER 0x00000001U
1096#define PB2_RXDV 0x00000002U
1097#define PB2_TXEN 0x00000004U
1098#define PB2_RXER 0x00000008U
1099#define PB2_COL 0x00000010U
1100#define PB2_CRS 0x00000020U
1101#define PB2_TXDAT 0x000003c0U
1102#define PB2_RXDAT 0x00003c00U
1103#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
1104 PB2_RXER | PB2_RXDV | PB2_TXER)
1105#define PB2_PSORB1 (PB2_TXEN)
1106#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
1107#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
1108
1109
1110/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
1111 * but there is little variation among the choices.
1112 */
1113#define PB3_RXDV 0x00004000U
1114#define PB3_RXER 0x00008000U
1115#define PB3_TXER 0x00010000U
1116#define PB3_TXEN 0x00020000U
1117#define PB3_COL 0x00040000U
1118#define PB3_CRS 0x00080000U
1119#define PB3_TXDAT 0x0f000000U
1120#define PC3_TXDAT 0x00000010U
1121#define PB3_RXDAT 0x00f00000U
1122#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
1123 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
1124#define PB3_PSORB1 0
1125#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
1126#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
1127#define PC3_DIRC1 (PC3_TXDAT)
1128
1129/* Handy macro to specify mem for FCCs*/
1130#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
1131#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
1132#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
1133#define FCC3_MEM_OFFSET FCC_MEM_OFFSET(2)
1134
1135/* Clocks and GRG's */
1136
1137enum cpm_clk_dir {
1138 CPM_CLK_RX,
1139 CPM_CLK_TX,
1140 CPM_CLK_RTX
1141};
1142
1143enum cpm_clk_target {
1144 CPM_CLK_SCC1,
1145 CPM_CLK_SCC2,
1146 CPM_CLK_SCC3,
1147 CPM_CLK_SCC4,
1148 CPM_CLK_FCC1,
1149 CPM_CLK_FCC2,
2652d4ec
SW		 1150 CPM_CLK_FCC3,
1151 CPM_CLK_SMC1,
1152 CPM_CLK_SMC2,
33d71d26
KG		 1153};
1154
1155enum cpm_clk {
1156 CPM_CLK_NONE = 0,
1157 CPM_BRG1, /* Baud Rate Generator 1 */
1158 CPM_BRG2, /* Baud Rate Generator 2 */
1159 CPM_BRG3, /* Baud Rate Generator 3 */
1160 CPM_BRG4, /* Baud Rate Generator 4 */
1161 CPM_BRG5, /* Baud Rate Generator 5 */
1162 CPM_BRG6, /* Baud Rate Generator 6 */
1163 CPM_BRG7, /* Baud Rate Generator 7 */
1164 CPM_BRG8, /* Baud Rate Generator 8 */
1165 CPM_CLK1, /* Clock 1 */
1166 CPM_CLK2, /* Clock 2 */
1167 CPM_CLK3, /* Clock 3 */
1168 CPM_CLK4, /* Clock 4 */
1169 CPM_CLK5, /* Clock 5 */
1170 CPM_CLK6, /* Clock 6 */
1171 CPM_CLK7, /* Clock 7 */
1172 CPM_CLK8, /* Clock 8 */
1173 CPM_CLK9, /* Clock 9 */
1174 CPM_CLK10, /* Clock 10 */
1175 CPM_CLK11, /* Clock 11 */
1176 CPM_CLK12, /* Clock 12 */
1177 CPM_CLK13, /* Clock 13 */
1178 CPM_CLK14, /* Clock 14 */
1179 CPM_CLK15, /* Clock 15 */
1180 CPM_CLK16, /* Clock 16 */
1181 CPM_CLK17, /* Clock 17 */
1182 CPM_CLK18, /* Clock 18 */
1183 CPM_CLK19, /* Clock 19 */
1184 CPM_CLK20, /* Clock 20 */
1185 CPM_CLK_DUMMY
1186};
1187
1188extern int cpm2_clk_setup(enum cpm_clk_target target, int clock, int mode);
2652d4ec 1189extern int cpm2_smc_clk_setup(enum cpm_clk_target target, int clock);
33d71d26 1190
7f21f529
SW		 1191#define CPM_PIN_INPUT 0
1192#define CPM_PIN_OUTPUT 1
1193#define CPM_PIN_PRIMARY 0
1194#define CPM_PIN_SECONDARY 2
1195#define CPM_PIN_GPIO 4
1196#define CPM_PIN_OPENDRAIN 8
1197
1198void cpm2_set_pin(int port, int pin, int flags);
1199
33d71d26
KG		 1200#endif /* __CPM2__ */
1201#endif /* __KERNEL__ */
Linux 6.x block layer and io_uring tree(s)