[linux-2.6-block.git] / include / asm-parisc / bitops.h

#ifndef _PARISC_BITOPS_H
#define _PARISC_BITOPS_H

#include <linux/compiler.h>
#include <asm/types.h>		/* for BITS_PER_LONG/SHIFT_PER_LONG */
#include <asm/byteorder.h>
#include <asm/atomic.h>

/*
 * HP-PARISC specific bit operations
 * for a detailed description of the functions please refer
 * to include/asm-i386/bitops.h or kerneldoc
 */

#define CHOP_SHIFTCOUNT(x) (((unsigned long) (x)) & (BITS_PER_LONG - 1))


#define smp_mb__before_clear_bit()      smp_mb()
#define smp_mb__after_clear_bit()       smp_mb()

/* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion
 * on use of volatile and __*_bit() (set/clear/change):
 *	*_bit() want use of volatile.
 *	__*_bit() are "relaxed" and don't use spinlock or volatile.
 */

static __inline__ void set_bit(int nr, volatile unsigned long * addr)
{
	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
	unsigned long flags;

	addr += (nr >> SHIFT_PER_LONG);
	_atomic_spin_lock_irqsave(addr, flags);
	*addr |= mask;
	_atomic_spin_unlock_irqrestore(addr, flags);
}

static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
{
	unsigned long mask = ~(1UL << CHOP_SHIFTCOUNT(nr));
	unsigned long flags;

	addr += (nr >> SHIFT_PER_LONG);
	_atomic_spin_lock_irqsave(addr, flags);
	*addr &= mask;
	_atomic_spin_unlock_irqrestore(addr, flags);
}

static __inline__ void change_bit(int nr, volatile unsigned long * addr)
{
	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
	unsigned long flags;

	addr += (nr >> SHIFT_PER_LONG);
	_atomic_spin_lock_irqsave(addr, flags);
	*addr ^= mask;
	_atomic_spin_unlock_irqrestore(addr, flags);
}

static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
{
	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
	unsigned long old;
	unsigned long flags;
	int set;

	addr += (nr >> SHIFT_PER_LONG);
	_atomic_spin_lock_irqsave(addr, flags);
	old = *addr;
	set = (old & mask) ? 1 : 0;
	if (!set)
		*addr = old | mask;
	_atomic_spin_unlock_irqrestore(addr, flags);

	return set;
}

static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
{
	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
	unsigned long old;
	unsigned long flags;
	int set;

	addr += (nr >> SHIFT_PER_LONG);
	_atomic_spin_lock_irqsave(addr, flags);
	old = *addr;
	set = (old & mask) ? 1 : 0;
	if (set)
		*addr = old & ~mask;
	_atomic_spin_unlock_irqrestore(addr, flags);

	return set;
}

static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
{
	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
	unsigned long oldbit;
	unsigned long flags;

	addr += (nr >> SHIFT_PER_LONG);
	_atomic_spin_lock_irqsave(addr, flags);
	oldbit = *addr;
	*addr = oldbit ^ mask;
	_atomic_spin_unlock_irqrestore(addr, flags);

	return (oldbit & mask) ? 1 : 0;
}

#include <asm-generic/bitops/non-atomic.h>

#ifdef __KERNEL__

/**
 * __ffs - find first bit in word. returns 0 to "BITS_PER_LONG-1".
 * @word: The word to search
 *
 * __ffs() return is undefined if no bit is set.
 *
 * 32-bit fast __ffs by LaMont Jones "lamont At hp com".
 * 64-bit enhancement by Grant Grundler "grundler At parisc-linux org".
 * (with help from willy/jejb to get the semantics right)
 *
 * This algorithm avoids branches by making use of nullification.
 * One side effect of "extr" instructions is it sets PSW[N] bit.
 * How PSW[N] (nullify next insn) gets set is determined by the 
 * "condition" field (eg "<>" or "TR" below) in the extr* insn.
 * Only the 1st and one of either the 2cd or 3rd insn will get executed.
 * Each set of 3 insn will get executed in 2 cycles on PA8x00 vs 16 or so
 * cycles for each mispredicted branch.
 */

static __inline__ unsigned long __ffs(unsigned long x)
{
	unsigned long ret;

	__asm__(
#ifdef CONFIG_64BIT
		" ldi       63,%1\n"
		" extrd,u,*<>  %0,63,32,%%r0\n"
		" extrd,u,*TR  %0,31,32,%0\n"	/* move top 32-bits down */
		" addi    -32,%1,%1\n"
#else
		" ldi       31,%1\n"
#endif
		" extru,<>  %0,31,16,%%r0\n"
		" extru,TR  %0,15,16,%0\n"	/* xxxx0000 -> 0000xxxx */
		" addi    -16,%1,%1\n"
		" extru,<>  %0,31,8,%%r0\n"
		" extru,TR  %0,23,8,%0\n"	/* 0000xx00 -> 000000xx */
		" addi    -8,%1,%1\n"
		" extru,<>  %0,31,4,%%r0\n"
		" extru,TR  %0,27,4,%0\n"	/* 000000x0 -> 0000000x */
		" addi    -4,%1,%1\n"
		" extru,<>  %0,31,2,%%r0\n"
		" extru,TR  %0,29,2,%0\n"	/* 0000000y, 1100b -> 0011b */
		" addi    -2,%1,%1\n"
		" extru,=  %0,31,1,%%r0\n"	/* check last bit */
		" addi    -1,%1,%1\n"
			: "+r" (x), "=r" (ret) );
	return ret;
}

#include <asm-generic/bitops/ffz.h>

/*
 * ffs: find first bit set. returns 1 to BITS_PER_LONG or 0 (if none set)
 * This is defined the same way as the libc and compiler builtin
 * ffs routines, therefore differs in spirit from the above ffz (man ffs).
 */
static __inline__ int ffs(int x)
{
	return x ? (__ffs((unsigned long)x) + 1) : 0;
}

/*
 * fls: find last (most significant) bit set.
 * fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
 */

static __inline__ int fls(int x)
{
	int ret;
	if (!x)
		return 0;

	__asm__(
	"	ldi		1,%1\n"
	"	extru,<>	%0,15,16,%%r0\n"
	"	zdep,TR		%0,15,16,%0\n"		/* xxxx0000 */
	"	addi		16,%1,%1\n"
	"	extru,<>	%0,7,8,%%r0\n"
	"	zdep,TR		%0,23,24,%0\n"		/* xx000000 */
	"	addi		8,%1,%1\n"
	"	extru,<>	%0,3,4,%%r0\n"
	"	zdep,TR		%0,27,28,%0\n"		/* x0000000 */
	"	addi		4,%1,%1\n"
	"	extru,<>	%0,1,2,%%r0\n"
	"	zdep,TR		%0,29,30,%0\n"		/* y0000000 (y&3 = 0) */
	"	addi		2,%1,%1\n"
	"	extru,=		%0,0,1,%%r0\n"
	"	addi		1,%1,%1\n"		/* if y & 8, add 1 */
		: "+r" (x), "=r" (ret) );

	return ret;
}

#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>
#include <asm-generic/bitops/sched.h>

#endif /* __KERNEL__ */

#include <asm-generic/bitops/find.h>

#ifdef __KERNEL__

#include <asm-generic/bitops/ext2-non-atomic.h>

/* '3' is bits per byte */
#define LE_BYTE_ADDR ((sizeof(unsigned long) - 1) << 3)

#define ext2_set_bit_atomic(l,nr,addr) \
		test_and_set_bit((nr)   ^ LE_BYTE_ADDR, (unsigned long *)addr)
#define ext2_clear_bit_atomic(l,nr,addr) \
		test_and_clear_bit( (nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)

#endif	/* __KERNEL__ */

#include <asm-generic/bitops/minix-le.h>

#endif /* _PARISC_BITOPS_H */
Commit	Line	Data
1da177e4 LT	1	#ifndef _PARISC_BITOPS_H
	2	#define _PARISC_BITOPS_H
	3
	4	#include <linux/compiler.h>
a366064c	5	#include <asm/types.h> /* for BITS_PER_LONG/SHIFT_PER_LONG */
1da177e4 LT	6	#include <asm/byteorder.h>
	7	#include <asm/atomic.h>
	8
	9	/*
	10	* HP-PARISC specific bit operations
	11	* for a detailed description of the functions please refer
	12	* to include/asm-i386/bitops.h or kerneldoc
	13	*/
	14
a366064c	15	#define CHOP_SHIFTCOUNT(x) (((unsigned long) (x)) & (BITS_PER_LONG - 1))
1da177e4 LT	16
	17
	18	#define smp_mb__before_clear_bit() smp_mb()
	19	#define smp_mb__after_clear_bit() smp_mb()
	20
a366064c GG	21	/* See http://marc.theaimsgroup.com/?t=108826637900003 for discussion
	22	* on use of volatile and __*_bit() (set/clear/change):
	23	* *_bit() want use of volatile.
	24	* __*_bit() are "relaxed" and don't use spinlock or volatile.
	25	*/
	26
	27	static __inline__ void set_bit(int nr, volatile unsigned long * addr)
1da177e4	28	{
a366064c	29	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
1da177e4 LT	30	unsigned long flags;
	31
	32	addr += (nr >> SHIFT_PER_LONG);
1da177e4 LT	33	_atomic_spin_lock_irqsave(addr, flags);
	34	*addr \|= mask;
	35	_atomic_spin_unlock_irqrestore(addr, flags);
	36	}
	37
a366064c	38	static __inline__ void clear_bit(int nr, volatile unsigned long * addr)
1da177e4	39	{
a366064c	40	unsigned long mask = ~(1UL << CHOP_SHIFTCOUNT(nr));
1da177e4 LT	41	unsigned long flags;
	42
	43	addr += (nr >> SHIFT_PER_LONG);
1da177e4	44	_atomic_spin_lock_irqsave(addr, flags);
a366064c	45	*addr &= mask;
1da177e4 LT	46	_atomic_spin_unlock_irqrestore(addr, flags);
	47	}
	48
a366064c	49	static __inline__ void change_bit(int nr, volatile unsigned long * addr)
1da177e4	50	{
a366064c	51	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
1da177e4 LT	52	unsigned long flags;
	53
	54	addr += (nr >> SHIFT_PER_LONG);
1da177e4 LT	55	_atomic_spin_lock_irqsave(addr, flags);
	56	*addr ^= mask;
	57	_atomic_spin_unlock_irqrestore(addr, flags);
	58	}
	59
a366064c	60	static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr)
1da177e4	61	{
a366064c	62	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
af5917f0	63	unsigned long old;
1da177e4	64	unsigned long flags;
af5917f0	65	int set;
1da177e4 LT	66
1da177e4 LT	67	addr += (nr >> SHIFT_PER_LONG);
1da177e4	68	_atomic_spin_lock_irqsave(addr, flags);
af5917f0 MW	69	old = *addr;
	70	set = (old & mask) ? 1 : 0;
	71	if (!set)
	72	*addr = old \| mask;
1da177e4 LT	73	_atomic_spin_unlock_irqrestore(addr, flags);
1da177e4 LT	74
af5917f0	75	return set;
1da177e4 LT	76	}
1da177e4 LT	77
a366064c	78	static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr)
1da177e4	79	{
a366064c	80	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
af5917f0	81	unsigned long old;
1da177e4	82	unsigned long flags;
af5917f0	83	int set;
1da177e4 LT	84
1da177e4 LT	85	addr += (nr >> SHIFT_PER_LONG);
1da177e4	86	_atomic_spin_lock_irqsave(addr, flags);
af5917f0 MW	87	old = *addr;
	88	set = (old & mask) ? 1 : 0;
	89	if (set)
	90	*addr = old & ~mask;
1da177e4 LT	91	_atomic_spin_unlock_irqrestore(addr, flags);
1da177e4 LT	92
af5917f0	93	return set;
1da177e4 LT	94	}
1da177e4 LT	95
a366064c	96	static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr)
1da177e4	97	{
a366064c GG	98	unsigned long mask = 1UL << CHOP_SHIFTCOUNT(nr);
a366064c GG	99	unsigned long oldbit;
1da177e4 LT	100	unsigned long flags;
	101
	102	addr += (nr >> SHIFT_PER_LONG);
1da177e4	103	_atomic_spin_lock_irqsave(addr, flags);
a366064c GG	104	oldbit = *addr;
a366064c GG	105	*addr = oldbit ^ mask;
1da177e4 LT	106	_atomic_spin_unlock_irqrestore(addr, flags);
1da177e4 LT	107
a366064c	108	return (oldbit & mask) ? 1 : 0;
1da177e4 LT	109	}
1da177e4 LT	110
59e18a2e	111	#include <asm-generic/bitops/non-atomic.h>
1da177e4 LT	112
	113	#ifdef __KERNEL__
	114
	115	/**
	116	* __ffs - find first bit in word. returns 0 to "BITS_PER_LONG-1".
	117	* @word: The word to search
	118	*
	119	* __ffs() return is undefined if no bit is set.
	120	*
	121	* 32-bit fast __ffs by LaMont Jones "lamont At hp com".
	122	* 64-bit enhancement by Grant Grundler "grundler At parisc-linux org".
	123	* (with help from willy/jejb to get the semantics right)
	124	*
	125	* This algorithm avoids branches by making use of nullification.
	126	* One side effect of "extr" instructions is it sets PSW[N] bit.
	127	* How PSW[N] (nullify next insn) gets set is determined by the
	128	* "condition" field (eg "<>" or "TR" below) in the extr* insn.
	129	* Only the 1st and one of either the 2cd or 3rd insn will get executed.
	130	* Each set of 3 insn will get executed in 2 cycles on PA8x00 vs 16 or so
	131	* cycles for each mispredicted branch.
	132	*/
	133
	134	static __inline__ unsigned long __ffs(unsigned long x)
	135	{
	136	unsigned long ret;
	137
	138	__asm__(
513e7ecd	139	#ifdef CONFIG_64BIT
1da177e4 LT	140	" ldi 63,%1\n"
	141	" extrd,u,*<> %0,63,32,%%r0\n"
	142	" extrd,u,TR %0,31,32,%0\n" / move top 32-bits down */
	143	" addi -32,%1,%1\n"
	144	#else
	145	" ldi 31,%1\n"
	146	#endif
	147	" extru,<> %0,31,16,%%r0\n"
	148	" extru,TR %0,15,16,%0\n" /* xxxx0000 -> 0000xxxx */
	149	" addi -16,%1,%1\n"
	150	" extru,<> %0,31,8,%%r0\n"
	151	" extru,TR %0,23,8,%0\n" /* 0000xx00 -> 000000xx */
	152	" addi -8,%1,%1\n"
	153	" extru,<> %0,31,4,%%r0\n"
	154	" extru,TR %0,27,4,%0\n" /* 000000x0 -> 0000000x */
	155	" addi -4,%1,%1\n"
	156	" extru,<> %0,31,2,%%r0\n"
	157	" extru,TR %0,29,2,%0\n" /* 0000000y, 1100b -> 0011b */
	158	" addi -2,%1,%1\n"
	159	" extru,= %0,31,1,%%r0\n" /* check last bit */
	160	" addi -1,%1,%1\n"
	161	: "+r" (x), "=r" (ret) );
	162	return ret;
	163	}
	164
59e18a2e	165	#include <asm-generic/bitops/ffz.h>
1da177e4 LT	166
	167	/*
	168	* ffs: find first bit set. returns 1 to BITS_PER_LONG or 0 (if none set)
	169	* This is defined the same way as the libc and compiler builtin
	170	* ffs routines, therefore differs in spirit from the above ffz (man ffs).
	171	*/
	172	static __inline__ int ffs(int x)
	173	{
	174	return x ? (__ffs((unsigned long)x) + 1) : 0;
	175	}
	176
	177	/*
	178	* fls: find last (most significant) bit set.
	179	* fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
	180	*/
	181
	182	static __inline__ int fls(int x)
	183	{
	184	int ret;
	185	if (!x)
	186	return 0;
	187
	188	__asm__(
	189	" ldi 1,%1\n"
	190	" extru,<> %0,15,16,%%r0\n"
	191	" zdep,TR %0,15,16,%0\n" /* xxxx0000 */
	192	" addi 16,%1,%1\n"
	193	" extru,<> %0,7,8,%%r0\n"
	194	" zdep,TR %0,23,24,%0\n" /* xx000000 */
	195	" addi 8,%1,%1\n"
	196	" extru,<> %0,3,4,%%r0\n"
	197	" zdep,TR %0,27,28,%0\n" /* x0000000 */
	198	" addi 4,%1,%1\n"
	199	" extru,<> %0,1,2,%%r0\n"
	200	" zdep,TR %0,29,30,%0\n" /* y0000000 (y&3 = 0) */
	201	" addi 2,%1,%1\n"
	202	" extru,= %0,0,1,%%r0\n"
	203	" addi 1,%1,%1\n" /* if y & 8, add 1 */
	204	: "+r" (x), "=r" (ret) );
	205
	206	return ret;
	207	}
	208
59e18a2e AM	209	#include <asm-generic/bitops/fls64.h>
59e18a2e AM	210	#include <asm-generic/bitops/hweight.h>
26333576	211	#include <asm-generic/bitops/lock.h>
59e18a2e	212	#include <asm-generic/bitops/sched.h>
1da177e4 LT	213
	214	#endif /* __KERNEL__ */
	215
59e18a2e	216	#include <asm-generic/bitops/find.h>
1da177e4 LT	217
1da177e4 LT	218	#ifdef __KERNEL__
59e18a2e AM	219
59e18a2e AM	220	#include <asm-generic/bitops/ext2-non-atomic.h>
1da177e4	221
a366064c GG	222	/* '3' is bits per byte */
a366064c GG	223	#define LE_BYTE_ADDR ((sizeof(unsigned long) - 1) << 3)
1da177e4	224
a366064c GG	225	#define ext2_set_bit_atomic(l,nr,addr) \
	226	test_and_set_bit((nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
	227	#define ext2_clear_bit_atomic(l,nr,addr) \
	228	test_and_clear_bit( (nr) ^ LE_BYTE_ADDR, (unsigned long *)addr)
	229
	230	#endif /* __KERNEL__ */
1da177e4	231
59e18a2e	232	#include <asm-generic/bitops/minix-le.h>
1da177e4 LT	233
1da177e4 LT	234	#endif /* _PARISC_BITOPS_H */