[linux-2.6-block.git] / include / asm-mips / smtc.h

#ifndef _ASM_SMTC_MT_H
#define _ASM_SMTC_MT_H

/*
 * Definitions for SMTC multitasking on MIPS MT cores
 */

#include <asm/mips_mt.h>

/*
 * System-wide SMTC status information
 */

extern unsigned int smtc_status;

#define SMTC_TLB_SHARED	0x00000001
#define SMTC_MTC_ACTIVE	0x00000002

/*
 * TLB/ASID Management information
 */

#define MAX_SMTC_TLBS 2
#define MAX_SMTC_ASIDS 256
#if NR_CPUS <= 8
typedef char asiduse;
#else
#if NR_CPUS <= 16
typedef short asiduse;
#else
typedef long asiduse;
#endif
#endif

extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];

struct mm_struct;
struct task_struct;

void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu);

void smtc_flush_tlb_asid(unsigned long asid);
extern int mipsmt_build_cpu_map(int startslot);
extern void mipsmt_prepare_cpus(void);
extern void smtc_smp_finish(void);
extern void smtc_boot_secondary(int cpu, struct task_struct *t);
extern void smtc_cpus_done(void);

/*
 * Sharing the TLB between multiple VPEs means that the
 * "random" index selection function is not allowed to
 * select the current value of the Index register. To
 * avoid additional TLB pressure, the Index registers
 * are "parked" with an non-Valid value.
 */

#define PARKED_INDEX	((unsigned int)0x80000000)

/*
 * Define low-level interrupt mask for IPIs, if necessary.
 * By default, use SW interrupt 1, which requires no external
 * hardware support, but which works only for single-core
 * MIPS MT systems.
 */
#ifndef MIPS_CPU_IPI_IRQ
#define MIPS_CPU_IPI_IRQ 1
#endif

#endif /*  _ASM_SMTC_MT_H */
Commit	Line	Data
41c594ab RB	1	#ifndef _ASM_SMTC_MT_H
	2	#define _ASM_SMTC_MT_H
	3
	4	/*
	5	* Definitions for SMTC multitasking on MIPS MT cores
	6	*/
	7
	8	#include <asm/mips_mt.h>
	9
	10	/*
	11	* System-wide SMTC status information
	12	*/
	13
	14	extern unsigned int smtc_status;
	15
	16	#define SMTC_TLB_SHARED 0x00000001
	17	#define SMTC_MTC_ACTIVE 0x00000002
	18
	19	/*
	20	* TLB/ASID Management information
	21	*/
	22
	23	#define MAX_SMTC_TLBS 2
	24	#define MAX_SMTC_ASIDS 256
	25	#if NR_CPUS <= 8
	26	typedef char asiduse;
	27	#else
	28	#if NR_CPUS <= 16
	29	typedef short asiduse;
	30	#else
	31	typedef long asiduse;
	32	#endif
	33	#endif
	34
	35	extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
	36
b3920590 RB	37	struct mm_struct;
	38	struct task_struct;
	39
41c594ab RB	40	void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu);
	41
	42	void smtc_flush_tlb_asid(unsigned long asid);
	43	extern int mipsmt_build_cpu_map(int startslot);
	44	extern void mipsmt_prepare_cpus(void);
	45	extern void smtc_smp_finish(void);
	46	extern void smtc_boot_secondary(int cpu, struct task_struct *t);
39b8d525	47	extern void smtc_cpus_done(void);
41c594ab RB	48
	49	/*
	50	* Sharing the TLB between multiple VPEs means that the
	51	* "random" index selection function is not allowed to
	52	* select the current value of the Index register. To
	53	* avoid additional TLB pressure, the Index registers
	54	* are "parked" with an non-Valid value.
	55	*/
	56
	57	#define PARKED_INDEX ((unsigned int)0x80000000)
	58
fe56b954 RB	59	/*
	60	* Define low-level interrupt mask for IPIs, if necessary.
	61	* By default, use SW interrupt 1, which requires no external
	62	* hardware support, but which works only for single-core
	63	* MIPS MT systems.
	64	*/
	65	#ifndef MIPS_CPU_IPI_IRQ
	66	#define MIPS_CPU_IPI_IRQ 1
	67	#endif
	68
41c594ab	69	#endif /* _ASM_SMTC_MT_H */