projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* ********************************************************************* |
| 2 | * SB1250 Board Support Package | |
| 42a3b4f2 | 3 | * |
| 1da177e4 | 4 | * SCD Constants and Macros File: sb1250_scd.h |
| 42a3b4f2 | 5 | * |
| 1da177e4 LT |
6 | * This module contains constants and macros useful for |
| 7 | * manipulating the System Control and Debug module on the 1250. | |
| 42a3b4f2 | 8 | * |
| 1da177e4 | 9 | * SB1250 specification level: User's manual 1/02/02 |
| 42a3b4f2 | 10 | * |
| 1da177e4 | 11 | * Author: Mitch Lichtenberg |
| 42a3b4f2 RB |
12 | * |
| 13 | ********************************************************************* | |
| 1da177e4 LT |
14 | * |
| 15 | * Copyright 2000,2001,2002,2003 | |
| 16 | * Broadcom Corporation. All rights reserved. | |
| 42a3b4f2 RB |
17 | * |
| 18 | * This program is free software; you can redistribute it and/or | |
| 19 | * modify it under the terms of the GNU General Public License as | |
| 20 | * published by the Free Software Foundation; either version 2 of | |
| 1da177e4 LT |
21 | * the License, or (at your option) any later version. |
| 22 | * | |
| 23 | * This program is distributed in the hope that it will be useful, | |
| 24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 26 | * GNU General Public License for more details. | |
| 27 | * | |
| 28 | * You should have received a copy of the GNU General Public License | |
| 29 | * along with this program; if not, write to the Free Software | |
| 42a3b4f2 | 30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 1da177e4 LT |
31 | * MA 02111-1307 USA |
| 32 | ********************************************************************* */ | |
| 33 | ||
| 34 | #ifndef _SB1250_SCD_H | |
| 35 | #define _SB1250_SCD_H | |
| 36 | ||
| 37 | #include "sb1250_defs.h" | |
| 38 | ||
| 39 | /* ********************************************************************* | |
| 40 | * System control/debug registers | |
| 41 | ********************************************************************* */ | |
| 42 | ||
| 43 | /* | |
| 44 | * System Revision Register (Table 4-1) | |
| 45 | */ | |
| 46 | ||
| 47 | #define M_SYS_RESERVED _SB_MAKEMASK(8,0) | |
| 48 | ||
| 49 | #define S_SYS_REVISION _SB_MAKE64(8) | |
| 50 | #define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION) | |
| 51 | #define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION) | |
| 52 | #define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION) | |
| 53 | ||
| 54 | #if SIBYTE_HDR_FEATURE_CHIP(1250) | |
| 55 | #define K_SYS_REVISION_BCM1250_PASS1 1 | |
| 56 | #define K_SYS_REVISION_BCM1250_PASS2 3 | |
| 57 | #define K_SYS_REVISION_BCM1250_A10 11 | |
| 58 | #define K_SYS_REVISION_BCM1250_PASS2_2 16 | |
| 59 | #define K_SYS_REVISION_BCM1250_B2 17 | |
| 60 | #define K_SYS_REVISION_BCM1250_PASS3 32 | |
| 61 | #define K_SYS_REVISION_BCM1250_C1 33 | |
| 62 | ||
| 63 | /* XXX: discourage people from using these constants. */ | |
| 64 | #define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1 | |
| 65 | #define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2 | |
| 66 | #define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2 | |
| 67 | #define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3 | |
| 68 | #endif /* 1250 */ | |
| 69 | ||
| 70 | #if SIBYTE_HDR_FEATURE_CHIP(112x) | |
| 71 | #define K_SYS_REVISION_BCM112x_A1 32 | |
| 72 | #define K_SYS_REVISION_BCM112x_A2 33 | |
| 73 | #endif /* 112x */ | |
| 74 | ||
| 75 | /* XXX: discourage people from using these constants. */ | |
| 76 | #define S_SYS_PART _SB_MAKE64(16) | |
| 77 | #define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART) | |
| 78 | #define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART) | |
| 79 | #define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART) | |
| 80 | ||
| 81 | /* XXX: discourage people from using these constants. */ | |
| 82 | #define K_SYS_PART_SB1250 0x1250 | |
| 83 | #define K_SYS_PART_BCM1120 0x1121 | |
| 84 | #define K_SYS_PART_BCM1125 0x1123 | |
| 85 | #define K_SYS_PART_BCM1125H 0x1124 | |
| 86 | ||
| 87 | /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */ | |
| 88 | #define S_SYS_SOC_TYPE _SB_MAKE64(16) | |
| 89 | #define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE) | |
| 90 | #define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE) | |
| 91 | #define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE) | |
| 92 | ||
| 93 | #define K_SYS_SOC_TYPE_BCM1250 0x0 | |
| 94 | #define K_SYS_SOC_TYPE_BCM1120 0x1 | |
| 95 | #define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */ | |
| 96 | #define K_SYS_SOC_TYPE_BCM1125 0x3 | |
| 97 | #define K_SYS_SOC_TYPE_BCM1125H 0x4 | |
| 98 | #define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */ | |
| 99 | ||
| 100 | /* | |
| 101 | * Calculate correct SOC type given a copy of system revision register. | |
| 102 | * | |
| 103 | * (For the assembler version, sysrev and dest may be the same register. | |
| 104 | * Also, it clobbers AT.) | |
| 105 | */ | |
| 106 | #ifdef __ASSEMBLER__ | |
| 107 | #define SYS_SOC_TYPE(dest, sysrev) \ | |
| 108 | .set push ; \ | |
| 109 | .set reorder ; \ | |
| 110 | dsrl dest, sysrev, S_SYS_SOC_TYPE ; \ | |
| 111 | andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \ | |
| 112 | beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \ | |
| 113 | beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \ | |
| 114 | b 992f ; \ | |
| 115 | 991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \ | |
| 116 | 992: \ | |
| 117 | .set pop | |
| 118 | #else | |
| 119 | #define SYS_SOC_TYPE(sysrev) \ | |
| 120 | ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \ | |
| 121 | || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \ | |
| 122 | ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev)) | |
| 123 | #endif | |
| 124 | ||
| 125 | #define S_SYS_WID _SB_MAKE64(32) | |
| 126 | #define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID) | |
| 127 | #define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID) | |
| 128 | #define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID) | |
| 129 | ||
| 130 | /* System Manufacturing Register | |
| 131 | * Register: SCD_SYSTEM_MANUF | |
| 132 | */ | |
| 42a3b4f2 | 133 | |
| 1da177e4 LT |
134 | /* Wafer ID: bits 31:0 */ |
| 135 | #define S_SYS_WAFERID1_200 _SB_MAKE64(0) | |
| 136 | #define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200) | |
| 137 | #define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200) | |
| 138 | #define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200) | |
| 42a3b4f2 | 139 | |
| 1da177e4 LT |
140 | #define S_SYS_BIN _SB_MAKE64(32) |
| 141 | #define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN) | |
| 142 | #define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN) | |
| 143 | #define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN) | |
| 42a3b4f2 | 144 | |
| 1da177e4 LT |
145 | /* Wafer ID: bits 39:36 */ |
| 146 | #define S_SYS_WAFERID2_200 _SB_MAKE64(36) | |
| 147 | #define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200) | |
| 148 | #define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200) | |
| 149 | #define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200) | |
| 42a3b4f2 | 150 | |
| 1da177e4 LT |
151 | /* Wafer ID: bits 39:0 */ |
| 152 | #define S_SYS_WAFERID_300 _SB_MAKE64(0) | |
| 153 | #define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300) | |
| 154 | #define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300) | |
| 155 | #define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300) | |
| 42a3b4f2 | 156 | |
| 1da177e4 LT |
157 | #define S_SYS_XPOS _SB_MAKE64(40) |
| 158 | #define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS) | |
| 159 | #define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS) | |
| 160 | #define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS) | |
| 42a3b4f2 | 161 | |
| 1da177e4 LT |
162 | #define S_SYS_YPOS _SB_MAKE64(46) |
| 163 | #define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS) | |
| 164 | #define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS) | |
| 165 | #define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS) | |
| 42a3b4f2 | 166 | |
| 1da177e4 LT |
167 | /* |
| 168 | * System Config Register (Table 4-2) | |
| 169 | * Register: SCD_SYSTEM_CFG | |
| 170 | */ | |
| 171 | ||
| 172 | #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3) | |
| 173 | #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4) | |
| 174 | #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5) | |
| 175 | #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6) | |
| 176 | ||
| 177 | #define S_SYS_PLL_DIV _SB_MAKE64(7) | |
| 178 | #define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV) | |
| 179 | #define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV) | |
| 180 | #define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV) | |
| 181 | ||
| 182 | #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12) | |
| 183 | #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13) | |
| 184 | #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14) | |
| 185 | #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15) | |
| 186 | #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) | |
| 187 | ||
| 188 | #define S_SYS_BOOT_MODE _SB_MAKE64(17) | |
| 189 | #define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE) | |
| 190 | #define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE) | |
| 191 | #define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE) | |
| 192 | #define K_SYS_BOOT_MODE_ROM32 0 | |
| 193 | #define K_SYS_BOOT_MODE_ROM8 1 | |
| 194 | #define K_SYS_BOOT_MODE_SMBUS_SMALL 2 | |
| 195 | #define K_SYS_BOOT_MODE_SMBUS_BIG 3 | |
| 196 | ||
| 197 | #define M_SYS_PCI_HOST _SB_MAKEMASK1(19) | |
| 198 | #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20) | |
| 199 | #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21) | |
| 200 | #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) | |
| 201 | #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23) | |
| 202 | #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24) | |
| 203 | #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25) | |
| 204 | ||
| 205 | #define S_SYS_CONFIG 26 | |
| 206 | #define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG) | |
| 207 | #define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG) | |
| 208 | #define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG) | |
| 209 | ||
| 210 | /* The following bits are writeable by JTAG only. */ | |
| 211 | ||
| 212 | #define M_SYS_CLKSTOP _SB_MAKEMASK1(32) | |
| 213 | #define M_SYS_CLKSTEP _SB_MAKEMASK1(33) | |
| 214 | ||
| 215 | #define S_SYS_CLKCOUNT 34 | |
| 216 | #define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT) | |
| 217 | #define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT) | |
| 218 | #define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT) | |
| 219 | ||
| 220 | #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42) | |
| 221 | ||
| 222 | #define S_SYS_PLL_IREF 43 | |
| 223 | #define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF) | |
| 224 | ||
| 225 | #define S_SYS_PLL_VCO 45 | |
| 226 | #define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO) | |
| 227 | ||
| 228 | #define S_SYS_PLL_VREG 47 | |
| 229 | #define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG) | |
| 230 | ||
| 231 | #define M_SYS_MEM_RESET _SB_MAKEMASK1(49) | |
| 232 | #define M_SYS_L2C_RESET _SB_MAKEMASK1(50) | |
| 233 | #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51) | |
| 234 | #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52) | |
| 235 | #define M_SYS_SCD_RESET _SB_MAKEMASK1(53) | |
| 236 | ||
| 237 | /* End of bits writable by JTAG only. */ | |
| 238 | ||
| 239 | #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54) | |
| 240 | #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55) | |
| 241 | ||
| 242 | #define M_SYS_UNICPU0 _SB_MAKEMASK1(56) | |
| 243 | #define M_SYS_UNICPU1 _SB_MAKEMASK1(57) | |
| 244 | ||
| 245 | #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58) | |
| 246 | #define M_SYS_EXT_RESET _SB_MAKEMASK1(59) | |
| 247 | #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60) | |
| 248 | ||
| 249 | #define M_SYS_MISR_MODE _SB_MAKEMASK1(61) | |
| 250 | #define M_SYS_MISR_RESET _SB_MAKEMASK1(62) | |
| 251 | ||
| 252 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
| 253 | #define M_SYS_SW_FLAG _SB_MAKEMASK1(63) | |
| 254 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
| 255 | ||
| 256 | ||
| 257 | /* | |
| 258 | * Mailbox Registers (Table 4-3) | |
| 259 | * Registers: SCD_MBOX_CPU_x | |
| 260 | */ | |
| 261 | ||
| 262 | #define S_MBOX_INT_3 0 | |
| 263 | #define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3) | |
| 264 | #define S_MBOX_INT_2 16 | |
| 265 | #define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2) | |
| 266 | #define S_MBOX_INT_1 32 | |
| 267 | #define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1) | |
| 268 | #define S_MBOX_INT_0 48 | |
| 269 | #define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0) | |
| 270 | ||
| 271 | /* | |
| 272 | * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10) | |
| 273 | * Registers: SCD_WDOG_INIT_CNT_x | |
| 274 | */ | |
| 275 | ||
| 276 | #define V_SCD_WDOG_FREQ 1000000 | |
| 277 | ||
| 278 | #define S_SCD_WDOG_INIT 0 | |
| 279 | #define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT) | |
| 280 | ||
| 281 | #define S_SCD_WDOG_CNT 0 | |
| 282 | #define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT) | |
| 283 | ||
| 284 | #define S_SCD_WDOG_ENABLE 0 | |
| 285 | #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE) | |
| 286 | ||
| 287 | #define S_SCD_WDOG_RESET_TYPE 2 | |
| 288 | #define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE) | |
| 289 | #define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE) | |
| 290 | #define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE) | |
| 291 | ||
| 292 | #define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ | |
| 293 | #define K_SCD_WDOG_RESET_SOFT 1 | |
| 294 | #define K_SCD_WDOG_RESET_CPU0 3 | |
| 295 | #define K_SCD_WDOG_RESET_CPU1 5 | |
| 296 | #define K_SCD_WDOG_RESET_BOTH_CPUS 7 | |
| 297 | ||
| 298 | /* This feature is present in 1250 C0 and later, but *not* in 112x A revs. */ | |
| 299 | #if SIBYTE_HDR_FEATURE(1250, PASS3) | |
| 300 | #define S_SCD_WDOG_HAS_RESET 8 | |
| 301 | #define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET) | |
| 302 | #endif | |
| 303 | ||
| 304 | ||
| 305 | /* | |
| 306 | * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13) | |
| 307 | */ | |
| 308 | ||
| 309 | #define V_SCD_TIMER_FREQ 1000000 | |
| 310 | ||
| 311 | #define S_SCD_TIMER_INIT 0 | |
| 312 | #define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT) | |
| 313 | #define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT) | |
| 314 | #define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT) | |
| 315 | ||
| 316 | #define S_SCD_TIMER_CNT 0 | |
| 317 | #define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT) | |
| 318 | #define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT) | |
| 319 | #define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT) | |
| 320 | ||
| 321 | #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0) | |
| 322 | #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1) | |
| 323 | #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE | |
| 324 | ||
| 325 | /* | |
| 326 | * System Performance Counters | |
| 327 | */ | |
| 328 | ||
| 329 | #define S_SPC_CFG_SRC0 0 | |
| 330 | #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0) | |
| 331 | #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0) | |
| 332 | #define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0) | |
| 333 | ||
| 334 | #define S_SPC_CFG_SRC1 8 | |
| 335 | #define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1) | |
| 336 | #define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1) | |
| 337 | #define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1) | |
| 338 | ||
| 339 | #define S_SPC_CFG_SRC2 16 | |
| 340 | #define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2) | |
| 341 | #define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2) | |
| 342 | #define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2) | |
| 343 | ||
| 344 | #define S_SPC_CFG_SRC3 24 | |
| 345 | #define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3) | |
| 346 | #define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3) | |
| 347 | #define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3) | |
| 348 | ||
| 349 | #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32) | |
| 350 | #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33) | |
| 351 | ||
| 352 | ||
| 353 | /* | |
| 354 | * Bus Watcher | |
| 355 | */ | |
| 356 | ||
| 357 | #define S_SCD_BERR_TID 8 | |
| 358 | #define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID) | |
| 359 | #define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID) | |
| 360 | #define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID) | |
| 361 | ||
| 362 | #define S_SCD_BERR_RID 18 | |
| 363 | #define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID) | |
| 364 | #define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID) | |
| 365 | #define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID) | |
| 366 | ||
| 367 | #define S_SCD_BERR_DCODE 22 | |
| 368 | #define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE) | |
| 369 | #define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE) | |
| 370 | #define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE) | |
| 371 | ||
| 372 | #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30) | |
| 373 | ||
| 374 | ||
| 375 | #define S_SCD_L2ECC_CORR_D 0 | |
| 376 | #define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D) | |
| 377 | #define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D) | |
| 378 | #define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D) | |
| 379 | ||
| 380 | #define S_SCD_L2ECC_BAD_D 8 | |
| 381 | #define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D) | |
| 382 | #define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D) | |
| 383 | #define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D) | |
| 384 | ||
| 385 | #define S_SCD_L2ECC_CORR_T 16 | |
| 386 | #define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T) | |
| 387 | #define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T) | |
| 388 | #define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T) | |
| 389 | ||
| 390 | #define S_SCD_L2ECC_BAD_T 24 | |
| 391 | #define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T) | |
| 392 | #define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T) | |
| 393 | #define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T) | |
| 394 | ||
| 395 | #define S_SCD_MEM_ECC_CORR 0 | |
| 396 | #define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR) | |
| 397 | #define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR) | |
| 398 | #define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR) | |
| 399 | ||
| 400 | #define S_SCD_MEM_ECC_BAD 8 | |
| 401 | #define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD) | |
| 402 | #define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD) | |
| 403 | #define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD) | |
| 404 | ||
| 405 | #define S_SCD_MEM_BUSERR 16 | |
| 406 | #define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR) | |
| 407 | #define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR) | |
| 408 | #define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR) | |
| 409 | ||
| 410 | ||
| 411 | /* | |
| 412 | * Address Trap Registers | |
| 413 | */ | |
| 414 | ||
| 415 | #define M_ATRAP_INDEX _SB_MAKEMASK(4,0) | |
| 416 | #define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0) | |
| 417 | ||
| 418 | #define S_ATRAP_CFG_CNT 0 | |
| 419 | #define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT) | |
| 420 | #define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT) | |
| 421 | #define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT) | |
| 422 | ||
| 423 | #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) | |
| 424 | #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4) | |
| 425 | #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5) | |
| 426 | #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) | |
| 427 | #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) | |
| 428 | ||
| 429 | #define S_ATRAP_CFG_AGENTID 8 | |
| 430 | #define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID) | |
| 431 | #define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID) | |
| 432 | #define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID) | |
| 433 | ||
| 434 | #define K_BUS_AGENT_CPU0 0 | |
| 435 | #define K_BUS_AGENT_CPU1 1 | |
| 436 | #define K_BUS_AGENT_IOB0 2 | |
| 437 | #define K_BUS_AGENT_IOB1 3 | |
| 438 | #define K_BUS_AGENT_SCD 4 | |
| 439 | #define K_BUS_AGENT_RESERVED 5 | |
| 440 | #define K_BUS_AGENT_L2C 6 | |
| 441 | #define K_BUS_AGENT_MC 7 | |
| 442 | ||
| 443 | #define S_ATRAP_CFG_CATTR 12 | |
| 444 | #define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR) | |
| 445 | #define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR) | |
| 446 | #define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR) | |
| 447 | ||
| 448 | #define K_ATRAP_CFG_CATTR_IGNORE 0 | |
| 449 | #define K_ATRAP_CFG_CATTR_UNC 1 | |
| 450 | #define K_ATRAP_CFG_CATTR_CACHEABLE 2 | |
| 451 | #define K_ATRAP_CFG_CATTR_NONCOH 3 | |
| 452 | #define K_ATRAP_CFG_CATTR_COHERENT 4 | |
| 453 | #define K_ATRAP_CFG_CATTR_NOTUNC 5 | |
| 454 | #define K_ATRAP_CFG_CATTR_NOTNONCOH 6 | |
| 455 | #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7 | |
| 456 | ||
| 457 | /* | |
| 458 | * Trace Buffer Config register | |
| 459 | */ | |
| 460 | ||
| 461 | #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) | |
| 462 | #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) | |
| 463 | #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) | |
| 464 | #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) | |
| 465 | #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) | |
| 466 | #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) | |
| 467 | #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) | |
| 468 | #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) | |
| 469 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) | |
| 470 | #define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) | |
| 471 | #endif /* 1250 PASS2 || 112x PASS1 */ | |
| 472 | ||
| 473 | #define S_SCD_TRACE_CFG_CUR_ADDR 10 | |
| 474 | #define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR) | |
| 475 | #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR) | |
| 476 | #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR) | |
| 477 | ||
| 478 | /* | |
| 479 | * Trace Event registers | |
| 480 | */ | |
| 481 | ||
| 482 | #define S_SCD_TREVT_ADDR_MATCH 0 | |
| 483 | #define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH) | |
| 484 | #define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH) | |
| 485 | #define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH) | |
| 486 | ||
| 487 | #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4) | |
| 488 | #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5) | |
| 489 | #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6) | |
| 490 | #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7) | |
| 491 | #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9) | |
| 492 | #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10) | |
| 493 | #define M_SCD_TREVT_READ _SB_MAKEMASK1(11) | |
| 494 | ||
| 495 | #define S_SCD_TREVT_REQID 12 | |
| 496 | #define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID) | |
| 497 | #define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID) | |
| 498 | #define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID) | |
| 499 | ||
| 500 | #define S_SCD_TREVT_RESPID 16 | |
| 501 | #define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID) | |
| 502 | #define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID) | |
| 503 | #define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID) | |
| 504 | ||
| 505 | #define S_SCD_TREVT_DATAID 20 | |
| 506 | #define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID) | |
| 507 | #define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID) | |
| 508 | #define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID) | |
| 509 | ||
| 510 | #define S_SCD_TREVT_COUNT 24 | |
| 511 | #define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT) | |
| 512 | #define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT) | |
| 513 | #define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT) | |
| 514 | ||
| 515 | /* | |
| 516 | * Trace Sequence registers | |
| 517 | */ | |
| 518 | ||
| 519 | #define S_SCD_TRSEQ_EVENT4 0 | |
| 520 | #define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4) | |
| 521 | #define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4) | |
| 522 | #define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4) | |
| 523 | ||
| 524 | #define S_SCD_TRSEQ_EVENT3 4 | |
| 525 | #define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3) | |
| 526 | #define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3) | |
| 527 | #define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3) | |
| 528 | ||
| 529 | #define S_SCD_TRSEQ_EVENT2 8 | |
| 530 | #define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2) | |
| 531 | #define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2) | |
| 532 | #define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2) | |
| 533 | ||
| 534 | #define S_SCD_TRSEQ_EVENT1 12 | |
| 535 | #define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1) | |
| 536 | #define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1) | |
| 537 | #define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1) | |
| 538 | ||
| 539 | #define K_SCD_TRSEQ_E0 0 | |
| 540 | #define K_SCD_TRSEQ_E1 1 | |
| 541 | #define K_SCD_TRSEQ_E2 2 | |
| 542 | #define K_SCD_TRSEQ_E3 3 | |
| 543 | #define K_SCD_TRSEQ_E0_E1 4 | |
| 544 | #define K_SCD_TRSEQ_E1_E2 5 | |
| 545 | #define K_SCD_TRSEQ_E2_E3 6 | |
| 546 | #define K_SCD_TRSEQ_E0_E1_E2 7 | |
| 547 | #define K_SCD_TRSEQ_E0_E1_E2_E3 8 | |
| 548 | #define K_SCD_TRSEQ_E0E1 9 | |
| 549 | #define K_SCD_TRSEQ_E0E1E2 10 | |
| 550 | #define K_SCD_TRSEQ_E0E1E2E3 11 | |
| 551 | #define K_SCD_TRSEQ_E0E1_E2 12 | |
| 552 | #define K_SCD_TRSEQ_E0E1_E2E3 13 | |
| 553 | #define K_SCD_TRSEQ_E0E1_E2_E3 14 | |
| 554 | #define K_SCD_TRSEQ_IGNORED 15 | |
| 555 | ||
| 556 | #define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \ | |
| 557 | V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \ | |
| 558 | V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \ | |
| 559 | V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED)) | |
| 560 | ||
| 561 | #define S_SCD_TRSEQ_FUNCTION 16 | |
| 562 | #define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION) | |
| 563 | #define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION) | |
| 564 | #define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION) | |
| 565 | ||
| 566 | #define K_SCD_TRSEQ_FUNC_NOP 0 | |
| 567 | #define K_SCD_TRSEQ_FUNC_START 1 | |
| 568 | #define K_SCD_TRSEQ_FUNC_STOP 2 | |
| 569 | #define K_SCD_TRSEQ_FUNC_FREEZE 3 | |
| 570 | ||
| 571 | #define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP) | |
| 572 | #define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START) | |
| 573 | #define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP) | |
| 574 | #define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE) | |
| 575 | ||
| 576 | #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18) | |
| 577 | #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19) | |
| 578 | #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20) | |
| 579 | #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21) | |
| 580 | #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22) | |
| 581 | ||
| 582 | #endif |