[linux-block.git] / include / asm-mips / pgtable-64.h

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
 */
#ifndef _ASM_PGTABLE_64_H
#define _ASM_PGTABLE_64_H

#include <linux/linkage.h>

#include <asm/addrspace.h>
#include <asm/page.h>
#include <asm/cachectl.h>

#include <asm-generic/pgtable-nopud.h>

/*
 * Each address space has 2 4K pages as its page directory, giving 1024
 * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a
 * single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page
 * tables. Each page table is also a single 4K page, giving 512 (==
 * PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to
 * invalid_pmd_table, each pmd entry is initialized to point to
 * invalid_pte_table, each pte is initialized to 0. When memory is low,
 * and a pmd table or a page table allocation fails, empty_bad_pmd_table
 * and empty_bad_page_table is returned back to higher layer code, so
 * that the failure is recognized later on. Linux does not seem to
 * handle these failures very well though. The empty_bad_page_table has
 * invalid pte entries in it, to force page faults.
 *
 * Kernel mappings: kernel mappings are held in the swapper_pg_table.
 * The layout is identical to userspace except it's indexed with the
 * fault address - VMALLOC_START.
 */

/* PMD_SHIFT determines the size of the area a second-level page table can map */
#define PMD_SHIFT	(PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
#define PMD_SIZE	(1UL << PMD_SHIFT)
#define PMD_MASK	(~(PMD_SIZE-1))

/* PGDIR_SHIFT determines what a third-level page table entry can map */
#define PGDIR_SHIFT	(PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
#define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

/*
 * For 4kB page size we use a 3 level page tree and an 8kB pud, which
 * permits us mapping 40 bits of virtual address space.
 *
 * We used to implement 41 bits by having an order 1 pmd level but that seemed
 * rather pointless.
 *
 * For 8kB page size we use a 3 level page tree which permits a total of
 * 8TB of address space.  Alternatively a 33-bit / 8GB organization using
 * two levels would be easy to implement.
 *
 * For 16kB page size we use a 2 level page tree which permits a total of
 * 36 bits of virtual address space.  We could add a third level but it seems
 * like at the moment there's no need for this.
 *
 * For 64kB page size we use a 2 level page table tree for a total of 42 bits
 * of virtual address space.
 */
#ifdef CONFIG_PAGE_SIZE_4KB
#define PGD_ORDER		1
#define PUD_ORDER		aieeee_attempt_to_allocate_pud
#define PMD_ORDER		0
#define PTE_ORDER		0
#endif
#ifdef CONFIG_PAGE_SIZE_8KB
#define PGD_ORDER		0
#define PUD_ORDER		aieeee_attempt_to_allocate_pud
#define PMD_ORDER		0
#define PTE_ORDER		0
#endif
#ifdef CONFIG_PAGE_SIZE_16KB
#define PGD_ORDER		0
#define PUD_ORDER		aieeee_attempt_to_allocate_pud
#define PMD_ORDER		0
#define PTE_ORDER		0
#endif
#ifdef CONFIG_PAGE_SIZE_64KB
#define PGD_ORDER		0
#define PUD_ORDER		aieeee_attempt_to_allocate_pud
#define PMD_ORDER		0
#define PTE_ORDER		0
#endif

#define PTRS_PER_PGD	((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
#define PTRS_PER_PMD	((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t))
#define PTRS_PER_PTE	((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))

#if PGDIR_SIZE >= TASK_SIZE
#define USER_PTRS_PER_PGD       (1)
#else
#define USER_PTRS_PER_PGD	(TASK_SIZE / PGDIR_SIZE)
#endif
#define FIRST_USER_ADDRESS	0UL

#define VMALLOC_START		MAP_BASE
#define VMALLOC_END	\
	(VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE)

#define pte_ERROR(e) \
	printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
#define pmd_ERROR(e) \
	printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
#define pgd_ERROR(e) \
	printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))

extern pte_t invalid_pte_table[PTRS_PER_PTE];
extern pte_t empty_bad_page_table[PTRS_PER_PTE];
extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];

/*
 * Empty pgd/pmd entries point to the invalid_pte_table.
 */
static inline int pmd_none(pmd_t pmd)
{
	return pmd_val(pmd) == (unsigned long) invalid_pte_table;
}

#define pmd_bad(pmd)		(pmd_val(pmd) & ~PAGE_MASK)

static inline int pmd_present(pmd_t pmd)
{
	return pmd_val(pmd) != (unsigned long) invalid_pte_table;
}

static inline void pmd_clear(pmd_t *pmdp)
{
	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
}

/*
 * Empty pud entries point to the invalid_pmd_table.
 */
static inline int pud_none(pud_t pud)
{
	return pud_val(pud) == (unsigned long) invalid_pmd_table;
}

static inline int pud_bad(pud_t pud)
{
	return pud_val(pud) & ~PAGE_MASK;
}

static inline int pud_present(pud_t pud)
{
	return pud_val(pud) != (unsigned long) invalid_pmd_table;
}

static inline void pud_clear(pud_t *pudp)
{
	pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
}

#define pte_page(x)		pfn_to_page(pte_pfn(x))

#ifdef CONFIG_CPU_VR41XX
#define pte_pfn(x)		((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
#define pfn_pte(pfn, prot)	__pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
#else
#define pte_pfn(x)		((unsigned long)((x).pte >> PAGE_SHIFT))
#define pfn_pte(pfn, prot)	__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
#endif

#define __pgd_offset(address)	pgd_index(address)
#define __pud_offset(address)	(((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
#define __pmd_offset(address)	pmd_index(address)

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, 0UL)

#define pgd_index(address)	(((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
#define pmd_index(address)	(((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))

/* to find an entry in a page-table-directory */
#define pgd_offset(mm,addr)	((mm)->pgd + pgd_index(addr))

static inline unsigned long pud_page_vaddr(pud_t pud)
{
	return pud_val(pud);
}
#define pud_phys(pud)		(pud_val(pud) - PAGE_OFFSET)
#define pud_page(pud)		(pfn_to_page(pud_phys(pud) >> PAGE_SHIFT))

/* Find an entry in the second-level page table.. */
static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
{
	return (pmd_t *) pud_page_vaddr(*pud) + pmd_index(address);
}

/* Find an entry in the third-level page table.. */
#define __pte_offset(address)						\
	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
#define pte_offset(dir, address)					\
	((pte_t *) (pmd_page_vaddr(*dir)) + __pte_offset(address))
#define pte_offset_kernel(dir, address)					\
	((pte_t *) pmd_page_vaddr(*(dir)) +  __pte_offset(address))
#define pte_offset_map(dir, address)					\
	((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
#define pte_offset_map_nested(dir, address)				\
	((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
#define pte_unmap(pte) ((void)(pte))
#define pte_unmap_nested(pte) ((void)(pte))

/*
 * Initialize a new pgd / pmd table with invalid pointers.
 */
extern void pgd_init(unsigned long page);
extern void pmd_init(unsigned long page, unsigned long pagetable);

/*
 * Non-present pages:  high 24 bits are offset, next 8 bits type,
 * low 32 bits zero.
 */
static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
{ pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; }

#define __swp_type(x)		(((x).val >> 32) & 0xff)
#define __swp_offset(x)		((x).val >> 40)
#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
#define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x)	((pte_t) { (x).val })

/*
 * Bits 0, 4, 6, and 7 are taken. Let's leave bits 1, 2, 3, and 5 alone to
 * make things easier, and only use the upper 56 bits for the page offset...
 */
#define PTE_FILE_MAX_BITS	56

#define pte_to_pgoff(_pte)	((_pte).pte >> 8)
#define pgoff_to_pte(off)	((pte_t) { ((off) << 8) | _PAGE_FILE })

#endif /* _ASM_PGTABLE_64_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
	7	* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
	8	*/
	9	#ifndef _ASM_PGTABLE_64_H
	10	#define _ASM_PGTABLE_64_H
	11
1da177e4 LT	12	#include <linux/linkage.h>
	13
	14	#include <asm/addrspace.h>
	15	#include <asm/page.h>
	16	#include <asm/cachectl.h>
	17
c6e8b587 RB	18	#include <asm-generic/pgtable-nopud.h>
c6e8b587 RB	19
1da177e4 LT	20	/*
	21	* Each address space has 2 4K pages as its page directory, giving 1024
	22	* (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a
c6e8b587 RB	23	* single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page
	24	* tables. Each page table is also a single 4K page, giving 512 (==
	25	* PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to
	26	* invalid_pmd_table, each pmd entry is initialized to point to
1da177e4 LT	27	* invalid_pte_table, each pte is initialized to 0. When memory is low,
	28	* and a pmd table or a page table allocation fails, empty_bad_pmd_table
	29	* and empty_bad_page_table is returned back to higher layer code, so
	30	* that the failure is recognized later on. Linux does not seem to
	31	* handle these failures very well though. The empty_bad_page_table has
	32	* invalid pte entries in it, to force page faults.
	33	*
	34	* Kernel mappings: kernel mappings are held in the swapper_pg_table.
	35	* The layout is identical to userspace except it's indexed with the
	36	* fault address - VMALLOC_START.
	37	*/
	38
	39	/* PMD_SHIFT determines the size of the area a second-level page table can map */
c6e8b587	40	#define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
1da177e4 LT	41	#define PMD_SIZE (1UL << PMD_SHIFT)
	42	#define PMD_MASK (~(PMD_SIZE-1))
	43
	44	/* PGDIR_SHIFT determines what a third-level page table entry can map */
c6e8b587	45	#define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
1da177e4 LT	46	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	47	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	48
	49	/*
c6e8b587	50	* For 4kB page size we use a 3 level page tree and an 8kB pud, which
1da177e4 LT	51	* permits us mapping 40 bits of virtual address space.
	52	*
	53	* We used to implement 41 bits by having an order 1 pmd level but that seemed
	54	* rather pointless.
	55	*
	56	* For 8kB page size we use a 3 level page tree which permits a total of
	57	* 8TB of address space. Alternatively a 33-bit / 8GB organization using
	58	* two levels would be easy to implement.
	59	*
	60	* For 16kB page size we use a 2 level page tree which permits a total of
f29244a5	61	* 36 bits of virtual address space. We could add a third level but it seems
1da177e4 LT	62	* like at the moment there's no need for this.
	63	*
	64	* For 64kB page size we use a 2 level page table tree for a total of 42 bits
	65	* of virtual address space.
	66	*/
	67	#ifdef CONFIG_PAGE_SIZE_4KB
	68	#define PGD_ORDER 1
c6e8b587	69	#define PUD_ORDER aieeee_attempt_to_allocate_pud
1da177e4 LT	70	#define PMD_ORDER 0
	71	#define PTE_ORDER 0
	72	#endif
	73	#ifdef CONFIG_PAGE_SIZE_8KB
	74	#define PGD_ORDER 0
c6e8b587	75	#define PUD_ORDER aieeee_attempt_to_allocate_pud
1da177e4 LT	76	#define PMD_ORDER 0
	77	#define PTE_ORDER 0
	78	#endif
	79	#ifdef CONFIG_PAGE_SIZE_16KB
	80	#define PGD_ORDER 0
c6e8b587	81	#define PUD_ORDER aieeee_attempt_to_allocate_pud
1da177e4 LT	82	#define PMD_ORDER 0
	83	#define PTE_ORDER 0
	84	#endif
	85	#ifdef CONFIG_PAGE_SIZE_64KB
	86	#define PGD_ORDER 0
c6e8b587	87	#define PUD_ORDER aieeee_attempt_to_allocate_pud
1da177e4 LT	88	#define PMD_ORDER 0
	89	#define PTE_ORDER 0
	90	#endif
	91
	92	#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
	93	#define PTRS_PER_PMD ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t))
	94	#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
	95
9dbd7b91 PW	96	#if PGDIR_SIZE >= TASK_SIZE
	97	#define USER_PTRS_PER_PGD (1)
	98	#else
1da177e4	99	#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
9dbd7b91 PW	100	#endif
9dbd7b91 PW	101	#define FIRST_USER_ADDRESS 0UL
1da177e4	102
f29244a5	103	#define VMALLOC_START MAP_BASE
1da177e4 LT	104	#define VMALLOC_END \
	105	(VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE)
	106
	107	#define pte_ERROR(e) \
	108	printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
	109	#define pmd_ERROR(e) \
	110	printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
	111	#define pgd_ERROR(e) \
	112	printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
	113
c6e8b587 RB	114	extern pte_t invalid_pte_table[PTRS_PER_PTE];
	115	extern pte_t empty_bad_page_table[PTRS_PER_PTE];
	116	extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
	117	extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
1da177e4 LT	118
1da177e4 LT	119	/*
1b3a6e97	120	* Empty pgd/pmd entries point to the invalid_pte_table.
1da177e4 LT	121	*/
	122	static inline int pmd_none(pmd_t pmd)
	123	{
	124	return pmd_val(pmd) == (unsigned long) invalid_pte_table;
	125	}
	126
	127	#define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
	128
	129	static inline int pmd_present(pmd_t pmd)
	130	{
	131	return pmd_val(pmd) != (unsigned long) invalid_pte_table;
	132	}
	133
	134	static inline void pmd_clear(pmd_t *pmdp)
	135	{
	136	pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
	137	}
	138
	139	/*
f29244a5	140	* Empty pud entries point to the invalid_pmd_table.
1da177e4	141	*/
c6e8b587	142	static inline int pud_none(pud_t pud)
1da177e4	143	{
c6e8b587	144	return pud_val(pud) == (unsigned long) invalid_pmd_table;
1da177e4 LT	145	}
1da177e4 LT	146
c6e8b587 RB	147	static inline int pud_bad(pud_t pud)
	148	{
	149	return pud_val(pud) & ~PAGE_MASK;
	150	}
1da177e4	151
c6e8b587	152	static inline int pud_present(pud_t pud)
1da177e4	153	{
c6e8b587	154	return pud_val(pud) != (unsigned long) invalid_pmd_table;
1da177e4 LT	155	}
1da177e4 LT	156
c6e8b587	157	static inline void pud_clear(pud_t *pudp)
1da177e4	158	{
c6e8b587	159	pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
1da177e4 LT	160	}
1da177e4 LT	161
1b3a6e97 TS	162	#define pte_page(x) pfn_to_page(pte_pfn(x))
1b3a6e97 TS	163
1da177e4 LT	164	#ifdef CONFIG_CPU_VR41XX
	165	#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
	166	#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) \| pgprot_val(prot))
	167	#else
	168	#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT))
	169	#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) \| pgprot_val(prot))
	170	#endif
	171
	172	#define __pgd_offset(address) pgd_index(address)
f29244a5	173	#define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1b3a6e97	174	#define __pmd_offset(address) pmd_index(address)
1da177e4 LT	175
1da177e4 LT	176	/* to find an entry in a kernel page-table-directory */
242954b5	177	#define pgd_offset_k(address) pgd_offset(&init_mm, 0UL)
1da177e4	178
f29244a5	179	#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1b3a6e97	180	#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1da177e4 LT	181
	182	/* to find an entry in a page-table-directory */
	183	#define pgd_offset(mm,addr) ((mm)->pgd + pgd_index(addr))
	184
46a82b2d	185	static inline unsigned long pud_page_vaddr(pud_t pud)
1da177e4	186	{
c6e8b587	187	return pud_val(pud);
1da177e4	188	}
46a82b2d DM	189	#define pud_phys(pud) (pud_val(pud) - PAGE_OFFSET)
46a82b2d DM	190	#define pud_page(pud) (pfn_to_page(pud_phys(pud) >> PAGE_SHIFT))
1da177e4 LT	191
1da177e4 LT	192	/* Find an entry in the second-level page table.. */
c6e8b587	193	static inline pmd_t pmd_offset(pud_t pud, unsigned long address)
1da177e4	194	{
46a82b2d	195	return (pmd_t ) pud_page_vaddr(pud) + pmd_index(address);
1da177e4 LT	196	}
	197
	198	/* Find an entry in the third-level page table.. */
	199	#define __pte_offset(address) \
	200	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
	201	#define pte_offset(dir, address) \
46a82b2d	202	((pte_t ) (pmd_page_vaddr(dir)) + __pte_offset(address))
1da177e4	203	#define pte_offset_kernel(dir, address) \
46a82b2d	204	((pte_t ) pmd_page_vaddr((dir)) + __pte_offset(address))
1da177e4 LT	205	#define pte_offset_map(dir, address) \
	206	((pte_t )page_address(pmd_page((dir))) + __pte_offset(address))
	207	#define pte_offset_map_nested(dir, address) \
	208	((pte_t )page_address(pmd_page((dir))) + __pte_offset(address))
	209	#define pte_unmap(pte) ((void)(pte))
	210	#define pte_unmap_nested(pte) ((void)(pte))
	211
	212	/*
	213	* Initialize a new pgd / pmd table with invalid pointers.
	214	*/
	215	extern void pgd_init(unsigned long page);
	216	extern void pmd_init(unsigned long page, unsigned long pagetable);
	217
	218	/*
	219	* Non-present pages: high 24 bits are offset, next 8 bits type,
	220	* low 32 bits zero.
	221	*/
	222	static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
	223	{ pte_t pte; pte_val(pte) = (type << 32) \| (offset << 40); return pte; }
	224
	225	#define __swp_type(x) (((x).val >> 32) & 0xff)
	226	#define __swp_offset(x) ((x).val >> 40)
	227	#define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
	228	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
	229	#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
	230
	231	/*
7cb710c9 SS	232	* Bits 0, 4, 6, and 7 are taken. Let's leave bits 1, 2, 3, and 5 alone to
7cb710c9 SS	233	* make things easier, and only use the upper 56 bits for the page offset...
1da177e4	234	*/
7cb710c9	235	#define PTE_FILE_MAX_BITS 56
1da177e4	236
7cb710c9 SS	237	#define pte_to_pgoff(_pte) ((_pte).pte >> 8)
7cb710c9 SS	238	#define pgoff_to_pte(off) ((pte_t) { ((off) << 8) \| _PAGE_FILE })
1da177e4 LT	239
1da177e4 LT	240	#endif /* _ASM_PGTABLE_64_H */