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699dbc90 RB |
1 | /* |
2 | * MT regs definitions, follows on from mipsregs.h | |
3 | * Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved. | |
4 | * Elizabeth Clarke et. al. | |
5 | * | |
6 | */ | |
7 | #ifndef _ASM_MIPSMTREGS_H | |
8 | #define _ASM_MIPSMTREGS_H | |
9 | ||
340ee4b9 | 10 | #include <asm/mipsregs.h> |
699dbc90 RB |
11 | #include <asm/war.h> |
12 | ||
13 | #ifndef __ASSEMBLY__ | |
14 | ||
15 | /* | |
16 | * C macros | |
17 | */ | |
18 | ||
19 | #define read_c0_mvpcontrol() __read_32bit_c0_register($0, 1) | |
20 | #define write_c0_mvpcontrol(val) __write_32bit_c0_register($0, 1, val) | |
21 | ||
22 | #define read_c0_mvpconf0() __read_32bit_c0_register($0, 2) | |
23 | #define read_c0_mvpconf1() __read_32bit_c0_register($0, 3) | |
24 | ||
25 | #define read_c0_vpecontrol() __read_32bit_c0_register($1, 1) | |
26 | #define write_c0_vpecontrol(val) __write_32bit_c0_register($1, 1, val) | |
27 | ||
28 | #define read_c0_vpeconf0() __read_32bit_c0_register($1, 2) | |
29 | #define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val) | |
30 | ||
31 | #define read_c0_tcstatus() __read_32bit_c0_register($2, 1) | |
32 | #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) | |
33 | ||
34 | #define read_c0_tcbind() __read_32bit_c0_register($2, 2) | |
35 | ||
36 | #define read_c0_tccontext() __read_32bit_c0_register($2, 5) | |
37 | #define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val) | |
38 | ||
39 | #else /* Assembly */ | |
40 | /* | |
41 | * Macros for use in assembly language code | |
42 | */ | |
43 | ||
44 | #define CP0_MVPCONTROL $0,1 | |
45 | #define CP0_MVPCONF0 $0,2 | |
46 | #define CP0_MVPCONF1 $0,3 | |
47 | #define CP0_VPECONTROL $1,1 | |
48 | #define CP0_VPECONF0 $1,2 | |
49 | #define CP0_VPECONF1 $1,3 | |
50 | #define CP0_YQMASK $1,4 | |
51 | #define CP0_VPESCHEDULE $1,5 | |
52 | #define CP0_VPESCHEFBK $1,6 | |
53 | #define CP0_TCSTATUS $2,1 | |
54 | #define CP0_TCBIND $2,2 | |
55 | #define CP0_TCRESTART $2,3 | |
56 | #define CP0_TCHALT $2,4 | |
57 | #define CP0_TCCONTEXT $2,5 | |
58 | #define CP0_TCSCHEDULE $2,6 | |
59 | #define CP0_TCSCHEFBK $2,7 | |
60 | #define CP0_SRSCONF0 $6,1 | |
61 | #define CP0_SRSCONF1 $6,2 | |
62 | #define CP0_SRSCONF2 $6,3 | |
63 | #define CP0_SRSCONF3 $6,4 | |
64 | #define CP0_SRSCONF4 $6,5 | |
65 | ||
66 | #endif | |
67 | ||
68 | /* MVPControl fields */ | |
69 | #define MVPCONTROL_EVP (_ULCAST_(1)) | |
70 | ||
71 | #define MVPCONTROL_VPC_SHIFT 1 | |
72 | #define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT) | |
73 | ||
74 | #define MVPCONTROL_STLB_SHIFT 2 | |
75 | #define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT) | |
76 | ||
77 | ||
78 | /* MVPConf0 fields */ | |
79 | #define MVPCONF0_PTC_SHIFT 0 | |
80 | #define MVPCONF0_PTC ( _ULCAST_(0xff)) | |
81 | #define MVPCONF0_PVPE_SHIFT 10 | |
82 | #define MVPCONF0_PVPE ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT) | |
83 | #define MVPCONF0_TCA_SHIFT 15 | |
84 | #define MVPCONF0_TCA ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT) | |
85 | #define MVPCONF0_PTLBE_SHIFT 16 | |
86 | #define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT) | |
87 | #define MVPCONF0_TLBS_SHIFT 29 | |
88 | #define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT) | |
89 | #define MVPCONF0_M_SHIFT 31 | |
90 | #define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT) | |
91 | ||
92 | ||
93 | /* config3 fields */ | |
94 | #define CONFIG3_MT_SHIFT 2 | |
95 | #define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT) | |
96 | ||
97 | ||
98 | /* VPEControl fields (per VPE) */ | |
99 | #define VPECONTROL_TARGTC (_ULCAST_(0xff)) | |
100 | ||
101 | #define VPECONTROL_TE_SHIFT 15 | |
102 | #define VPECONTROL_TE (_ULCAST_(1) << VPECONTROL_TE_SHIFT) | |
103 | #define VPECONTROL_EXCPT_SHIFT 16 | |
104 | #define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT) | |
105 | ||
106 | /* Thread Exception Codes for EXCPT field */ | |
107 | #define THREX_TU 0 | |
108 | #define THREX_TO 1 | |
109 | #define THREX_IYQ 2 | |
110 | #define THREX_GSX 3 | |
111 | #define THREX_YSCH 4 | |
112 | #define THREX_GSSCH 5 | |
113 | ||
114 | #define VPECONTROL_GSI_SHIFT 20 | |
115 | #define VPECONTROL_GSI (_ULCAST_(1) << VPECONTROL_GSI_SHIFT) | |
116 | #define VPECONTROL_YSI_SHIFT 21 | |
117 | #define VPECONTROL_YSI (_ULCAST_(1) << VPECONTROL_YSI_SHIFT) | |
118 | ||
119 | /* VPEConf0 fields (per VPE) */ | |
120 | #define VPECONF0_VPA_SHIFT 0 | |
121 | #define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT) | |
122 | #define VPECONF0_MVP_SHIFT 1 | |
123 | #define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT) | |
124 | #define VPECONF0_XTC_SHIFT 21 | |
125 | #define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT) | |
126 | ||
127 | /* TCStatus fields (per TC) */ | |
128 | #define TCSTATUS_TASID (_ULCAST_(0xff)) | |
129 | #define TCSTATUS_IXMT_SHIFT 10 | |
130 | #define TCSTATUS_IXMT (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT) | |
131 | #define TCSTATUS_TKSU_SHIFT 11 | |
132 | #define TCSTATUS_TKSU (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT) | |
133 | #define TCSTATUS_A_SHIFT 13 | |
134 | #define TCSTATUS_A (_ULCAST_(1) << TCSTATUS_A_SHIFT) | |
135 | #define TCSTATUS_DA_SHIFT 15 | |
136 | #define TCSTATUS_DA (_ULCAST_(1) << TCSTATUS_DA_SHIFT) | |
137 | #define TCSTATUS_DT_SHIFT 20 | |
138 | #define TCSTATUS_DT (_ULCAST_(1) << TCSTATUS_DT_SHIFT) | |
139 | #define TCSTATUS_TDS_SHIFT 21 | |
140 | #define TCSTATUS_TDS (_ULCAST_(1) << TCSTATUS_TDS_SHIFT) | |
141 | #define TCSTATUS_TSST_SHIFT 22 | |
142 | #define TCSTATUS_TSST (_ULCAST_(1) << TCSTATUS_TSST_SHIFT) | |
143 | #define TCSTATUS_RNST_SHIFT 23 | |
144 | #define TCSTATUS_RNST (_ULCAST_(3) << TCSTATUS_RNST_SHIFT) | |
145 | /* Codes for RNST */ | |
146 | #define TC_RUNNING 0 | |
147 | #define TC_WAITING 1 | |
148 | #define TC_YIELDING 2 | |
149 | #define TC_GATED 3 | |
150 | ||
151 | #define TCSTATUS_TMX_SHIFT 27 | |
152 | #define TCSTATUS_TMX (_ULCAST_(1) << TCSTATUS_TMX_SHIFT) | |
153 | /* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */ | |
154 | ||
155 | /* TCBind */ | |
156 | #define TCBIND_CURVPE_SHIFT 0 | |
157 | #define TCBIND_CURVPE (_ULCAST_(0xf)) | |
158 | ||
159 | #define TCBIND_CURTC_SHIFT 21 | |
160 | ||
161 | #define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT) | |
162 | ||
163 | /* TCHalt */ | |
164 | #define TCHALT_H (_ULCAST_(1)) | |
165 | ||
166 | #ifndef __ASSEMBLY__ | |
167 | ||
168 | extern void mips_mt_regdump(void); | |
169 | ||
170 | static inline unsigned int dvpe(void) | |
171 | { | |
172 | int res = 0; | |
173 | ||
174 | __asm__ __volatile__( | |
175 | " .set push \n" | |
176 | " .set noreorder \n" | |
177 | " .set noat \n" | |
178 | " .set mips32r2 \n" | |
699dbc90 | 179 | " .word 0x41610001 # dvpe $1 \n" |
8f40611d | 180 | " move %0, $1 \n" |
699dbc90 RB |
181 | " ehb \n" |
182 | " .set pop \n" | |
183 | : "=r" (res)); | |
184 | ||
185 | instruction_hazard(); | |
186 | ||
187 | return res; | |
188 | } | |
189 | ||
190 | static inline void __raw_evpe(void) | |
191 | { | |
192 | __asm__ __volatile__( | |
193 | " .set push \n" | |
194 | " .set noreorder \n" | |
195 | " .set noat \n" | |
196 | " .set mips32r2 \n" | |
197 | " .word 0x41600021 # evpe \n" | |
198 | " ehb \n" | |
199 | " .set pop \n"); | |
200 | } | |
201 | ||
202 | /* Enable multiMT if previous suggested it should be. | |
203 | EMT_ENABLE to force */ | |
204 | ||
205 | #define EVPE_ENABLE MVPCONTROL_EVP | |
206 | ||
207 | static inline void evpe(int previous) | |
208 | { | |
209 | if ((previous & MVPCONTROL_EVP)) | |
210 | __raw_evpe(); | |
211 | } | |
212 | ||
213 | static inline unsigned int dmt(void) | |
214 | { | |
215 | int res; | |
216 | ||
217 | __asm__ __volatile__( | |
8f40611d | 218 | " .set push \n" |
699dbc90 | 219 | " .set mips32r2 \n" |
8f40611d RB |
220 | " .set noat \n" |
221 | " .word 0x41610BC1 # dmt $1 \n" | |
699dbc90 | 222 | " ehb \n" |
8f40611d RB |
223 | " move %0, $1 \n" |
224 | " .set pop \n" | |
699dbc90 RB |
225 | : "=r" (res)); |
226 | ||
227 | instruction_hazard(); | |
228 | ||
229 | return res; | |
230 | } | |
231 | ||
232 | static inline void __raw_emt(void) | |
233 | { | |
234 | __asm__ __volatile__( | |
235 | " .set noreorder \n" | |
236 | " .set mips32r2 \n" | |
237 | " emt \n" | |
238 | " ehb \n" | |
239 | " .set mips0 \n" | |
240 | " .set reorder"); | |
241 | } | |
242 | ||
243 | /* enable multiVPE if previous suggested it should be. | |
244 | EVPE_ENABLE to force */ | |
245 | ||
246 | #define EMT_ENABLE VPECONTROL_TE | |
247 | ||
248 | static inline void emt(int previous) | |
249 | { | |
250 | if ((previous & EMT_ENABLE)) | |
251 | __raw_emt(); | |
252 | } | |
253 | ||
254 | static inline void ehb(void) | |
255 | { | |
8f40611d RB |
256 | __asm__ __volatile__( |
257 | " .set mips32r2 \n" | |
258 | " ehb \n" | |
259 | " .set mips0 \n"); | |
699dbc90 RB |
260 | } |
261 | ||
262 | #define mftc0(rt,sel) \ | |
263 | ({ \ | |
264 | unsigned long __res; \ | |
265 | \ | |
266 | __asm__ __volatile__( \ | |
8f40611d RB |
267 | " .set push \n" \ |
268 | " .set mips32r2 \n" \ | |
269 | " .set noat \n" \ | |
270 | " # mftc0 $1, $" #rt ", " #sel " \n" \ | |
271 | " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \ | |
272 | " move %0, $1 \n" \ | |
273 | " .set pop \n" \ | |
274 | : "=r" (__res)); \ | |
699dbc90 RB |
275 | \ |
276 | __res; \ | |
277 | }) | |
278 | ||
279 | #define mftgpr(rt) \ | |
280 | ({ \ | |
281 | unsigned long __res; \ | |
282 | \ | |
283 | __asm__ __volatile__( \ | |
8f40611d RB |
284 | " .set push \n" \ |
285 | " .set mips32r2 \n" \ | |
699dbc90 | 286 | " mftgpr %0," #rt " \n" \ |
8f40611d | 287 | " .set pop \n" \ |
699dbc90 RB |
288 | : "=r" (__res)); \ |
289 | \ | |
290 | __res; \ | |
291 | }) | |
292 | ||
293 | #define mftr(rt,u,sel) \ | |
294 | ({ \ | |
295 | unsigned long __res; \ | |
296 | \ | |
297 | __asm__ __volatile__( \ | |
298 | ".set noat\n\t" \ | |
299 | "mftr\t%0, " #rt ", " #u ", " #sel "\n\t" \ | |
300 | ".set at\n\t" \ | |
301 | : "=r" (__res)); \ | |
302 | \ | |
303 | __res; \ | |
304 | }) | |
305 | ||
306 | #define mttgpr(rd,v) \ | |
8f40611d | 307 | do { \ |
699dbc90 | 308 | __asm__ __volatile__( \ |
8f40611d RB |
309 | " .set push \n" \ |
310 | " .set mips32r2 \n" \ | |
311 | " .set noat \n" \ | |
312 | " move $1, %0 \n" \ | |
313 | " # mttgpr $1, " #rd " \n" \ | |
314 | " .word 0x41810020 | (" #rd " << 11) \n" \ | |
315 | " .set pop \n" \ | |
699dbc90 | 316 | : : "r" (v)); \ |
8f40611d | 317 | } while (0) |
699dbc90 RB |
318 | |
319 | #define mttc0(rd,sel,v) \ | |
320 | ({ \ | |
321 | __asm__ __volatile__( \ | |
8f40611d RB |
322 | " .set push \n" \ |
323 | " .set mips32r2 \n" \ | |
324 | " .set noat \n" \ | |
325 | " move $1, %0 \n" \ | |
326 | " # mttc0 %0," #rd ", " #sel " \n" \ | |
327 | " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \ | |
328 | " .set pop \n" \ | |
329 | : \ | |
330 | : "r" (v)); \ | |
699dbc90 RB |
331 | }) |
332 | ||
333 | ||
334 | #define mttr(rd,u,sel,v) \ | |
335 | ({ \ | |
336 | __asm__ __volatile__( \ | |
337 | "mttr %0," #rd ", " #u ", " #sel \ | |
338 | : : "r" (v)); \ | |
339 | }) | |
340 | ||
341 | ||
342 | #define settc(tc) \ | |
343 | do { \ | |
344 | write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); \ | |
345 | ehb(); \ | |
346 | } while (0) | |
347 | ||
348 | ||
349 | /* you *must* set the target tc (settc) before trying to use these */ | |
8f40611d RB |
350 | #define read_vpe_c0_vpecontrol() mftc0(1, 1) |
351 | #define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val) | |
352 | #define read_vpe_c0_vpeconf0() mftc0(1, 2) | |
353 | #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) | |
354 | #define read_vpe_c0_status() mftc0(12, 0) | |
355 | #define write_vpe_c0_status(val) mttc0(12, 0, val) | |
356 | #define read_vpe_c0_cause() mftc0(13, 0) | |
357 | #define write_vpe_c0_cause(val) mttc0(13, 0, val) | |
358 | #define read_vpe_c0_config() mftc0(16, 0) | |
359 | #define write_vpe_c0_config(val) mttc0(16, 0, val) | |
360 | #define read_vpe_c0_config1() mftc0(16, 1) | |
361 | #define write_vpe_c0_config1(val) mttc0(16, 1, val) | |
362 | #define read_vpe_c0_config7() mftc0(16, 7) | |
363 | #define write_vpe_c0_config7(val) mttc0(16, 7, val) | |
364 | #define read_vpe_c0_ebase() mftc0(15,1) | |
365 | #define write_vpe_c0_ebase(val) mttc0(15, 1, val) | |
366 | #define write_vpe_c0_compare(val) mttc0(11, 0, val) | |
699dbc90 RB |
367 | |
368 | ||
369 | /* TC */ | |
8f40611d RB |
370 | #define read_tc_c0_tcstatus() mftc0(2, 1) |
371 | #define write_tc_c0_tcstatus(val) mttc0(2,1,val) | |
372 | #define read_tc_c0_tcbind() mftc0(2, 2) | |
373 | #define write_tc_c0_tcbind(val) mttc0(2,2,val) | |
374 | #define read_tc_c0_tcrestart() mftc0(2, 3) | |
375 | #define write_tc_c0_tcrestart(val) mttc0(2,3,val) | |
376 | #define read_tc_c0_tchalt() mftc0(2, 4) | |
377 | #define write_tc_c0_tchalt(val) mttc0(2,4,val) | |
378 | #define read_tc_c0_tccontext() mftc0(2, 5) | |
379 | #define write_tc_c0_tccontext(val) mttc0(2,5,val) | |
699dbc90 RB |
380 | |
381 | /* GPR */ | |
8f40611d RB |
382 | #define read_tc_gpr_sp() mftgpr(29) |
383 | #define write_tc_gpr_sp(val) mttgpr(29, val) | |
384 | #define read_tc_gpr_gp() mftgpr(28) | |
385 | #define write_tc_gpr_gp(val) mttgpr(28, val) | |
699dbc90 | 386 | |
340ee4b9 | 387 | __BUILD_SET_C0(mvpcontrol) |
699dbc90 RB |
388 | |
389 | #endif /* Not __ASSEMBLY__ */ | |
390 | ||
391 | #endif |