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1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle | |
7 | * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle | |
8 | */ | |
9 | #ifndef _ASM_IRQ_H | |
10 | #define _ASM_IRQ_H | |
11 | ||
1da177e4 | 12 | #include <linux/linkage.h> |
41c594ab RB |
13 | |
14 | #include <asm/mipsmtregs.h> | |
15 | ||
1da177e4 LT |
16 | #include <irq.h> |
17 | ||
18 | #ifdef CONFIG_I8259 | |
19 | static inline int irq_canonicalize(int irq) | |
20 | { | |
2fa7937b | 21 | return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq); |
1da177e4 LT |
22 | } |
23 | #else | |
24 | #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ | |
25 | #endif | |
26 | ||
0db34215 | 27 | #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP |
41c594ab RB |
28 | /* |
29 | * Clear interrupt mask handling "backstop" if irq_hwmask | |
30 | * entry so indicates. This implies that the ack() or end() | |
31 | * functions will take over re-enabling the low-level mask. | |
32 | * Otherwise it will be done on return from exception. | |
33 | */ | |
f9bba75e | 34 | #define __DO_IRQ_SMTC_HOOK(irq) \ |
41c594ab RB |
35 | do { \ |
36 | if (irq_hwmask[irq] & 0x0000ff00) \ | |
37 | write_c0_tccontext(read_c0_tccontext() & \ | |
38 | ~(irq_hwmask[irq] & 0x0000ff00)); \ | |
39 | } while (0) | |
40 | #else | |
f9bba75e | 41 | #define __DO_IRQ_SMTC_HOOK(irq) do { } while (0) |
41c594ab RB |
42 | #endif |
43 | ||
1da177e4 LT |
44 | /* |
45 | * do_IRQ handles all normal device IRQ's (the special | |
46 | * SMP cross-CPU interrupts have their own specific | |
47 | * handlers). | |
48 | * | |
49 | * Ideally there should be away to get this into kernel/irq/handle.c to | |
50 | * avoid the overhead of a call for just a tiny function ... | |
51 | */ | |
937a8015 | 52 | #define do_IRQ(irq) \ |
1da177e4 LT |
53 | do { \ |
54 | irq_enter(); \ | |
f9bba75e | 55 | __DO_IRQ_SMTC_HOOK(irq); \ |
1417836e | 56 | generic_handle_irq(irq); \ |
1da177e4 LT |
57 | irq_exit(); \ |
58 | } while (0) | |
59 | ||
1da177e4 | 60 | extern void arch_init_irq(void); |
937a8015 | 61 | extern void spurious_interrupt(void); |
1da177e4 | 62 | |
41c594ab RB |
63 | #ifdef CONFIG_MIPS_MT_SMTC |
64 | struct irqaction; | |
65 | ||
66 | extern unsigned long irq_hwmask[]; | |
67 | extern int setup_irq_smtc(unsigned int irq, struct irqaction * new, | |
68 | unsigned long hwmask); | |
69 | #endif /* CONFIG_MIPS_MT_SMTC */ | |
70 | ||
4a4cf779 RB |
71 | extern int allocate_irqno(void); |
72 | extern void alloc_legacy_irqno(void); | |
73 | extern void free_irqno(unsigned int irq); | |
74 | ||
3b1d4ed5 RB |
75 | /* |
76 | * Before R2 the timer and performance counter interrupts were both fixed to | |
77 | * IE7. Since R2 their number has to be read from the c0_intctl register. | |
78 | */ | |
79 | #define CP0_LEGACY_COMPARE_IRQ 7 | |
80 | ||
81 | extern int cp0_compare_irq; | |
82 | extern int cp0_perfcount_irq; | |
83 | ||
1da177e4 | 84 | #endif /* _ASM_IRQ_H */ |