[linux-2.6-block.git] / include / asm-mips / i8259.h

/*
 *	include/asm-mips/i8259.h
 *
 *	i8259A interrupt definitions.
 *
 *	Copyright (C) 2003  Maciej W. Rozycki
 *	Copyright (C) 2003  Ralf Baechle <ralf@linux-mips.org>
 *
 *	This program is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU General Public License
 *	as published by the Free Software Foundation; either version
 *	2 of the License, or (at your option) any later version.
 */
#ifndef _ASM_I8259_H
#define _ASM_I8259_H

#include <linux/compiler.h>
#include <linux/spinlock.h>

#include <asm/io.h>
#include <irq.h>

/* i8259A PIC registers */
#define PIC_MASTER_CMD		0x20
#define PIC_MASTER_IMR		0x21
#define PIC_MASTER_ISR		PIC_MASTER_CMD
#define PIC_MASTER_POLL		PIC_MASTER_ISR
#define PIC_MASTER_OCW3		PIC_MASTER_ISR
#define PIC_SLAVE_CMD		0xa0
#define PIC_SLAVE_IMR		0xa1

/* i8259A PIC related value */
#define PIC_CASCADE_IR		2
#define MASTER_ICW4_DEFAULT	0x01
#define SLAVE_ICW4_DEFAULT	0x01
#define PIC_ICW4_AEOI		2

extern spinlock_t i8259A_lock;

extern int i8259A_irq_pending(unsigned int irq);
extern void make_8259A_irq(unsigned int irq);

extern void init_i8259_irqs(void);

/*
 * Do the traditional i8259 interrupt polling thing.  This is for the few
 * cases where no better interrupt acknowledge method is available and we
 * absolutely must touch the i8259.
 */
static inline int i8259_irq(void)
{
	int irq;

	spin_lock(&i8259A_lock);

	/* Perform an interrupt acknowledge cycle on controller 1. */
	outb(0x0C, PIC_MASTER_CMD);		/* prepare for poll */
	irq = inb(PIC_MASTER_CMD) & 7;
	if (irq == PIC_CASCADE_IR) {
		/*
		 * Interrupt is cascaded so perform interrupt
		 * acknowledge on controller 2.
		 */
		outb(0x0C, PIC_SLAVE_CMD);		/* prepare for poll */
		irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
	}

	if (unlikely(irq == 7)) {
		/*
		 * This may be a spurious interrupt.
		 *
		 * Read the interrupt status register (ISR). If the most
		 * significant bit is not set then there is no valid
		 * interrupt.
		 */
		outb(0x0B, PIC_MASTER_ISR);		/* ISR register */
		if(~inb(PIC_MASTER_ISR) & 0x80)
			irq = -1;
	}

	spin_unlock(&i8259A_lock);

	return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
}

#endif /* _ASM_I8259_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* include/asm-mips/i8259.h
	3	*
	4	* i8259A interrupt definitions.
	5	*
	6	* Copyright (C) 2003 Maciej W. Rozycki
	7	* Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version
	12	* 2 of the License, or (at your option) any later version.
	13	*/
	14	#ifndef _ASM_I8259_H
	15	#define _ASM_I8259_H
	16
	17	#include <linux/compiler.h>
	18	#include <linux/spinlock.h>
	19
	20	#include <asm/io.h>
2fa7937b	21	#include <irq.h>
1da177e4	22
2cafe978 AN	23	/* i8259A PIC registers */
	24	#define PIC_MASTER_CMD 0x20
	25	#define PIC_MASTER_IMR 0x21
	26	#define PIC_MASTER_ISR PIC_MASTER_CMD
	27	#define PIC_MASTER_POLL PIC_MASTER_ISR
	28	#define PIC_MASTER_OCW3 PIC_MASTER_ISR
	29	#define PIC_SLAVE_CMD 0xa0
	30	#define PIC_SLAVE_IMR 0xa1
	31
	32	/* i8259A PIC related value */
	33	#define PIC_CASCADE_IR 2
	34	#define MASTER_ICW4_DEFAULT 0x01
	35	#define SLAVE_ICW4_DEFAULT 0x01
	36	#define PIC_ICW4_AEOI 2
	37
1da177e4 LT	38	extern spinlock_t i8259A_lock;
1da177e4 LT	39
d80c1c0b YY	40	extern int i8259A_irq_pending(unsigned int irq);
d80c1c0b YY	41	extern void make_8259A_irq(unsigned int irq);
2cafe978	42
1da177e4 LT	43	extern void init_i8259_irqs(void);
	44
	45	/*
	46	* Do the traditional i8259 interrupt polling thing. This is for the few
	47	* cases where no better interrupt acknowledge method is available and we
	48	* absolutely must touch the i8259.
	49	*/
	50	static inline int i8259_irq(void)
	51	{
	52	int irq;
	53
	54	spin_lock(&i8259A_lock);
	55
	56	/* Perform an interrupt acknowledge cycle on controller 1. */
2cafe978 AN	57	outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */
	58	irq = inb(PIC_MASTER_CMD) & 7;
	59	if (irq == PIC_CASCADE_IR) {
1da177e4 LT	60	/*
	61	* Interrupt is cascaded so perform interrupt
	62	* acknowledge on controller 2.
	63	*/
2cafe978 AN	64	outb(0x0C, PIC_SLAVE_CMD); /* prepare for poll */
2cafe978 AN	65	irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
1da177e4 LT	66	}
	67
	68	if (unlikely(irq == 7)) {
	69	/*
	70	* This may be a spurious interrupt.
	71	*
	72	* Read the interrupt status register (ISR). If the most
	73	* significant bit is not set then there is no valid
	74	* interrupt.
	75	*/
2cafe978 AN	76	outb(0x0B, PIC_MASTER_ISR); /* ISR register */
2cafe978 AN	77	if(~inb(PIC_MASTER_ISR) & 0x80)
1da177e4 LT	78	irq = -1;
	79	}
	80
	81	spin_unlock(&i8259A_lock);
	82
2cafe978	83	return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
1da177e4 LT	84	}
	85
	86	#endif /* _ASM_I8259_H */