projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc. | |
| 3 | * All rights reserved. | |
| 4 | * Authors: Carsten Langgaard <carstenl@mips.com> | |
| 5 | * Maciej W. Rozycki <macro@mips.com> | |
| 6 | * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) | |
| 7 | * | |
| 8 | * This program is free software; you can distribute it and/or modify it | |
| 9 | * under the terms of the GNU General Public License (Version 2) as | |
| 10 | * published by the Free Software Foundation. | |
| 11 | * | |
| 12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 15 | * for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License along | |
| 18 | * with this program; if not, write to the Free Software Foundation, Inc., | |
| 19 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | |
| 20 | */ | |
| 21 | #ifndef _ASM_GT64120_H | |
| 22 | #define _ASM_GT64120_H | |
| 23 | ||
| 1097c6ac YY |
24 | #include <linux/clocksource.h> |
| 25 | ||
| 1da177e4 LT |
26 | #include <asm/addrspace.h> |
| 27 | #include <asm/byteorder.h> | |
| 28 | ||
| 29 | #define MSK(n) ((1 << (n)) - 1) | |
| 30 | ||
| 31 | /* | |
| 32 | * Register offset addresses | |
| 33 | */ | |
| 34 | /* CPU Configuration. */ | |
| 35 | #define GT_CPU_OFS 0x000 | |
| 36 | ||
| 37 | #define GT_MULTI_OFS 0x120 | |
| 38 | ||
| 39 | /* CPU Address Decode. */ | |
| 40 | #define GT_SCS10LD_OFS 0x008 | |
| 41 | #define GT_SCS10HD_OFS 0x010 | |
| 42 | #define GT_SCS32LD_OFS 0x018 | |
| 43 | #define GT_SCS32HD_OFS 0x020 | |
| 44 | #define GT_CS20LD_OFS 0x028 | |
| 45 | #define GT_CS20HD_OFS 0x030 | |
| 46 | #define GT_CS3BOOTLD_OFS 0x038 | |
| 47 | #define GT_CS3BOOTHD_OFS 0x040 | |
| 48 | #define GT_PCI0IOLD_OFS 0x048 | |
| 49 | #define GT_PCI0IOHD_OFS 0x050 | |
| 50 | #define GT_PCI0M0LD_OFS 0x058 | |
| 51 | #define GT_PCI0M0HD_OFS 0x060 | |
| 52 | #define GT_ISD_OFS 0x068 | |
| 53 | ||
| 54 | #define GT_PCI0M1LD_OFS 0x080 | |
| 55 | #define GT_PCI0M1HD_OFS 0x088 | |
| 56 | #define GT_PCI1IOLD_OFS 0x090 | |
| 57 | #define GT_PCI1IOHD_OFS 0x098 | |
| 58 | #define GT_PCI1M0LD_OFS 0x0a0 | |
| 59 | #define GT_PCI1M0HD_OFS 0x0a8 | |
| 60 | #define GT_PCI1M1LD_OFS 0x0b0 | |
| 61 | #define GT_PCI1M1HD_OFS 0x0b8 | |
| 62 | #define GT_PCI1M1LD_OFS 0x0b0 | |
| 63 | #define GT_PCI1M1HD_OFS 0x0b8 | |
| 64 | ||
| 65 | #define GT_SCS10AR_OFS 0x0d0 | |
| 66 | #define GT_SCS32AR_OFS 0x0d8 | |
| 67 | #define GT_CS20R_OFS 0x0e0 | |
| 68 | #define GT_CS3BOOTR_OFS 0x0e8 | |
| 69 | ||
| 70 | #define GT_PCI0IOREMAP_OFS 0x0f0 | |
| 71 | #define GT_PCI0M0REMAP_OFS 0x0f8 | |
| 72 | #define GT_PCI0M1REMAP_OFS 0x100 | |
| 73 | #define GT_PCI1IOREMAP_OFS 0x108 | |
| 74 | #define GT_PCI1M0REMAP_OFS 0x110 | |
| 75 | #define GT_PCI1M1REMAP_OFS 0x118 | |
| 76 | ||
| 77 | /* CPU Error Report. */ | |
| 78 | #define GT_CPUERR_ADDRLO_OFS 0x070 | |
| 79 | #define GT_CPUERR_ADDRHI_OFS 0x078 | |
| 80 | ||
| 81 | #define GT_CPUERR_DATALO_OFS 0x128 /* GT-64120A only */ | |
| 82 | #define GT_CPUERR_DATAHI_OFS 0x130 /* GT-64120A only */ | |
| 83 | #define GT_CPUERR_PARITY_OFS 0x138 /* GT-64120A only */ | |
| 84 | ||
| 85 | /* CPU Sync Barrier. */ | |
| 86 | #define GT_PCI0SYNC_OFS 0x0c0 | |
| 87 | #define GT_PCI1SYNC_OFS 0x0c8 | |
| 88 | ||
| 89 | /* SDRAM and Device Address Decode. */ | |
| 90 | #define GT_SCS0LD_OFS 0x400 | |
| 91 | #define GT_SCS0HD_OFS 0x404 | |
| 92 | #define GT_SCS1LD_OFS 0x408 | |
| 93 | #define GT_SCS1HD_OFS 0x40c | |
| 94 | #define GT_SCS2LD_OFS 0x410 | |
| 95 | #define GT_SCS2HD_OFS 0x414 | |
| 96 | #define GT_SCS3LD_OFS 0x418 | |
| 97 | #define GT_SCS3HD_OFS 0x41c | |
| 98 | #define GT_CS0LD_OFS 0x420 | |
| 99 | #define GT_CS0HD_OFS 0x424 | |
| 100 | #define GT_CS1LD_OFS 0x428 | |
| 101 | #define GT_CS1HD_OFS 0x42c | |
| 102 | #define GT_CS2LD_OFS 0x430 | |
| 103 | #define GT_CS2HD_OFS 0x434 | |
| 104 | #define GT_CS3LD_OFS 0x438 | |
| 105 | #define GT_CS3HD_OFS 0x43c | |
| 106 | #define GT_BOOTLD_OFS 0x440 | |
| 107 | #define GT_BOOTHD_OFS 0x444 | |
| 108 | ||
| 109 | #define GT_ADERR_OFS 0x470 | |
| 110 | ||
| 111 | /* SDRAM Configuration. */ | |
| 112 | #define GT_SDRAM_CFG_OFS 0x448 | |
| 113 | ||
| 114 | #define GT_SDRAM_OPMODE_OFS 0x474 | |
| 115 | #define GT_SDRAM_BM_OFS 0x478 | |
| 116 | #define GT_SDRAM_ADDRDECODE_OFS 0x47c | |
| 117 | ||
| 118 | /* SDRAM Parameters. */ | |
| 119 | #define GT_SDRAM_B0_OFS 0x44c | |
| 120 | #define GT_SDRAM_B1_OFS 0x450 | |
| 121 | #define GT_SDRAM_B2_OFS 0x454 | |
| 122 | #define GT_SDRAM_B3_OFS 0x458 | |
| 123 | ||
| 124 | /* Device Parameters. */ | |
| 125 | #define GT_DEV_B0_OFS 0x45c | |
| 126 | #define GT_DEV_B1_OFS 0x460 | |
| 127 | #define GT_DEV_B2_OFS 0x464 | |
| 128 | #define GT_DEV_B3_OFS 0x468 | |
| 129 | #define GT_DEV_BOOT_OFS 0x46c | |
| 130 | ||
| 131 | /* ECC. */ | |
| 132 | #define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */ | |
| 133 | #define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */ | |
| 134 | #define GT_ECC_MEM 0x488 /* GT-64120A only */ | |
| 135 | #define GT_ECC_CALC 0x48c /* GT-64120A only */ | |
| 136 | #define GT_ECC_ERRADDR 0x490 /* GT-64120A only */ | |
| 137 | ||
| 138 | /* DMA Record. */ | |
| 139 | #define GT_DMA0_CNT_OFS 0x800 | |
| 140 | #define GT_DMA1_CNT_OFS 0x804 | |
| 141 | #define GT_DMA2_CNT_OFS 0x808 | |
| 142 | #define GT_DMA3_CNT_OFS 0x80c | |
| 143 | #define GT_DMA0_SA_OFS 0x810 | |
| 144 | #define GT_DMA1_SA_OFS 0x814 | |
| 145 | #define GT_DMA2_SA_OFS 0x818 | |
| 146 | #define GT_DMA3_SA_OFS 0x81c | |
| 147 | #define GT_DMA0_DA_OFS 0x820 | |
| 148 | #define GT_DMA1_DA_OFS 0x824 | |
| 149 | #define GT_DMA2_DA_OFS 0x828 | |
| 150 | #define GT_DMA3_DA_OFS 0x82c | |
| 151 | #define GT_DMA0_NEXT_OFS 0x830 | |
| 152 | #define GT_DMA1_NEXT_OFS 0x834 | |
| 153 | #define GT_DMA2_NEXT_OFS 0x838 | |
| 154 | #define GT_DMA3_NEXT_OFS 0x83c | |
| 155 | ||
| 156 | #define GT_DMA0_CUR_OFS 0x870 | |
| 157 | #define GT_DMA1_CUR_OFS 0x874 | |
| 158 | #define GT_DMA2_CUR_OFS 0x878 | |
| 159 | #define GT_DMA3_CUR_OFS 0x87c | |
| 160 | ||
| 161 | /* DMA Channel Control. */ | |
| 162 | #define GT_DMA0_CTRL_OFS 0x840 | |
| 163 | #define GT_DMA1_CTRL_OFS 0x844 | |
| 164 | #define GT_DMA2_CTRL_OFS 0x848 | |
| 165 | #define GT_DMA3_CTRL_OFS 0x84c | |
| 166 | ||
| 167 | /* DMA Arbiter. */ | |
| 168 | #define GT_DMA_ARB_OFS 0x860 | |
| 169 | ||
| 170 | /* Timer/Counter. */ | |
| 171 | #define GT_TC0_OFS 0x850 | |
| 172 | #define GT_TC1_OFS 0x854 | |
| 173 | #define GT_TC2_OFS 0x858 | |
| 174 | #define GT_TC3_OFS 0x85c | |
| 175 | ||
| 176 | #define GT_TC_CONTROL_OFS 0x864 | |
| 177 | ||
| 178 | /* PCI Internal. */ | |
| 179 | #define GT_PCI0_CMD_OFS 0xc00 | |
| 180 | #define GT_PCI0_TOR_OFS 0xc04 | |
| 181 | #define GT_PCI0_BS_SCS10_OFS 0xc08 | |
| 182 | #define GT_PCI0_BS_SCS32_OFS 0xc0c | |
| 183 | #define GT_PCI0_BS_CS20_OFS 0xc10 | |
| 184 | #define GT_PCI0_BS_CS3BT_OFS 0xc14 | |
| 185 | ||
| 186 | #define GT_PCI1_IACK_OFS 0xc30 | |
| 187 | #define GT_PCI0_IACK_OFS 0xc34 | |
| 188 | ||
| 189 | #define GT_PCI0_BARE_OFS 0xc3c | |
| 190 | #define GT_PCI0_PREFMBR_OFS 0xc40 | |
| 191 | ||
| 192 | #define GT_PCI0_SCS10_BAR_OFS 0xc48 | |
| 193 | #define GT_PCI0_SCS32_BAR_OFS 0xc4c | |
| 194 | #define GT_PCI0_CS20_BAR_OFS 0xc50 | |
| 195 | #define GT_PCI0_CS3BT_BAR_OFS 0xc54 | |
| 196 | #define GT_PCI0_SSCS10_BAR_OFS 0xc58 | |
| 197 | #define GT_PCI0_SSCS32_BAR_OFS 0xc5c | |
| 198 | ||
| 199 | #define GT_PCI0_SCS3BT_BAR_OFS 0xc64 | |
| 200 | ||
| 201 | #define GT_PCI1_CMD_OFS 0xc80 | |
| 202 | #define GT_PCI1_TOR_OFS 0xc84 | |
| 203 | #define GT_PCI1_BS_SCS10_OFS 0xc88 | |
| 204 | #define GT_PCI1_BS_SCS32_OFS 0xc8c | |
| 205 | #define GT_PCI1_BS_CS20_OFS 0xc90 | |
| 206 | #define GT_PCI1_BS_CS3BT_OFS 0xc94 | |
| 207 | ||
| 208 | #define GT_PCI1_BARE_OFS 0xcbc | |
| 209 | #define GT_PCI1_PREFMBR_OFS 0xcc0 | |
| 210 | ||
| 211 | #define GT_PCI1_SCS10_BAR_OFS 0xcc8 | |
| 212 | #define GT_PCI1_SCS32_BAR_OFS 0xccc | |
| 213 | #define GT_PCI1_CS20_BAR_OFS 0xcd0 | |
| 214 | #define GT_PCI1_CS3BT_BAR_OFS 0xcd4 | |
| 215 | #define GT_PCI1_SSCS10_BAR_OFS 0xcd8 | |
| 216 | #define GT_PCI1_SSCS32_BAR_OFS 0xcdc | |
| 217 | ||
| 218 | #define GT_PCI1_SCS3BT_BAR_OFS 0xce4 | |
| 219 | ||
| 220 | #define GT_PCI1_CFGADDR_OFS 0xcf0 | |
| 221 | #define GT_PCI1_CFGDATA_OFS 0xcf4 | |
| 222 | #define GT_PCI0_CFGADDR_OFS 0xcf8 | |
| 223 | #define GT_PCI0_CFGDATA_OFS 0xcfc | |
| 224 | ||
| 225 | /* Interrupts. */ | |
| 226 | #define GT_INTRCAUSE_OFS 0xc18 | |
| 227 | #define GT_INTRMASK_OFS 0xc1c | |
| 228 | ||
| 229 | #define GT_PCI0_ICMASK_OFS 0xc24 | |
| 230 | #define GT_PCI0_SERR0MASK_OFS 0xc28 | |
| 231 | ||
| 232 | #define GT_CPU_INTSEL_OFS 0xc70 | |
| 233 | #define GT_PCI0_INTSEL_OFS 0xc74 | |
| 234 | ||
| 235 | #define GT_HINTRCAUSE_OFS 0xc98 | |
| 236 | #define GT_HINTRMASK_OFS 0xc9c | |
| 237 | ||
| 238 | #define GT_PCI0_HICMASK_OFS 0xca4 | |
| 239 | #define GT_PCI1_SERR1MASK_OFS 0xca8 | |
| 240 | ||
| 241 | ||
| 242 | /* | |
| 243 | * I2O Support Registers | |
| 244 | */ | |
| 245 | #define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 | |
| 246 | #define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 | |
| 247 | #define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 | |
| 248 | #define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c | |
| 249 | #define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 | |
| 250 | #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 | |
| 251 | #define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 | |
| 252 | #define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c | |
| 253 | #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 | |
| 254 | #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 | |
| 255 | #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 | |
| 256 | #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 | |
| 257 | #define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 | |
| 258 | #define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 | |
| 259 | #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 | |
| 260 | #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 | |
| 261 | #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 | |
| 262 | #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c | |
| 263 | #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 | |
| 264 | #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 | |
| 265 | #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 | |
| 266 | #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c | |
| 267 | ||
| 268 | #define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10 | |
| 269 | #define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14 | |
| 270 | #define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18 | |
| 271 | #define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c | |
| 272 | #define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20 | |
| 273 | #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24 | |
| 274 | #define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28 | |
| 275 | #define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c | |
| 276 | #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30 | |
| 277 | #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34 | |
| 278 | #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40 | |
| 279 | #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44 | |
| 280 | #define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50 | |
| 281 | #define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54 | |
| 282 | #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60 | |
| 283 | #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64 | |
| 284 | #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68 | |
| 285 | #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c | |
| 286 | #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70 | |
| 287 | #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74 | |
| 288 | #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78 | |
| 289 | #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c | |
| 290 | ||
| 291 | /* | |
| 292 | * Register encodings | |
| 293 | */ | |
| 294 | #define GT_CPU_ENDIAN_SHF 12 | |
| 295 | #define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF) | |
| 296 | #define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK | |
| 297 | #define GT_CPU_WR_SHF 16 | |
| 298 | #define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) | |
| 299 | #define GT_CPU_WR_BIT GT_CPU_WR_MSK | |
| 300 | #define GT_CPU_WR_DXDXDXDX 0 | |
| 301 | #define GT_CPU_WR_DDDD 1 | |
| 302 | ||
| 303 | ||
| 304 | #define GT_PCI_DCRM_SHF 21 | |
| 305 | #define GT_PCI_LD_SHF 0 | |
| 306 | #define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF) | |
| 307 | #define GT_PCI_HD_SHF 0 | |
| 308 | #define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF) | |
| 309 | #define GT_PCI_REMAP_SHF 0 | |
| 310 | #define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF) | |
| 311 | ||
| 312 | ||
| 313 | #define GT_CFGADDR_CFGEN_SHF 31 | |
| 314 | #define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) | |
| 315 | #define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK | |
| 316 | ||
| 317 | #define GT_CFGADDR_BUSNUM_SHF 16 | |
| 318 | #define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) | |
| 319 | ||
| 320 | #define GT_CFGADDR_DEVNUM_SHF 11 | |
| 321 | #define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) | |
| 322 | ||
| 323 | #define GT_CFGADDR_FUNCNUM_SHF 8 | |
| 324 | #define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) | |
| 325 | ||
| 326 | #define GT_CFGADDR_REGNUM_SHF 2 | |
| 327 | #define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) | |
| 328 | ||
| 329 | ||
| 330 | #define GT_SDRAM_BM_ORDER_SHF 2 | |
| 331 | #define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) | |
| 332 | #define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK | |
| 333 | #define GT_SDRAM_BM_ORDER_SUB 1 | |
| 334 | #define GT_SDRAM_BM_ORDER_LIN 0 | |
| 335 | ||
| 336 | #define GT_SDRAM_BM_RSVD_ALL1 0xffb | |
| 337 | ||
| 338 | ||
| 339 | #define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 | |
| 340 | #define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) | |
| 341 | #define GT_SDRAM_ADDRDECODE_ADDR_0 0 | |
| 342 | #define GT_SDRAM_ADDRDECODE_ADDR_1 1 | |
| 343 | #define GT_SDRAM_ADDRDECODE_ADDR_2 2 | |
| 344 | #define GT_SDRAM_ADDRDECODE_ADDR_3 3 | |
| 345 | #define GT_SDRAM_ADDRDECODE_ADDR_4 4 | |
| 346 | #define GT_SDRAM_ADDRDECODE_ADDR_5 5 | |
| 347 | #define GT_SDRAM_ADDRDECODE_ADDR_6 6 | |
| 348 | #define GT_SDRAM_ADDRDECODE_ADDR_7 7 | |
| 349 | ||
| 350 | ||
| 351 | #define GT_SDRAM_B0_CASLAT_SHF 0 | |
| 352 | #define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) | |
| 353 | #define GT_SDRAM_B0_CASLAT_2 1 | |
| 354 | #define GT_SDRAM_B0_CASLAT_3 2 | |
| 355 | ||
| 356 | #define GT_SDRAM_B0_FTDIS_SHF 2 | |
| 357 | #define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) | |
| 358 | #define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK | |
| 359 | ||
| 360 | #define GT_SDRAM_B0_SRASPRCHG_SHF 3 | |
| 361 | #define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) | |
| 362 | #define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK | |
| 363 | #define GT_SDRAM_B0_SRASPRCHG_2 0 | |
| 364 | #define GT_SDRAM_B0_SRASPRCHG_3 1 | |
| 365 | ||
| 366 | #define GT_SDRAM_B0_B0COMPAB_SHF 4 | |
| 367 | #define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) | |
| 368 | #define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK | |
| 369 | ||
| 370 | #define GT_SDRAM_B0_64BITINT_SHF 5 | |
| 371 | #define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) | |
| 372 | #define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK | |
| 373 | #define GT_SDRAM_B0_64BITINT_2 0 | |
| 374 | #define GT_SDRAM_B0_64BITINT_4 1 | |
| 375 | ||
| 376 | #define GT_SDRAM_B0_BW_SHF 6 | |
| 377 | #define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) | |
| 378 | #define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK | |
| 379 | #define GT_SDRAM_B0_BW_32 0 | |
| 380 | #define GT_SDRAM_B0_BW_64 1 | |
| 381 | ||
| 382 | #define GT_SDRAM_B0_BLODD_SHF 7 | |
| 383 | #define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) | |
| 384 | #define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK | |
| 385 | ||
| 386 | #define GT_SDRAM_B0_PAR_SHF 8 | |
| 387 | #define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) | |
| 388 | #define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK | |
| 389 | ||
| 390 | #define GT_SDRAM_B0_BYPASS_SHF 9 | |
| 391 | #define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) | |
| 392 | #define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK | |
| 393 | ||
| 394 | #define GT_SDRAM_B0_SRAS2SCAS_SHF 10 | |
| 395 | #define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) | |
| 396 | #define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK | |
| 397 | #define GT_SDRAM_B0_SRAS2SCAS_2 0 | |
| 398 | #define GT_SDRAM_B0_SRAS2SCAS_3 1 | |
| 399 | ||
| 400 | #define GT_SDRAM_B0_SIZE_SHF 11 | |
| 401 | #define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) | |
| 402 | #define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK | |
| 403 | #define GT_SDRAM_B0_SIZE_16M 0 | |
| 404 | #define GT_SDRAM_B0_SIZE_64M 1 | |
| 405 | ||
| 406 | #define GT_SDRAM_B0_EXTPAR_SHF 12 | |
| 407 | #define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) | |
| 408 | #define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK | |
| 409 | ||
| 410 | #define GT_SDRAM_B0_BLEN_SHF 13 | |
| 411 | #define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) | |
| 412 | #define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK | |
| 413 | #define GT_SDRAM_B0_BLEN_8 0 | |
| 414 | #define GT_SDRAM_B0_BLEN_4 1 | |
| 415 | ||
| 416 | ||
| 417 | #define GT_SDRAM_CFG_REFINT_SHF 0 | |
| 418 | #define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) | |
| 419 | ||
| 420 | #define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 | |
| 421 | #define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) | |
| 422 | #define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK | |
| 423 | ||
| 424 | #define GT_SDRAM_CFG_RMW_SHF 15 | |
| 425 | #define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) | |
| 426 | #define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK | |
| 427 | ||
| 428 | #define GT_SDRAM_CFG_NONSTAGREF_SHF 16 | |
| 429 | #define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) | |
| 430 | #define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK | |
| 431 | ||
| 432 | #define GT_SDRAM_CFG_DUPCNTL_SHF 19 | |
| 433 | #define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) | |
| 434 | #define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK | |
| 435 | ||
| 436 | #define GT_SDRAM_CFG_DUPBA_SHF 20 | |
| 437 | #define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) | |
| 438 | #define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK | |
| 439 | ||
| 440 | #define GT_SDRAM_CFG_DUPEOT0_SHF 21 | |
| 441 | #define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) | |
| 442 | #define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK | |
| 443 | ||
| 444 | #define GT_SDRAM_CFG_DUPEOT1_SHF 22 | |
| 445 | #define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) | |
| 446 | #define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK | |
| 447 | ||
| 448 | #define GT_SDRAM_OPMODE_OP_SHF 0 | |
| 449 | #define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) | |
| 450 | #define GT_SDRAM_OPMODE_OP_NORMAL 0 | |
| 451 | #define GT_SDRAM_OPMODE_OP_NOP 1 | |
| 452 | #define GT_SDRAM_OPMODE_OP_PRCHG 2 | |
| 453 | #define GT_SDRAM_OPMODE_OP_MODE 3 | |
| 454 | #define GT_SDRAM_OPMODE_OP_CBR 4 | |
| 455 | ||
| 56ae5833 YY |
456 | #define GT_TC_CONTROL_ENTC0_SHF 0 |
| 457 | #define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF) | |
| 458 | #define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK | |
| 459 | #define GT_TC_CONTROL_SELTC0_SHF 1 | |
| 460 | #define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF) | |
| 461 | #define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK | |
| 462 | ||
| 1da177e4 LT |
463 | |
| 464 | #define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 | |
| 465 | #define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) | |
| 466 | #define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK | |
| 467 | ||
| 468 | #define GT_PCI0_BARE_SWSCS32DIS_SHF 1 | |
| 469 | #define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) | |
| 470 | #define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK | |
| 471 | ||
| 472 | #define GT_PCI0_BARE_SWSCS10DIS_SHF 2 | |
| 473 | #define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) | |
| 474 | #define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK | |
| 475 | ||
| 476 | #define GT_PCI0_BARE_INTIODIS_SHF 3 | |
| 477 | #define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) | |
| 478 | #define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK | |
| 479 | ||
| 480 | #define GT_PCI0_BARE_INTMEMDIS_SHF 4 | |
| 481 | #define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) | |
| 482 | #define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK | |
| 483 | ||
| 484 | #define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 | |
| 485 | #define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) | |
| 486 | #define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK | |
| 487 | ||
| 488 | #define GT_PCI0_BARE_CS20DIS_SHF 6 | |
| 489 | #define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) | |
| 490 | #define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK | |
| 491 | ||
| 492 | #define GT_PCI0_BARE_SCS32DIS_SHF 7 | |
| 493 | #define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) | |
| 494 | #define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK | |
| 495 | ||
| 496 | #define GT_PCI0_BARE_SCS10DIS_SHF 8 | |
| 497 | #define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) | |
| 498 | #define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK | |
| 499 | ||
| 500 | ||
| 501 | #define GT_INTRCAUSE_MASABORT0_SHF 18 | |
| 502 | #define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) | |
| 503 | #define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK | |
| 504 | ||
| 505 | #define GT_INTRCAUSE_TARABORT0_SHF 19 | |
| 506 | #define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) | |
| 507 | #define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK | |
| 508 | ||
| 509 | ||
| 510 | #define GT_PCI0_CFGADDR_REGNUM_SHF 2 | |
| 511 | #define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) | |
| 512 | #define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 | |
| 513 | #define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | |
| 514 | #define GT_PCI0_CFGADDR_DEVNUM_SHF 11 | |
| 515 | #define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) | |
| 516 | #define GT_PCI0_CFGADDR_BUSNUM_SHF 16 | |
| 517 | #define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) | |
| 518 | #define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 | |
| 519 | #define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) | |
| 520 | #define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK | |
| 521 | ||
| 522 | #define GT_PCI0_CMD_MBYTESWAP_SHF 0 | |
| 523 | #define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) | |
| 524 | #define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK | |
| 525 | #define GT_PCI0_CMD_MWORDSWAP_SHF 10 | |
| 526 | #define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF) | |
| 527 | #define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK | |
| 528 | #define GT_PCI0_CMD_SBYTESWAP_SHF 16 | |
| 529 | #define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF) | |
| 530 | #define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK | |
| 531 | #define GT_PCI0_CMD_SWORDSWAP_SHF 11 | |
| 532 | #define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) | |
| 533 | #define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK | |
| 534 | ||
| 56ae5833 YY |
535 | #define GT_INTR_T0EXP_SHF 8 |
| 536 | #define GT_INTR_T0EXP_MSK (MSK(1) << GT_INTR_T0EXP_SHF) | |
| 537 | #define GT_INTR_T0EXP_BIT GT_INTR_T0EXP_MSK | |
| 538 | #define GT_INTR_RETRYCTR0_SHF 20 | |
| 539 | #define GT_INTR_RETRYCTR0_MSK (MSK(1) << GT_INTR_RETRYCTR0_SHF) | |
| 540 | #define GT_INTR_RETRYCTR0_BIT GT_INTR_RETRYCTR0_MSK | |
| 541 | ||
| 1da177e4 LT |
542 | /* |
| 543 | * Misc | |
| 544 | */ | |
| 545 | #define GT_DEF_PCI0_IO_BASE 0x10000000UL | |
| 546 | #define GT_DEF_PCI0_IO_SIZE 0x02000000UL | |
| 547 | #define GT_DEF_PCI0_MEM0_BASE 0x12000000UL | |
| 548 | #define GT_DEF_PCI0_MEM0_SIZE 0x02000000UL | |
| 549 | #define GT_DEF_BASE 0x14000000UL | |
| 550 | ||
| 551 | #define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ | |
| 552 | #define GT_LATTIM_MIN 6 /* Minimum lat */ | |
| 553 | ||
| 554 | /* | |
| 555 | * The gt64120_dep.h file must define the following macros | |
| 556 | * | |
| 557 | * GT_READ(ofs, data_pointer) | |
| 558 | * GT_WRITE(ofs, data) - read/write GT64120 registers in 32bit | |
| 559 | * | |
| 560 | * TIMER - gt64120 timer irq, temporary solution until | |
| 561 | * full gt64120 cascade interrupt support is in place | |
| 562 | */ | |
| 563 | ||
| 564 | #include <mach-gt64120.h> | |
| 565 | ||
| 566 | /* | |
| 567 | * Because of an error/peculiarity in the Galileo chip, we need to swap the | |
| 568 | * bytes when running bigendian. We also provide non-swapping versions. | |
| 569 | */ | |
| 570 | #define __GT_READ(ofs) \ | |
| 571 | (*(volatile u32 *)(GT64120_BASE+(ofs))) | |
| 572 | #define __GT_WRITE(ofs, data) \ | |
| 573 | do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0) | |
| 574 | #define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs)) | |
| 575 | #define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data)) | |
| 576 | ||
| 1097c6ac YY |
577 | extern void gt641xx_set_base_clock(unsigned int clock); |
| 578 | extern int gt641xx_timer0_state(void); | |
| 579 | ||
| 1da177e4 | 580 | #endif /* _ASM_GT64120_H */ |