Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public | |
3 | * License. See the file "COPYING" in the main directory of this archive | |
4 | * for more details. | |
5 | * | |
6 | * Copyright (C) 2003, 2004 Ralf Baechle | |
4194318c | 7 | * Copyright (C) 2004 Maciej W. Rozycki |
1da177e4 LT |
8 | */ |
9 | #ifndef __ASM_CPU_FEATURES_H | |
10 | #define __ASM_CPU_FEATURES_H | |
11 | ||
12 | #include <linux/config.h> | |
13 | ||
14 | #include <asm/cpu.h> | |
15 | #include <asm/cpu-info.h> | |
16 | #include <cpu-feature-overrides.h> | |
17 | ||
18 | /* | |
19 | * SMP assumption: Options of CPU 0 are a superset of all processors. | |
20 | * This is true for all known MIPS systems. | |
21 | */ | |
22 | #ifndef cpu_has_tlb | |
23 | #define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB) | |
24 | #endif | |
25 | #ifndef cpu_has_4kex | |
26 | #define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX) | |
27 | #endif | |
02cf2119 RB |
28 | #ifndef cpu_has_3k_cache |
29 | #define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE) | |
30 | #endif | |
31 | #define cpu_has_6k_cache 0 | |
32 | #define cpu_has_8k_cache 0 | |
33 | #ifndef cpu_has_4k_cache | |
34 | #define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE) | |
35 | #endif | |
36 | #ifndef cpu_has_tx39_cache | |
37 | #define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) | |
38 | #endif | |
39 | #ifndef cpu_has_sb1_cache | |
40 | #define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE) | |
1da177e4 LT |
41 | #endif |
42 | #ifndef cpu_has_fpu | |
43 | #define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU) | |
44 | #endif | |
45 | #ifndef cpu_has_32fpr | |
46 | #define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR) | |
47 | #endif | |
48 | #ifndef cpu_has_counter | |
49 | #define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER) | |
50 | #endif | |
51 | #ifndef cpu_has_watch | |
52 | #define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH) | |
53 | #endif | |
1da177e4 LT |
54 | #ifndef cpu_has_divec |
55 | #define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC) | |
56 | #endif | |
57 | #ifndef cpu_has_vce | |
58 | #define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE) | |
59 | #endif | |
60 | #ifndef cpu_has_cache_cdex_p | |
61 | #define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P) | |
62 | #endif | |
63 | #ifndef cpu_has_cache_cdex_s | |
64 | #define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S) | |
65 | #endif | |
66 | #ifndef cpu_has_prefetch | |
67 | #define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH) | |
68 | #endif | |
69 | #ifndef cpu_has_mcheck | |
70 | #define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK) | |
71 | #endif | |
72 | #ifndef cpu_has_ejtag | |
73 | #define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG) | |
74 | #endif | |
75 | #ifndef cpu_has_llsc | |
76 | #define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC) | |
77 | #endif | |
4194318c RB |
78 | #ifndef cpu_has_mips16 |
79 | #define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16) | |
80 | #endif | |
81 | #ifndef cpu_has_mdmx | |
82 | #define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX) | |
83 | #endif | |
84 | #ifndef cpu_has_mips3d | |
85 | #define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D) | |
86 | #endif | |
87 | #ifndef cpu_has_smartmips | |
88 | #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) | |
89 | #endif | |
1da177e4 LT |
90 | #ifndef cpu_has_vtag_icache |
91 | #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) | |
92 | #endif | |
93 | #ifndef cpu_has_dc_aliases | |
94 | #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) | |
95 | #endif | |
96 | #ifndef cpu_has_ic_fills_f_dc | |
97 | #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) | |
98 | #endif | |
de62893b AN |
99 | #ifndef cpu_has_pindexed_dcache |
100 | #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) | |
101 | #endif | |
1da177e4 LT |
102 | |
103 | /* | |
104 | * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors | |
105 | * such as the R10000 have I-Caches that snoop local stores; the embedded ones | |
106 | * don't. For maintaining I-cache coherency this means we need to flush the | |
107 | * D-cache all the way back to whever the I-cache does refills from, so the | |
108 | * I-cache has a chance to see the new data at all. Then we have to flush the | |
109 | * I-cache also. | |
110 | * Note we may have been rescheduled and may no longer be running on the CPU | |
111 | * that did the store so we can't optimize this into only doing the flush on | |
112 | * the local CPU. | |
113 | */ | |
114 | #ifndef cpu_icache_snoops_remote_store | |
115 | #ifdef CONFIG_SMP | |
116 | #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) | |
117 | #else | |
118 | #define cpu_icache_snoops_remote_store 1 | |
119 | #endif | |
120 | #endif | |
121 | ||
0401572a RB |
122 | # ifndef cpu_has_mips32r1 |
123 | # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) | |
124 | # endif | |
125 | # ifndef cpu_has_mips32r2 | |
126 | # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) | |
127 | # endif | |
128 | # ifndef cpu_has_mips64r1 | |
129 | # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) | |
130 | # endif | |
131 | # ifndef cpu_has_mips64r2 | |
132 | # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) | |
133 | # endif | |
134 | ||
135 | /* | |
136 | * Shortcuts ... | |
137 | */ | |
138 | #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2) | |
139 | #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2) | |
140 | #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) | |
141 | #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) | |
142 | ||
e50c0a8f RB |
143 | #ifndef cpu_has_dsp |
144 | #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) | |
145 | #endif | |
146 | ||
8f40611d RB |
147 | #ifdef CONFIG_MIPS_MT |
148 | #ifndef cpu_has_mipsmt | |
149 | # define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT) | |
150 | #endif | |
151 | #else | |
152 | # define cpu_has_mipsmt 0 | |
153 | #endif | |
154 | ||
875d43e7 | 155 | #ifdef CONFIG_32BIT |
1da177e4 LT |
156 | # ifndef cpu_has_nofpuex |
157 | # define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX) | |
158 | # endif | |
159 | # ifndef cpu_has_64bits | |
160 | # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) | |
161 | # endif | |
162 | # ifndef cpu_has_64bit_zero_reg | |
163 | # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) | |
164 | # endif | |
165 | # ifndef cpu_has_64bit_gp_regs | |
166 | # define cpu_has_64bit_gp_regs 0 | |
167 | # endif | |
168 | # ifndef cpu_has_64bit_addresses | |
169 | # define cpu_has_64bit_addresses 0 | |
170 | # endif | |
171 | #endif | |
172 | ||
875d43e7 | 173 | #ifdef CONFIG_64BIT |
1da177e4 LT |
174 | # ifndef cpu_has_nofpuex |
175 | # define cpu_has_nofpuex 0 | |
176 | # endif | |
177 | # ifndef cpu_has_64bits | |
178 | # define cpu_has_64bits 1 | |
179 | # endif | |
180 | # ifndef cpu_has_64bit_zero_reg | |
181 | # define cpu_has_64bit_zero_reg 1 | |
182 | # endif | |
183 | # ifndef cpu_has_64bit_gp_regs | |
184 | # define cpu_has_64bit_gp_regs 1 | |
185 | # endif | |
186 | # ifndef cpu_has_64bit_addresses | |
187 | # define cpu_has_64bit_addresses 1 | |
188 | # endif | |
189 | #endif | |
190 | ||
8f40611d RB |
191 | #ifdef CONFIG_CPU_MIPSR2 |
192 | # if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) | |
193 | # define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) | |
194 | # else | |
195 | # define cpu_has_vint 0 | |
196 | # endif | |
197 | # if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) | |
198 | # define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) | |
199 | # else | |
200 | # define cpu_has_veic 0 | |
201 | # endif | |
202 | #else | |
203 | # define cpu_has_vint 0 | |
204 | # define cpu_has_veic 0 | |
205 | #endif | |
206 | ||
1da177e4 LT |
207 | #ifndef cpu_has_subset_pcaches |
208 | #define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES) | |
209 | #endif | |
210 | ||
211 | #ifndef cpu_dcache_line_size | |
212 | #define cpu_dcache_line_size() current_cpu_data.dcache.linesz | |
213 | #endif | |
214 | #ifndef cpu_icache_line_size | |
215 | #define cpu_icache_line_size() current_cpu_data.icache.linesz | |
216 | #endif | |
217 | #ifndef cpu_scache_line_size | |
218 | #define cpu_scache_line_size() current_cpu_data.scache.linesz | |
219 | #endif | |
220 | ||
221 | #endif /* __ASM_CPU_FEATURES_H */ |