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[MIPS] Add empty argument parenthesis to GCC_IMM_ASM
[linux-2.6-block.git] / include / asm-mips / cpu-features.h
CommitLineData
1da177e4
LT		 1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Ralf Baechle
4194318c 7 * Copyright (C) 2004 Maciej W. Rozycki
1da177e4
LT		 8 */
9#ifndef __ASM_CPU_FEATURES_H
10#define __ASM_CPU_FEATURES_H
11
1da177e4
LT		 12#include <asm/cpu.h>
13#include <asm/cpu-info.h>
14#include <cpu-feature-overrides.h>
15
10cc3529
RB		 16#ifndef current_cpu_type
17#define current_cpu_type() current_cpu_data.cputype
18#endif
19
1da177e4
LT		 20/*
21 * SMP assumption: Options of CPU 0 are a superset of all processors.
22 * This is true for all known MIPS systems.
23 */
24#ifndef cpu_has_tlb
25#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
26#endif
27#ifndef cpu_has_4kex
28#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
29#endif
02cf2119
RB		 30#ifndef cpu_has_3k_cache
31#define cpu_has_3k_cache (cpu_data[0].options & MIPS_CPU_3K_CACHE)
32#endif
33#define cpu_has_6k_cache 0
34#define cpu_has_8k_cache 0
35#ifndef cpu_has_4k_cache
36#define cpu_has_4k_cache (cpu_data[0].options & MIPS_CPU_4K_CACHE)
37#endif
38#ifndef cpu_has_tx39_cache
39#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
40#endif
1da177e4 41#ifndef cpu_has_fpu
f088fc84 42#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
53dc8028
AN		 43#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
44#else
45#define raw_cpu_has_fpu cpu_has_fpu
1da177e4
LT		 46#endif
47#ifndef cpu_has_32fpr
48#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
49#endif
50#ifndef cpu_has_counter
51#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
52#endif
53#ifndef cpu_has_watch
54#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
55#endif
1da177e4
LT		 56#ifndef cpu_has_divec
57#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
58#endif
59#ifndef cpu_has_vce
60#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
61#endif
62#ifndef cpu_has_cache_cdex_p
63#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
64#endif
65#ifndef cpu_has_cache_cdex_s
66#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
67#endif
68#ifndef cpu_has_prefetch
69#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
70#endif
71#ifndef cpu_has_mcheck
72#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
73#endif
74#ifndef cpu_has_ejtag
75#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
76#endif
77#ifndef cpu_has_llsc
78#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
79#endif
4194318c
RB		 80#ifndef cpu_has_mips16
81#define cpu_has_mips16 (cpu_data[0].ases & MIPS_ASE_MIPS16)
82#endif
83#ifndef cpu_has_mdmx
84#define cpu_has_mdmx (cpu_data[0].ases & MIPS_ASE_MDMX)
85#endif
86#ifndef cpu_has_mips3d
87#define cpu_has_mips3d (cpu_data[0].ases & MIPS_ASE_MIPS3D)
88#endif
89#ifndef cpu_has_smartmips
90#define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
91#endif
1da177e4
LT		 92#ifndef cpu_has_vtag_icache
93#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
94#endif
95#ifndef cpu_has_dc_aliases
96#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
97#endif
98#ifndef cpu_has_ic_fills_f_dc
99#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
100#endif
de62893b
AN		 101#ifndef cpu_has_pindexed_dcache
102#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
103#endif
1da177e4
LT		 104
105/*
106 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
107 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
108 * don't. For maintaining I-cache coherency this means we need to flush the
109 * D-cache all the way back to whever the I-cache does refills from, so the
110 * I-cache has a chance to see the new data at all. Then we have to flush the
111 * I-cache also.
112 * Note we may have been rescheduled and may no longer be running on the CPU
113 * that did the store so we can't optimize this into only doing the flush on
114 * the local CPU.
115 */
116#ifndef cpu_icache_snoops_remote_store
117#ifdef CONFIG_SMP
118#define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
119#else
120#define cpu_icache_snoops_remote_store 1
121#endif
122#endif
123
0401572a
RB		 124# ifndef cpu_has_mips32r1
125# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
126# endif
127# ifndef cpu_has_mips32r2
128# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
129# endif
130# ifndef cpu_has_mips64r1
131# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
132# endif
133# ifndef cpu_has_mips64r2
134# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
135# endif
136
137/*
138 * Shortcuts ...
139 */
140#define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
141#define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
142#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
143#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
144
e50c0a8f
RB		 145#ifndef cpu_has_dsp
146#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
147#endif
148
8f40611d 149#ifndef cpu_has_mipsmt
2e128ded 150#define cpu_has_mipsmt (cpu_data[0].ases & MIPS_ASE_MIPSMT)
8f40611d
RB		 151#endif
152
a3692020
RB		 153#ifndef cpu_has_userlocal
154#define cpu_has_userlocal (cpu_data[0].options & MIPS_CPU_ULRI)
155#endif
156
875d43e7 157#ifdef CONFIG_32BIT
1da177e4
LT		 158# ifndef cpu_has_nofpuex
159# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
160# endif
161# ifndef cpu_has_64bits
162# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
163# endif
164# ifndef cpu_has_64bit_zero_reg
165# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
166# endif
167# ifndef cpu_has_64bit_gp_regs
168# define cpu_has_64bit_gp_regs 0
169# endif
170# ifndef cpu_has_64bit_addresses
171# define cpu_has_64bit_addresses 0
172# endif
173#endif
174
875d43e7 175#ifdef CONFIG_64BIT
1da177e4
LT		 176# ifndef cpu_has_nofpuex
177# define cpu_has_nofpuex 0
178# endif
179# ifndef cpu_has_64bits
180# define cpu_has_64bits 1
181# endif
182# ifndef cpu_has_64bit_zero_reg
183# define cpu_has_64bit_zero_reg 1
184# endif
185# ifndef cpu_has_64bit_gp_regs
186# define cpu_has_64bit_gp_regs 1
187# endif
188# ifndef cpu_has_64bit_addresses
189# define cpu_has_64bit_addresses 1
190# endif
191#endif
192
f41ae0b2
RB		 193#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
194# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT)
195#elif !defined(cpu_has_vint)
8f40611d 196# define cpu_has_vint 0
f41ae0b2
RB		 197#endif
198
199#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
200# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC)
201#elif !defined(cpu_has_veic)
8f40611d
RB		 202# define cpu_has_veic 0
203#endif
204
fc5d2d27
RB		 205#ifndef cpu_has_inclusive_pcaches
206#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
1da177e4
LT		 207#endif
208
209#ifndef cpu_dcache_line_size
54fd6441 210#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
1da177e4
LT		 211#endif
212#ifndef cpu_icache_line_size
54fd6441 213#define cpu_icache_line_size() cpu_data[0].icache.linesz
1da177e4
LT		 214#endif
215#ifndef cpu_scache_line_size
54fd6441 216#define cpu_scache_line_size() cpu_data[0].scache.linesz
1da177e4
LT		 217#endif
218
219#endif /* __ASM_CPU_FEATURES_H */
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